CN101369452B - Circuit and method for reducing SRAM power consumption - Google Patents
Circuit and method for reducing SRAM power consumption Download PDFInfo
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- CN101369452B CN101369452B CN2008102224270A CN200810222427A CN101369452B CN 101369452 B CN101369452 B CN 101369452B CN 2008102224270 A CN2008102224270 A CN 2008102224270A CN 200810222427 A CN200810222427 A CN 200810222427A CN 101369452 B CN101369452 B CN 101369452B
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Abstract
The invention provides a circuit for reducing SRAM power consumption and method thereof, the circuit comprises a reading and writing access unit for performing reading and writing operations to the SRAM and outputting a triggering signal; a low power consumption mode control unit for receiving the triggering signal of the reading and writing access unit and generating a clock switch signal; a clock switch unit for receiving the clock switch signal and performing the clock switch for the SRAM. The invention provides a high frequency clock for the SRAM when performing the reading and writing operations; switches the clock to low frequency when closing the reading and writing operations for the SRAM, and realizes that the SRAM can enter into the low power consumption mode and can be awaken quickly.
Description
Technical field
The present invention relates to static RAM control field, particularly relate to a kind of circuit and method of the SRAM of reduction power consumption.
Background technology
As Embedded Application, the development trend of internal memory is littler, the more power saving of area occupied, and higher these 3 directions of efficient develop.Except flash memory, the consumption maximum be as SOC (System On Chip, multicomputer system level chip) and semiconductor core flake products high-speed cache commonly used, be main flow with SRAM (StaticRandom-Access Memory, static RAM).Along with the improvement development of process integration technology, semiconductor is already made the trend of integrated circuit at present, is to use the internal memory of one-transistor framework, be 1T SRAM, it is because cost is lower, and chip area is little, help significantly expanding capacity, therefore in the SOC system, obtained using widely.Yet the power consumption of SRAM is maximum in the total system power consumption, even surpasses 60%.Therefore, for the system design trend of current low-power consumption small size, the power consumption that how to reduce SRAM has become a problem that needs to be resolved hurrily.
SRAM has read-write state and keeps two kinds of patterns of state, when being in when keeping state, as long as add lower voltage, just can keep data wherein not lose; And when being in read-write state, then need the clock (as 100MHZ) of upper frequency could keep the state of its operate as normal.Yet there is quite a few SRAM not need to be operated in high frequency clock all the time in the system, that is to say, at part-time, SRAM can slow running even is quit work, if at this moment continuing as SRAM keeps high frequency clock and will cause very big power wastage, this is because in COMS (Complementary Metal OxideSemiconductor, complementary metal oxide semiconductor (CMOS)) circuit, power consumption is directly proportional with clock.
In the prior art, for reducing the power consumption of SRAM, adopt following method usually:
High-speed cache is divided into the block that quantity does not wait, utilizes the memory field to add the mode of counter.When specific memory block was read and write, counter will make zero, and counter is when reaching critical value, and then decidable is the demand of not read and write between short-term, can further enter low-power consumption mode, or will close the power supply of particular memory block.Yet close the data loss that the block power supply might cause being closed block, and just in case program has a large amount of high-speed cache read-write demands suddenly, then might cause the cache capacity deficiency because pent block is too much, making needs the number of times of repetitive read-write to increase, and has increased power consumption on the contrary.And SRAM enters and withdraw from low-power consumption mode all needs long time-delay, thereby has influence on the bandwidth of SRAM.
In a word, need the urgent technical matters that solves of those skilled in the art to be exactly at present: the circuit and the method that how to propose a kind of SRAM of reduction power consumption with innovating, reducing the power consumption of SRAM effectively, and can make SRAM enter low-power consumption mode fast, and can wake up apace.
Summary of the invention
Technical matters to be solved by this invention provides a kind of circuit and method of the SRAM of reduction power consumption, reducing the power consumption of SRAM effectively, and can make SRAM enter low-power consumption mode fast, and can wake up apace.
In order to address the above problem, embodiments of the invention provide a kind of circuit of the SRAM of reduction power consumption, and this circuit comprises:
The read and write access unit is used for SRAM is carried out read-write operation, and the output trigger pip;
The low-power consumption mode control module is used to receive the trigger pip of read and write access unit, produces the clock switching signal;
The clock switch unit is used for the receive clock switching signal, SRAM is carried out clock switch.
Preferably, described trigger pip is exported by the RS pin; If RS is output as low level, expression SRAM has read and write access; If RS is output as high level, expression SRAM read and write access finishes.
Preferably, described clock switches to the switching between high frequency clock CLK1 and the low-frequency clock CLK2; When RS output trigger pip was low level, the clock of SRAM switched to high frequency from low frequency; When RS output trigger pip was high level, the clock of SRAM switched to low frequency from high frequency.
Incision when preferably, described high frequency clock CLK1 is before low-frequency clock CLK2 finishes a clock period.
Preferably, described low-power consumption mode control module specifically comprises: first D flip-flop, and its input end of clock connects high frequency clock CLK1, and data input pin connects RS trigger pip, data output end output signal SD1; Second D flip-flop, its input end of clock connects high frequency clock CLK1, and data input pin connects the output signal SD1 of first D flip-flop, data output end output signal SD2; With door, be used for SD1 signal and SD2 signal and, output clock switching signal.
Preferably, described clock switch unit specifically comprises: the 3rd D flip-flop, and its input end of clock connects high frequency clock CLK1, and data input pin connects low-frequency clock CLK2; The 4th D flip-flop, its input end of clock connects high frequency clock CLK1, and data input pin connects the 3rd D flip-flop output signal; Selector switch, it selects control signal is the clock switching signal, input end is the output signal and the high frequency clock CLK1 of the 4th D flip-flop, and its clock signal is offered SRAM.
Further, the circuit of described reduction SRAM power consumption, also comprise: clock synchronization module, it is at the data input pin that low-frequency clock CLK2 is inserted the 3rd D flip-flop D3, with high frequency clock CLK1 is inserted before the input end of clock of the 3rd D flip-flop D3, low-frequency clock CLK2 is carried out in high frequency clock CLK1 territory synchronously.
According to embodiments of the invention, a kind of method of the SRAM of reduction power consumption is also disclosed, may further comprise the steps: when receiving the SRAM read-write operation request, the output low level trigger pip, the described low level trigger pip of foundation switches to high frequency with the clock of SRAM from low frequency; When the SRAM read-write operation finishes, the output high trigger signal, the described high trigger signal of foundation switches to low frequency with the clock of SRAM from high frequency.
Preferably, described trigger pip is exported by the RS pin; Described low level trigger pip is that RS is output as low level; Described high trigger signal is that RS is output as high level.
Further, described method also comprises: before switching clock, low-frequency clock is carried out in the high frequency clock territory synchronously.
Incision when preferably, described high frequency clock is before low-frequency clock is finished a clock period.
Compared with prior art, the present invention has the following advantages:
The present invention provides high frequency clock by when SRAM has read-write operation to it; When the SRAM read-write operation finishes, its clock is switched to low frequency, thereby reduced the power consumption of SRAM, and realize that SRAM enters low-power consumption mode fast, and can wake up apace, minimizing takies the SRAM bandwidth, has improved the access efficiency of system.
Description of drawings
Fig. 1 is the circuit general structure block diagram of a kind of SRAM of reduction power consumption of the present invention;
Fig. 2 is the circuit diagram of low-power consumption mode control module in the circuit embodiments of a kind of SRAM of reduction power consumption of the present invention;
Fig. 3 is the signal timing diagram that adopts the circuit of low-power consumption mode control module shown in Figure 2;
Fig. 4 is the circuit diagram of clock switch unit in the circuit embodiments of a kind of SRAM of reduction power consumption of the present invention;
Fig. 5 is the signal timing diagram that adopts the circuit of clock switch unit shown in Figure 4.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
Core concept of the present invention is: when SRAM has read-write operation, provide high frequency clock to it; When the SRAM read-write operation finishes, its clock is switched to low frequency, and realize that SRAM enters low-power consumption mode fast, and can wake up apace.
With reference to Fig. 1, show the circuit of a kind of SRAM of reduction power consumption of the present invention, this circuit specifically can comprise: read and write access unit 100, low-power consumption mode control module 110 and clock switch unit 120.Wherein, read and write access unit 100 is used for sram cell 130 is carried out read-write operation, and the output trigger pip; Low-power consumption mode control module 110 is used to receive the trigger pip of read and write access unit 100, produces the clock switching signal; Clock switch unit 120 is used for the receive clock switching signal, sram cell 130 is carried out clock switch.
Preferably, described trigger pip is exported by the RS pin; If RS is output as low level, expression SRAM has read and write access; If RS is output as high level, expression SRAM read and write access finishes.
Further, when described trigger pip RS is low level, produce the clock switching signal that low-frequency clock is switched to high frequency clock; When described trigger pip RS is high level, produce the clock switching signal that high frequency clock is switched to low-frequency clock.
With reference to Fig. 2, show the specific implementation circuit of low-power consumption mode control module in the preferred embodiment of the present invention.This circuit specifically can comprise: the first D flip-flop D1, the second D flip-flop D2 and one and door 210.Wherein, the input end of clock of the first D flip-flop D1 connects high frequency clock CLK1, and data input pin connects RS trigger pip, data output end output signal SD1; The input end of clock of the second D flip-flop D2 connects high frequency clock CLK1, and data input pin connects the output signal SD1 of the first D flip-flop D1, data output end output signal SD2; With door 210, with SD1 signal and SD2 signal with, promptly be output as clock switching signal DKS with the result.
Fig. 3 shows the signal timing diagram of the realization circuit of low-power consumption mode control module in the corresponding diagram 2.When trigger pip RS was low level, the first D flip-flop D1 and second D flip-flop D2 output were the SD1 and the SD2 of low level signal.Two low level signal SD1 carry out producing clock control signal DKS with the operation back with door 210 through one with SD2, and be low level this moment.
Need to prove, the specific implementation circuit of low-power consumption mode control module shown in Figure 2 only is a preferred embodiment of the present invention, in actual applications, those skilled in the art can also adopt other method to produce the clock control signal that switches clock, repeat no more herein.
Fig. 4 shows the specific implementation circuit of clock switch unit in the preferred embodiment of the present invention.This circuit specifically can comprise: the 3rd D flip-flop D3, the 4th D flip-flop D4 and a selector switch SEL.Wherein, the clock signal of the 3rd D flip-flop D3, the 4th D flip-flop D4 is high frequency clock CLK1.The data input pin of the 3rd D flip-flop D3 inserts low-frequency clock CLK2, through logical operation, its output signal is inserted the data input pin of the 4th D flip-flop D4.The 4th D flip-flop D4 is through logical operation, output signal is inserted 1 port of selector switch, and 0 port of selector switch inserts high frequency clock CLK1, simultaneously clock switching signal DKS is inserted selector switch SEL and select control signal as it, the signal of the final output of selector switch SEL is the clock signal of sram cell.Further, at the data input pin that low-frequency clock CLK2 is inserted the 3rd D flip-flop D3, with high frequency clock CLK1 is inserted before the input end of clock of the 3rd D flip-flop D3, low-frequency clock CLK2 is carried out in high frequency clock CLK1 territory synchronously, to avoid in the switching of clock, introducing burr or sequential mistake.
Shown in Figure 5 is the signal timing diagram of corresponding diagram 4 clock switch circuits.When clock switching signal DKS is low level, selector switch SEL output high frequency clock CLK1.Obviously, when clock switching signal DKS is high level, selector switch SEL output low frequency clock CLK2.By in the signal timing diagram of Fig. 5 as can be seen, the clock signal SELC waveform of the sram cell of final output is smooth, this clock switch circuit has avoided introducing the defective of burr or sequential mistake in the switching of clock.The more important thing is, utilize this clock switch circuit in the embodiment of the invention, can before low-frequency clock is finished a complete cycle, just switch to high frequency, guarantee after trigger pip RS finishes, still to have the rising edge of a high frequency clock simultaneously, realize SRAM clock switching fast.
Correspondingly, the invention provides a kind of method that reduces the static RAM power consumption, specifically may further comprise the steps: when receiving the SRAM read-write operation request, the output low level trigger pip, the described low level trigger pip of foundation switches to high frequency with the clock of SRAM from low frequency; When the SRAM read-write operation finishes, the output high trigger signal, the described high trigger signal of foundation switches to low frequency with the clock of SRAM from high frequency.
Preferably, in the embodiment of the invention, described trigger pip is exported by the RS pin; Described low level trigger pip is that RS is output as low level; Described high trigger signal is that RS is output as high level.And, before switching clock, at first low-frequency clock is carried out in the high frequency clock territory synchronously, thereby avoids the defective of in the switching of clock introducing burr or sequential mistake.And, can before finishing a complete cycle, low-frequency clock just switch to high frequency, guarantee after trigger pip RS finishes, still to have the rising edge of a high frequency clock simultaneously, realize SRAM clock switching fast.In embodiments of the present invention, high frequency clock when read-write operation is 100MHZ, when read-write operation finishes, when the low-limit frequency low-frequency clock when allowing SRAM to carry out read-write operation once more is 1MHZ, because in cmos circuit, power consumption is directly proportional with clock, and this has reduced the power consumption of SRAM largely with regard to making SRAM finish and power consumption when being in idle state 1% when being reduced to operate as normal at read-write operation.
For method embodiment, because it is substantially corresponding to method embodiment, so description is fairly simple, relevant part partly illustrates referring to circuit embodiments and gets final product.
More than to a kind of circuit and method that reduces the SRAM power consumption provided by the present invention, be described in detail, used specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1. a circuit that reduces the SRAM power consumption is characterized in that, comprising:
The read and write access unit is used for SRAM is carried out read-write operation, and the output trigger pip;
The low-power consumption mode control module is used to receive the trigger pip of read and write access unit, produces the clock switching signal;
The clock switch unit is used for the receive clock switching signal, SRAM is carried out clock switch.
2. the circuit of reduction SRAM power consumption according to claim 1 is characterized in that,
Described trigger pip is a low level, and expression SRAM has read and write access; Described trigger pip is a high level, and expression SRAM read and write access finishes.
3. the circuit of reduction SRAM power consumption according to claim 2 is characterized in that described clock switches to the switching between high frequency clock CLK1 and the low-frequency clock CLK2; When described trigger pip was low level, the clock of SRAM switched to high frequency from low frequency; When described trigger pip was high level, the clock of SRAM switched to low frequency from high frequency.
4. the circuit of reduction SRAM power consumption according to claim 3 is characterized in that,
Described high frequency clock CLK1 time incision before low-frequency clock CLK2 finishes a clock period.
5. the circuit of reduction SRAM power consumption according to claim 1 is characterized in that described low-power consumption mode control module specifically comprises:
First D flip-flop, its input end of clock connects high frequency clock CLK1, and data input pin connects described trigger pip, data output end output signal SD1;
Second D flip-flop, its input end of clock connects high frequency clock CLK1, and data input pin connects the output signal SD1 of first D flip-flop, data output end output signal SD2;
With door, be used for SD1 signal and SD2 signal and, output clock switching signal.
6. the circuit of reduction SRAM power consumption according to claim 1 is characterized in that described clock switch unit specifically comprises:
The 3rd D flip-flop, its input end of clock connects high frequency clock CLK1, and data input pin connects low-frequency clock CLK2;
The 4th D flip-flop, its input end of clock connects high frequency clock CLK1, and data input pin connects the 3rd D flip-flop output signal;
Selector switch, it selects control signal is the clock switching signal, input end is the output signal and the high frequency clock CLK1 of the 4th D flip-flop, and its clock signal is offered SRAM.
7. the circuit of reduction SRAM power consumption according to claim 6 is characterized in that, also comprises:
Clock synchronization module, it is at the data input pin that low-frequency clock CLK2 is inserted the 3rd D flip-flop D3, and high frequency clock CLK1 is inserted before the input end of clock of the 3rd D flip-flop D3, and low-frequency clock CLK2 is carried out in high frequency clock CLK1 territory synchronously.
8. a method that reduces the SRAM power consumption is characterized in that, may further comprise the steps:
When receiving the SRAM read-write operation request, the output low level trigger pip, the described low level trigger pip of foundation switches to high frequency with the clock of SRAM from low frequency; When the SRAM read-write operation finishes, the output high trigger signal, the described high trigger signal of foundation switches to low frequency with the clock of SRAM from high frequency.
9. the method for reduction SRAM power consumption according to claim 8 is characterized in that, also comprises:
Before switching clock, low-frequency clock is carried out in the high frequency clock territory synchronously.
10. the method for reduction SRAM power consumption according to claim 8 is characterized in that,
The time incision before low-frequency clock is finished a clock period of described high frequency clock.
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| CN2008102224270A CN101369452B (en) | 2008-09-16 | 2008-09-16 | Circuit and method for reducing SRAM power consumption |
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| CN2008102224270A CN101369452B (en) | 2008-09-16 | 2008-09-16 | Circuit and method for reducing SRAM power consumption |
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| CN101369452A CN101369452A (en) | 2009-02-18 |
| CN101369452B true CN101369452B (en) | 2011-04-06 |
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Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102654532B (en) * | 2011-05-31 | 2014-09-03 | 万高(杭州)科技有限公司 | Method for reducing power consumption of electric energy metering chip |
| CN103474093B (en) * | 2012-06-07 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Control following the trail of circuit and using the SRAM following the trail of circuit of sense amplifier unlatching |
| US9355692B2 (en) | 2012-09-18 | 2016-05-31 | International Business Machines Corporation | High frequency write through memory device |
| CN103809105B (en) * | 2012-11-13 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | There is the chip of low-and high-frequency clock handoff functionality |
| CN103019132B (en) * | 2012-11-21 | 2015-03-18 | 杭州士兰微电子股份有限公司 | Chip and method for realizing low-power-consumption mode |
| CN103985403B (en) * | 2013-02-07 | 2017-04-05 | 群联电子股份有限公司 | Working clock switching method, memory controller and memory storage device |
| CN104598160A (en) * | 2013-10-31 | 2015-05-06 | 北京航天长征飞行器研究所 | Method for lowering power consumption of nand flash controller |
| CN106529067B (en) * | 2016-11-23 | 2019-03-15 | 中国电子科技集团公司第五十四研究所 | A kind of low power consuming clock dynamic management circuit and management method |
| CN108089689A (en) * | 2017-11-17 | 2018-05-29 | 珠海慧联科技有限公司 | A kind of small-sized SoC super low-power consumptions control circuit and method |
| CN119088195B (en) * | 2024-11-05 | 2025-03-07 | 北京轩宇信息技术有限公司 | SRAM array low-power consumption control method |
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