CN101368990A - Method for eliminating probe needle track bias - Google Patents
Method for eliminating probe needle track bias Download PDFInfo
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- CN101368990A CN101368990A CN 200710044851 CN200710044851A CN101368990A CN 101368990 A CN101368990 A CN 101368990A CN 200710044851 CN200710044851 CN 200710044851 CN 200710044851 A CN200710044851 A CN 200710044851A CN 101368990 A CN101368990 A CN 101368990A
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Abstract
The invention discloses a method for eliminating probe track offset, which is characterized in that the method comprises following steps: A) a wafer can be arranged on a probe device; B) the wafer is positioned; C) whether the wafer position has errors or not is judged, if yes, and then step D can be executed; if no error exists, step E is executed; D) the probe trace is detected, and the probe position can be adjusted; E) all parameters of the wafer can be tested through a test machine; F) the wafer is unloaded. The method belongs to the integration circuit manufacturing, can greatly reduce error of the measuring result of electrical parameter, and can prevent the wafer from being discarded.
Description
Technical field
The present invention relates to ic manufacturing technology, refer in particular to the method for the probe needle track bias (Probe Mark Shift) in a kind of elimination wafer acceptance testing (WAT, Wafer Acceptance Test).
Background technology
Wafer acceptance testing (WAT, Wafer Acceptance Test) promptly be by measuring the electrical parameter of some testing element structure, to understand and to react the physical characteristics and the manufacture process of whole wafer, thereby making in earlier stage, the research staff can improve circuit elements design and processing procedure by above-mentioned electrical parameter measurement result.Described electrical parameter comprises voltage breakdown, contact resistance, square resistance of cut-in voltage, saturation current, leakage current, gate pole oxidation layer etc.
The result of semiconductor parametric test need by accurate and fast parameter testing equipment obtain the test machine (Tester) of the probe machine (Prober) of TEL (TEL), probe (Probe Card), Agilent (Agilent) etc. for example.Probe places the probe machine, and the probe board is connected (Cable End) with test machine by cable.When carrying out the measurement of each parameter, the probe on the probe needs to move in real time at the detecting location of wafer, and the needle tracking of probe can produce skew inevitably.
The WAT testing procedure of prior art as shown in Figure 1.A collection of (Lot) product comprises 25 wafer, should test every wafer in turn, and concrete steps are as follows:
101) wafer is placed on the probe machine (Prober);
102) location (Alignment) wafer;
103) utilize test machine (Tester) that wafer is carried out the parameters test;
104) unloading wafer.
Because the location wafer has error sometimes, the needle tracking of probe on wafer can produce skew inevitably.And in the prior art, the skew of needle tracking is not monitored and handled, thereby cause the measurement result of electrical parameter to have than mistake.
In addition, the mobile meeting of the deviation of probe causes the scuffing of wafer, and then may cause scrapping of wafer.
In addition, owing to ceaselessly every wafer is tested in turn, may cause a collection of (Lot) wafer, also promptly 25 wafer are all scrapped.
Summary of the invention
In view of this, the object of the present invention is to provide the method for the probe needle track bias among a kind of WAT of elimination, thereby greatly reduce the error of the measurement result of electrical parameter, and avoid scrapping of wafer.
The present invention is achieved by the following technical solutions, comprises the steps:
A) wafer is placed on the probe machine;
B) location wafer;
C) whether the location of judging wafer has error, if any error, and execution in step D); As error free,
Execution in step E);
D) needle tracking inspection, and probe location regulated;
E) utilize test machine that wafer is carried out the parameters test;
F) unloading wafer.
Further, described needle tracking inspection is by the LCDs on the probe machine, observes the position of probe on wafer, and probe is regulated, and the detecting location that shows on LCDs is correct.
Further, described wafer location is to monitor by the microscope of probe machine.
Further, described step C) back is further comprising the steps of:
A1) judge whether to position adjusting; Regulate as need, then execution in step C1); As not regulating, execution in step B1 then);
B1) judge whether to end to carry out first test cell of test, as termination, then execution in step C1); As not ending, execution in step E then);
C1) end test;
D1) judge whether to carry out the needle tracking inspection, check as the need needle tracking, then execution in step D); As not needing the needle tracking inspection, execution in step C1 then).
Further, described step F) after, judge whether the test of a collection of wafer is finished, finish if tested, then the wafer acceptance testing of this batch wafer finishes; If test is not finished, then execution in step A).
Beneficial effect of the present invention is: the present invention mistakes detecting being positioned with of wafer, introduces needle tracking inspection (Contact Check) to eliminate needle track bias, has greatly improved the measuring accuracy of electrical parameter.
In addition, after needle track bias was eliminated, probe moved between correct detecting location, can avoid the scuffing of wafer effectively, thereby avoid scrapping of wafer.
In addition, the present invention judges whether to carry out the test of next wafer after the test of finishing a wafer, thereby has increased the controllability of WAT test.
Description of drawings
Fig. 1 is existing WAT process flow diagram;
Fig. 2 is a WAT process flow diagram of the present invention;
Fig. 3 is the condition judgment process flow diagram that needle tracking is checked that carries out of the present invention.
Embodiment
Below in conjunction with specific embodiments and the drawings, the invention will be further described.
Fig. 2 is a WAT process flow diagram of the present invention.Testing procedure to every wafer is as follows:
201) wafer is placed on the probe machine (Prober);
202) location (Alignment) wafer;
203) whether the location of judging wafer has error, if any error, and execution in step 204); As error free, execution in step 205);
204) needle tracking inspection, and probe location regulated;
205) utilize test machine (Tester) that wafer is carried out the parameters test;
206) unloading wafer.
Method of the present invention is monitored the wafer location by the microscope (Camera) of probe machine, correct as the wafer location, then execution in step 205), also promptly the step to the testing procedure of every wafer and prior art is consistent, be positioned with error as wafer, then execution in step 204) carry out the needle tracking inspection.The needle tracking inspection that is to say by the LCDs on the probe machine (LCD), observes the position of probe on wafer.Probe is regulated, and it is correct to go up the detecting location that shows until LCD.
In step 203) after can carry out multiple judgement to the condition of carrying out the needle tracking inspection, as shown in Figure 3, comprise the steps:
301) judge whether to position adjusting; Regulate as need, then execution in step 303); As not regulating, then execution in step 302);
302) judge whether to end to carry out test first test cell (Chip), as termination, then execution in step 303); As not ending, then execution in step 205);
303) end test;
304) judge whether to carry out the needle tracking inspection, check that as the need needle tracking then execution in step 204); As not needing the needle tracking inspection, then execution in step 303).
In step 204) preceding termination test, the condition that the hand-manipulating of needle mark of going forward side by side is checked of being provided with.Be positioned with error as wafer, the present invention also is an execution in step 205 continuing test) the preceding two-stage condition judgment step 301 that is provided with), step 302), be positioned with under the situation of error at wafer preventing, execution in step 204), and direct execution in step 205), thereby the scuffing of wafer caused.
When step 301), step 302) arbitrary condition judgment result when being "Yes", execution in step 303), step 304).As step 304) condition judgment result when being "No", circulation execution in step 303), step 304), until step 304) condition judgment result be "Yes", also promptly must execution in step 204), the position of probe is regulated.Above condition judgment strengthens the controllability of in the WAT test needle tracking being checked.
In addition, in step 206) behind the unloading wafer, the present invention can judge whether to carry out the test of next wafer after the test of finishing a wafer, judges promptly also whether the test of a collection of (Lot) wafer is finished.Finish if tested, then the WAT end of test (EOT) of this batch wafer; If test is not finished, then execution in step 201), begin the test of next wafer of this batch product.Above condition judgment further strengthens the controllability of WAT test.
More than method of the present invention is described in detail, but can not limit scope of the present invention with this.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. a method of eliminating probe needle track bias is characterized in that, comprises the steps:
A) wafer is placed on the probe machine;
B) location wafer;
C) whether the location of judging wafer has error, if any error, and execution in step D); As error free, execution in step E);
D) needle tracking inspection, and probe location regulated;
E) utilize test machine that wafer is carried out the parameters test;
F) unloading wafer.
2. the method for elimination probe needle track bias as claimed in claim 1, it is characterized in that described needle tracking inspection is by the LCDs on the probe machine, observe the position of probe on wafer, probe is regulated, and the detecting location that shows on LCDs is correct.
3. the method for elimination probe needle track bias as claimed in claim 1 is characterized in that, described wafer location is to monitor by the microscope of probe machine.
4. the method for elimination probe needle track bias as claimed in claim 1 is characterized in that, described step C) back further comprising the steps of:
A1) judge whether to position adjusting; Regulate as need, then execution in step C1); As not regulating, execution in step B1 then);
B1) judge whether to end to carry out first test cell of test, as termination, then execution in step C1); As not ending, execution in step E then);
C1) end test;
D1) judge whether to carry out the needle tracking inspection, check as the need needle tracking, then execution in step D); As not needing the needle tracking inspection, execution in step C1 then).
5. the method for elimination probe needle track bias as claimed in claim 1 is characterized in that, described step F) after, judge whether the test of a collection of wafer is finished, finish if tested, then the wafer acceptance testing of this batch wafer finishes; If test is not finished, then execution in step A).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710044851 CN101368990A (en) | 2007-08-14 | 2007-08-14 | Method for eliminating probe needle track bias |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710044851 CN101368990A (en) | 2007-08-14 | 2007-08-14 | Method for eliminating probe needle track bias |
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| CN101368990A true CN101368990A (en) | 2009-02-18 |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102162831A (en) * | 2011-03-15 | 2011-08-24 | 上海宏力半导体制造有限公司 | Detection method of wafer parameters |
| CN102254220A (en) * | 2011-04-13 | 2011-11-23 | 致茂电子(苏州)有限公司 | Probe deviation detection system and method thereof of LED die point measurement machine |
| CN102749570A (en) * | 2012-07-26 | 2012-10-24 | 上海宏力半导体制造有限公司 | Wafer test device and wafer test method for probe station |
| CN104422864A (en) * | 2013-08-21 | 2015-03-18 | 上海华虹宏力半导体制造有限公司 | Method for confirming position alignment in wafer test |
| CN105467174A (en) * | 2015-11-23 | 2016-04-06 | 上海华岭集成电路技术股份有限公司 | Method of acquiring cantilever-type probe system maintenance period |
| CN107368100A (en) * | 2017-06-26 | 2017-11-21 | 上海华岭集成电路技术股份有限公司 | The method for adjusting cantilever probe card needle tracking |
| CN108172154A (en) * | 2018-01-03 | 2018-06-15 | 惠科股份有限公司 | Test method and test equipment |
| CN112534277A (en) * | 2018-08-07 | 2021-03-19 | 派克泰克封装技术有限公司 | Method and apparatus for maintenance inspection of contact arrangement |
| CN112927948A (en) * | 2021-01-22 | 2021-06-08 | 上海华虹宏力半导体制造有限公司 | Method for correcting probe position of resistance instrument and method for measuring square resistance |
-
2007
- 2007-08-14 CN CN 200710044851 patent/CN101368990A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102162831A (en) * | 2011-03-15 | 2011-08-24 | 上海宏力半导体制造有限公司 | Detection method of wafer parameters |
| CN102254220A (en) * | 2011-04-13 | 2011-11-23 | 致茂电子(苏州)有限公司 | Probe deviation detection system and method thereof of LED die point measurement machine |
| CN102749570A (en) * | 2012-07-26 | 2012-10-24 | 上海宏力半导体制造有限公司 | Wafer test device and wafer test method for probe station |
| CN104422864A (en) * | 2013-08-21 | 2015-03-18 | 上海华虹宏力半导体制造有限公司 | Method for confirming position alignment in wafer test |
| CN104422864B (en) * | 2013-08-21 | 2017-10-24 | 上海华虹宏力半导体制造有限公司 | The confirmation method of position alignment is realized in wafer sort |
| CN105467174B (en) * | 2015-11-23 | 2018-11-09 | 上海华岭集成电路技术股份有限公司 | A method of obtaining the cantalever type probe system maintenance period |
| CN105467174A (en) * | 2015-11-23 | 2016-04-06 | 上海华岭集成电路技术股份有限公司 | Method of acquiring cantilever-type probe system maintenance period |
| CN107368100A (en) * | 2017-06-26 | 2017-11-21 | 上海华岭集成电路技术股份有限公司 | The method for adjusting cantilever probe card needle tracking |
| CN108172154A (en) * | 2018-01-03 | 2018-06-15 | 惠科股份有限公司 | Test method and test equipment |
| CN112534277A (en) * | 2018-08-07 | 2021-03-19 | 派克泰克封装技术有限公司 | Method and apparatus for maintenance inspection of contact arrangement |
| CN112534277B (en) * | 2018-08-07 | 2024-05-14 | 派克泰克封装技术有限公司 | Method and apparatus for repairing and checking contact device |
| US12048972B2 (en) | 2018-08-07 | 2024-07-30 | PAC Tech—Packaging Technologies GmbH | Method and device including laser heating of gripper for repairing a test contact arrangement |
| CN112927948A (en) * | 2021-01-22 | 2021-06-08 | 上海华虹宏力半导体制造有限公司 | Method for correcting probe position of resistance instrument and method for measuring square resistance |
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