CN101351083B - Circuit board and its process - Google Patents

Abstract

The present invention discloses a circuit board process, which includes the following steps: first, providing a substrate, the substrate having a core layer and two first composite metal layers, the core layer being located between the first composite metal layers, wherein each first composite metal layer has a first metal layer and a first etching barrier layer, and the first metal layer is located between the core layer and the first etching barrier layer. Then, a conductive hole is formed on the substrate. Then, a patterned conductive layer is formed on the inner wall of the conductive hole and the first etching barrier layer. Then, the portion of the first etching barrier layer exposed by the patterned conductive layer is removed to form a patterned first etching barrier layer. Afterwards, the portion of the first metal layer exposed by the patterned conductive layer is removed to form a patterned first metal layer. In addition, the present invention also discloses a circuit board.

Description

Circuit board and its process

technical field

The present invention relates to a circuit board (Circuit Board) and its technology, and in particular to a circuit board with thin circuits and its technology.

Background technique

In recent years, with the rapid development of the production technology of the electronics industry, circuit boards can be equipped with various electronic components with exquisite volumes, so as to be widely used in various electronic products with different functions. The manufacturing process of the known circuit board will be described below. Please refer to FIG. 1A to FIG. 1F . FIG. 1A to FIG. 1F are cross-sectional views illustrating a process flow of a known circuit board process. A known circuit board process includes the following steps: First, as shown in FIG. 1A , a substrate 110 is provided. Wherein, the substrate 110 has a core layer 112 and two copper foil layers 114 , and the core layer 112 is disposed between the two copper foil layers 114 . Then, as shown in FIG. 1B , a through hole 120 is formed on the substrate 110 by mechanical drilling.

Next, as shown in FIG. 1C , an electroplating process is used to form a conductive layer 130 on the copper foil layer 114 and the inner wall of the through hole 120 . The conductive layer 130 is electrically connected to the circuits on both sides of the core layer 112 . Next, as shown in FIG. 1D , a patterned photoresist layer 140 is formed on the conductive layer 130 , wherein the patterned photoresist layer 140 exposes part of the conductive layer 130 . Next, as shown in FIG. 1E, the patterned photoresist layer 140 is used as a mask, and the part of the conductive layer 130 and the copper foil layer 114 exposed by the patterned photoresist layer 140 are patterned by etching technology to form The patterned conductive layer 130 ′ and the patterned copper foil layer 114 ′ constitute the patterned circuit layer 150 . Afterwards, as shown in FIG. 1F , the patterned photoresist layer 140 is removed to complete the fabrication of the known circuit board 100 .

It is worth mentioning that, as the design of integrated circuits becomes more complex and finer, the circuit design in circuit boards is also becoming more refined. However, in the process of forming the patterned wiring layer 150, the known technique is to apply an etching process to remove the exposed portion of the conductive layer 130 and the copper foil layer 114 from the patterned photoresist layer 140 to produce the patterned wiring layer. 150. Wherein, since the copper foil layer 114 and the material such as the conductive layer 130 of copper have large variability in their thickness during the formation process, and the known technology cannot stably control the etching variability (the etching solution has a large impact on the copper foil layer 114 and the conductive layer 130). The etching degree of layer 130), so the line width W1 of the patterned line layer 150 produced by the known technology cannot meet the specifications of the thin line (the etchant will over-etch the copper foil layer 114 and the conductive layer 130 and cause the line width W1 to be insignificant. conforms to thin line specifications). In other words, the known circuit board technology cannot produce circuit boards with fine lines.

Contents of the invention

The object of the present invention is to provide a circuit board process to produce a circuit board with thin lines.

Another object of the present invention is to provide a circuit board whose line width complies with the specifications of thin lines.

In order to achieve the above or other purposes, the present invention proposes a circuit board process, which includes the following steps: first, a substrate is provided, the substrate has a core layer and two first composite metal layers, and the core layer is arranged on these first composite metal layers. Between layers, each of the first composite metal layers has a first metal layer and a first etch barrier layer, and the first metal layer is located between the core layer and the first etch barrier layer. Then, conductive holes are formed on the substrate. Next, a patterned conductive layer is formed on the inner wall of the conductive hole and the first etching barrier layer, wherein the patterned conductive layer exposes a part of the first etching barrier layer. Next, the exposed portion of the first etching barrier layer of the patterned conductive layer is removed to form a patterned first etching barrier layer, and the patterned conductive layer exposes a portion of the first metal layer. Afterwards, a patterning process is performed on a part of the first metal layer exposed by the patterned conductive layer by using the patterned conductive layer as an etching barrier, so as to form a patterned first metal layer.

In an embodiment of the invention, the conductive hole is formed by mechanical drilling.

In an embodiment of the present invention, the conductive hole is formed by laser burning.

In an embodiment of the present invention, the method of forming the patterned conductive layer includes the following steps: firstly, forming a third metal layer on the inner wall of the conductive hole and the first etching barrier layer. Then, a patterned second composite metal layer is formed on the third metal layer, wherein the patterned second composite metal layer exposes part of the third metal layer, and the patterned second composite metal layer has the patterned second metal layer and the patterned The second etching barrier layer, and the patterned second metal layer is located between the third metal layer and the patterned second etching barrier layer. Next, a patterning process is performed on a part of the third metal layer exposed by the patterned second composite metal layer by using the patterned second etch barrier layer as an etch barrier to form a patterned third metal layer, wherein the patterned third metal layer layer exposing a portion of the first etch barrier layer. Afterwards, the patterned second etching barrier layer is removed, and the patterned conductive layer includes a patterned second metal layer and a patterned third metal layer.

In an embodiment of the present invention, the method of forming the third metal layer includes an electroplating process.

In an embodiment of the present invention, the method of forming the patterned second composite metal layer includes the following steps: first, forming a patterned photoresist layer on the third metal layer, wherein the patterned photoresist layer exposes a part of the second compound metal layer. Three metal layers. Then, a patterned second metal layer is formed on the part of the third metal layer exposed by the patterned photoresist layer. Next, a patterned second etching barrier layer is formed on the patterned second metal layer. Afterwards, the patterned photoresist layer is removed.

In an embodiment of the invention, the method of forming the patterned second metal layer includes an electroplating process.

In an embodiment of the invention, the method of forming the patterned second etch barrier layer includes an electroplating process.

The invention provides a circuit board, which includes a substrate and a patterned conductive layer. Wherein, the substrate has a core layer, two patterned first composite metal layers and conductive holes, the core layer is disposed between the two patterned first composite metal layers, and each patterned first composite metal layer has a patterned first composite metal layer. The metal layer and a patterned first etching barrier layer, the patterned first metal layer is located between the core layer and the patterned first etching barrier layer. In addition, the patterned conductive layer is disposed on the inner wall of the conductive hole and the patterned first etching barrier layer. The patterned first composite metal layer and the patterned conductive layer constitute the conductive hole and the circuit layer outside the conductive hole.

In an embodiment of the invention, the patterned conductive layer includes patterned second metal layer and patterned third metal layer.

In an embodiment of the invention, the patterned first metal layer is a copper foil layer.

In an embodiment of the invention, the patterned first etch barrier layer is a nickel layer.

In an embodiment of the present invention, the patterned third metal layer and the patterned second metal layer are electroplated copper layers.

In an embodiment of the invention, the material of the patterned first etch barrier layer is different from that of the patterned conductive layer.

In an embodiment of the invention, the material of the patterned first etch barrier layer is different from that of the patterned first metal layer.

In the above-mentioned circuit board process, the present invention uses the etching barrier layer to control the etching degree of the etchant to the patterned first metal layer and the patterned conductive layer. Therefore, compared with the known technology, the circuit board process of the present invention can stably control the etching degree of the etchant to the patterned first metal layer and the patterned conductive layer, thereby making the circuits of the circuit board (including the patterned first metal layer) and the patterned conductive layer) width can meet the specifications of the thin circuit, that is, the circuit board process of the present invention can produce a thin circuit board with better quality.

In order to make the above-mentioned and other objects, features and advantages of the present invention more comprehensible, the preferred embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows.

Description of drawings

FIG. 1A to FIG. 1F are schematic cross-sectional views of a known circuit board process.

FIG. 2 is a flow chart showing the fabrication of a circuit board according to a preferred embodiment of the present invention.

3A to 3J are schematic cross-sectional views of the circuit board process of FIG. 2 .

Explanation of reference signs

100: Circuit board 110: Substrate

112: Core layer 114: Copper foil layer

114': Patterned copper foil layer 120: Through hole

130: Conductive layer 130’: Patterned conductive layer

140: Patterned photoresist layer 150: Patterned circuit layer

300: circuit board 310: substrate

312: Core layer 312a: Surface above the core layer

312b: The surface below the core layer 314: The first composite metal layer

314': patterning the first composite metal layer 314a: the first metal layer

314a': patterning the first metal layer 314b: the first etch barrier layer

314b': Patterning the first etch barrier layer 320: Conductive holes

330: patterned conductive layer 332: third metal layer

332': Patterning the third metal layer 340: Patterning the photoresist layer

350: Patterning the second composite metal layer 352: Patterning the second metal layer

354: Patterning the second etch barrier layer S1～S5: each step

W1, W2: line width

Detailed ways

FIG. 2 is a flow chart showing the fabrication of a circuit board according to a preferred embodiment of the present invention. Please refer to Fig. 2, the circuit board process of the present embodiment includes the following steps: first, execute step S1, provide the substrate, the substrate has a core layer and two first composite metal layers, wherein each first composite metal layer has a first metal layer and the first etch barrier layer. Next, step S2 is performed to form conductive holes on the substrate. Then, step S3 is performed to form a patterned conductive layer on the inner wall of the conductive hole and the first etch barrier layer, wherein the patterned conduction layer exposes part of the first etch barrier layer.

After step S3 is performed, step S4 is immediately performed to remove a part of the first etch barrier layer exposed by the patterned conductive layer to form a patterned first etch barrier layer, and to expose a part of the first etch barrier layer in the patterned conductive layer. metal layer. Afterwards, step S5 is performed, using the patterned conductive layer as an etching barrier to perform a patterning process on a part of the first metal layer exposed by the patterned conductive layer, so as to form a patterned first metal layer. Hereinafter, this embodiment will illustrate the above circuit board process with a detailed process sectional view.

3A to 3J are schematic cross-sectional views of the circuit board process of FIG. 2 . The manufacturing method of this circuit board is as follows: first, as shown in Figure 3A, provide substrate 310, substrate 310 has a core layer 312 and two first composite metal layers 314, core layer 312 is arranged on these first composite metal layers 314 , that is, the first composite metal layers 314 are disposed on the upper surface 312 a and the lower surface 312 b of the core layer 312 , for example. In addition, in this embodiment, each first composite metal layer 314 has a first metal layer 314a and a first etch barrier layer 314b, and the first metal layer 314a is located between the core layer 312 and the first etch barrier layer 314b between. Wherein, the first metal layer 314a is, for example, a copper foil layer, and the first etch barrier layer 314b is, for example, a nickel layer. Next, as shown in FIG. 3B , a conductive hole 320 is formed on the substrate 310 . For example, the conductive hole 320 can be a through hole or a blind via. The conductive hole 320 shown in FIG. , laser burning or other appropriate methods.

After forming the conductive hole 320 on the substrate 310, as shown in FIG. 3C to FIG. part of the first etch barrier layer 314b (please refer to FIG. 3H). In this embodiment, forming the patterned conductive layer 330 includes, for example, the following steps: First, as shown in FIG. 3C , a third metal layer 332 is formed on the inner wall of the conductive hole 320 and the first etch barrier layer 314b. Wherein, the third metal layer 332 is, for example, an electroplated copper layer produced by an electroplating process, an electroless copper layer produced by an electroless copper process, or a metal layer produced by other appropriate processes. In addition, before forming the third metal layer 332 , in this embodiment, an electroless plating process may be performed to form an electroplating seed layer on the inner wall of the conductive hole 320 and the first etch barrier layer 314 b to facilitate the subsequent electroplating process.

After the third metal layer 332 is formed on the inner wall of the conductive hole 320 and the first etch barrier layer 314b, then as shown in FIG. Resist layer 340, wherein the patterned photoresist layer 340 is formed on the third metal layer 332, for example, through exposure and development techniques (in this embodiment, for example, the photoresist layer is first formed on the third metal layer 332, and then The photoresist layer is patterned using NaOH solution to form a patterned photoresist layer 340). Then, as shown in FIG. 3E, a patterned second metal layer 352 and a patterned second etch barrier layer 354 are sequentially formed on the part of the third metal layer 332 exposed by the patterned photoresist layer 340 (i.e. The second metal layer 352 is located between the third metal layer 332 and the patterned second etch barrier layer 354), wherein the patterned second metal layer 352 and the patterned second etch barrier layer 354 constitute a patterned second composite metal layer 350, and the ways of forming the patterned second metal layer 352 and the patterned second etch barrier layer 354 are, for example, electroplating copper process and electroplating nickel process respectively, that is, the patterned second metal layer 352 is an electroplated copper layer, and the pattern The second etch barrier layer 354 is an electroplated nickel layer. After forming the patterned second composite metal layer 350 on the third metal layer 332, then as shown in FIG. glue layer 340 ), and patterning the second composite metal layer 350 exposes part of the third metal layer 332 .

After forming the patterned second composite metal layer 350 on the third metal layer 332, as shown in FIG. Part of the third metal layer 332 is subjected to a patterning process to form a patterned third metal layer 332' exposing a part of the first etch barrier layer 314b, and the patterning process is, for example, an etching process. Wherein, since the material of the first etching barrier layer 314b is, for example, nickel, the material of the patterned third metal layer 332' is, for example, copper, and the etchant has different etching capabilities for copper and nickel (in the step of FIG. 3G The applied etching solution has a relatively large etching rate for copper metal), so this embodiment can effectively pattern the third metal layer 332 in the above etching process to form the patterned third metal layer 332 ′. For example, the etchant used to remove nickel is an alkaline solution, while the etchant used to etch copper is an acidic solution such as CuCl ₂ . Next, as shown in FIG. 3H , the patterned second etch barrier layer 354 is removed, and the patterned conductive layer 330 includes the patterned second metal layer 352 and the patterned third metal layer 332 ′.

As mentioned above, after the patterned conductive layer 330 is formed on the inner wall of the conductive hole 320 and the first etch barrier layer 314b, then as shown in FIG. layer 314b to form a patterned first etch barrier layer 314b', and make the patterned conductive layer 330 expose part of the first metal layer 314a. Of course, when removing the patterned second etch barrier layer 354, the exposed part of the first etch barrier layer 314b of the patterned conductive layer 330 may also be removed simultaneously to form the patterned first etch barrier layer 314b', This embodiment does not make any limitation here.

After forming the patterned first etching barrier layer 314b', as shown in FIG. 3J, the patterned conductive layer 330 is used as an etching barrier to perform a patterning process on the part of the first metal layer 314a exposed by the patterned conductive layer 330. (The patterning process is, for example, an etching process) to form the patterned first metal layer 314 a ′. In this way, the manufacturing process of the circuit board 300 of this embodiment is completed. Wherein, the circuit of the circuit board 300 is mainly composed of the patterned first composite metal layer 314' (the patterned first composite metal layer 314' is composed of the patterned first metal layer 314a' and the patterned first etch barrier layer 314b' ) and the patterned conductive layer 330 (the patterned conductive layer 330 is composed of the patterned second metal layer 352 and the patterned third metal layer 332 ′).

Similarly, since the material of the patterned first etch barrier layer 314b' is different from that of the first metal layer (the material of the patterned first etch barrier layer 314b' is nickel, while the material of the first metal layer 314a is copper), And the etchant has different etching abilities to copper and nickel (the etchant applied in the step of Fig. 3J has a larger etching rate to copper metal), so the present embodiment can effectively use the first one in the above-mentioned etching process. The metal layer 314a is patterned to form a patterned first metal layer 314a'.

It is worth mentioning that the patterned conductive layer 330 of this embodiment is separated from the first metal layer 314a by the first etch barrier layer 314b. Therefore, when the patterned conductive layer 330 is fabricated in this embodiment, the etching The etchant does not act on the first metal layer 314a, and after removing part of the first etch barrier layer 314b, the etchant can remove the first metal layer 314a exposed by the patterned conductive layer 330 to form a pattern Thin the first metal layer 314a'. In this way, this embodiment can effectively control the etching degree of the etchant on the patterned first metal layer 314a' and the patterned conductive layer 330, thereby reducing the influence of etching variability on the line width W2, so that this embodiment The manufactured line width W2 can meet the specifications of thin lines.

In summary, in the wiring board process of the present invention, the present invention utilizes the etch barrier layer to control the etchant to the etching degree of the first metal layer and the conductive layer (the etchant used in different processes has a significant impact on the etch barrier layer) different etch selectivity from the first metal layer or conductive layer). Therefore, compared with the known technology, the circuit board process of the present invention can effectively control the line width on the circuit board, so that the line width on the circuit board can meet the specifications of thin lines. That is, the circuit board process of the present invention can produce thin circuit boards with better quality.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope is to be determined as defined by the appended claims.

Claims (7)

1. circuit board technique comprises:

Substrate is provided, this substrate has a core layer and 2 first complex metal layers, this core layer is equipped between this first complex metal layer, wherein respectively this first complex metal layer has the first metal layer and first etch barrier, and this first metal layer is between this core layer and this first etch barrier;

On this substrate, form conductive hole;

Form patterned conductive layer on the inwall of this conductive hole and this first etch barrier, wherein this patterned conductive layer exposes this first etch barrier of part;

Remove this first etch barrier of this patterned conductive layer exposed portions,, and make this patterned conductive layer expose this first metal layer of part with formation patterning first etch barrier; And

With this patterned conductive layer is that etch barrier is carried out Patternized technique to this this first metal layer of patterned conductive layer exposed portions, with formation patterning the first metal layer,

The mode that wherein forms this patterned conductive layer comprises:

On the inwall of this conductive hole and this first etch barrier, form the 3rd metal level;

On the 3rd metal level, form patterning second complex metal layer, wherein this patterning second complex metal layer exposes part the 3rd metal level, this patterning second complex metal layer has patterning second metal level and patterning second etch barrier, and this patterning second metal level is between the 3rd metal level and this patterning second etch barrier;

With this patterning second etch barrier is that etch barrier is carried out Patternized technique to this patterning second complex metal layer exposed portions the 3rd metal level, to form patterning the 3rd metal level, wherein this patterning the 3rd metal level exposes this first etch barrier of part; And

Remove this patterning second etch barrier, and this patterned conductive layer comprises this patterning second metal level and this patterning the 3rd metal level.

2. circuit board technique as claimed in claim 1, the mode that wherein forms this conductive hole is machine drilling or laser hole burning.

3. circuit board technique as claimed in claim 1, the mode that wherein forms the 3rd metal level comprises electroplating technology.

4. circuit board technique as claimed in claim 1, the mode that wherein forms this patterning second complex metal layer comprises:

Form the patterning photoresist layer on the 3rd metal level, wherein this patterning photoresist layer exposes part the 3rd metal level;

On this patterning photoresist layer exposed portions the 3rd metal level, form this patterning second metal level;

On this patterning second metal level, form patterning second etch barrier; And

Remove this patterning photoresist layer.

5. circuit board technique as claimed in claim 4, the mode that wherein forms this patterning second metal level comprises electroplating technology.

6. circuit board technique as claimed in claim 4, the mode that wherein forms this patterning second etch barrier comprises electroplating technology.

7. wiring board comprises:

Substrate, have a core layer, two patternings, first complex metal layer and conductive hole, this core layer is equipped between this patterning first complex metal layer, wherein respectively this patterning first complex metal layer has patterning the first metal layer and a patterning first etch barrier, and this patterning the first metal layer is between this core layer and this patterning first etch barrier; And

Patterned conductive layer, be equipped on the inwall and this patterning first etch barrier of this conductive hole, wherein this patterned conductive layer comprises patterning second metal level and patterning the 3rd metal level, this patterning the 3rd metal level and this patterning second metal level are copper electroplating layer, and this patterning first complex metal layer and this patterned conductive layer constitute this conductive hole and the outer line layer of this conductive hole.

Images