TWI573506B - Method for manufacturing printed circuit board - Google Patents

Description

Circuit board manufacturing method

The invention relates to a method of manufacturing a circuit board.

With the development of miniaturization and thinning of electronic products, circuit boards applied to electronic products are also moving toward smaller and thinner, and thus, circuit boards are required to have a larger wiring density, that is, have finer wiring.

Therefore, it is necessary to provide a method of fabricating a circuit board having fine wiring.

A method for manufacturing a circuit board, comprising the steps of: providing a circuit substrate, the circuit substrate comprising a dielectric layer and a conductive circuit layer formed on one side of the dielectric layer; forming a plurality of blind holes on the circuit substrate, and Forming a fourth surface of the conductive circuit layer from the blind via; forming a patterned first photoresist layer on a side of the circuit substrate away from the conductive circuit layer; away from the circuit substrate Forming a patterned second photoresist layer on the conductive circuit layer side, the patterned second photoresist layer being formed on the gap of the patterned first photoresist layer and the patterned first photoresist Laminar spacing; forming a conductive pillar in the blind via, and forming a conductive layer in the patterned gap between the first and second photoresist layers, the conductive pillar electrically connecting the conductive trace layer and the conductive a layer; and removing the first and second photoresist layers to form a circuit board.

With respect to the prior art, in the method of fabricating the circuit board of the embodiment of the present technical solution, the photoresist layer is formed twice, and the second photoresist layer is formed in the gap of the first photoresist layer, and adjacent to the photoresist The gap between the layers forms a conductive line, and the gap of the photoresist layer obtained by forming the photoresist layer can be made smaller. Therefore, the method for fabricating the circuit board of the embodiment of the present invention can produce a thinner conductive line.

10‧‧‧ circuit board

11‧‧‧Dielectric layer

12‧‧‧ Conductive circuit layer

111‧‧‧ first surface

112‧‧‧ second surface

121‧‧‧ third surface

122‧‧‧ fourth surface

13‧‧‧Blind hole

14‧‧‧Electroplating seed layer

15‧‧‧First photoresist layer

151‧‧‧First surrounding area

152‧‧‧First strip area

16‧‧‧Second photoresist layer

161‧‧‧Second surrounding area

162‧‧‧Second strip area

17‧‧‧conductive column

18‧‧‧ Conductive layer

19‧‧‧Second conductive circuit layer

191‧‧‧Electrical circuit

21‧‧‧ solder mask

20‧‧‧ boards

1 is a cross-sectional view of a circuit substrate according to an embodiment of the present invention.

2 is a cross-sectional view of a circuit substrate provided by another embodiment of the present invention.

3 is a cross-sectional view showing a blind hole formed in the circuit board of FIG. 1.

4 is a cross-sectional view showing a plating seed layer formed on the circuit substrate of FIG. 3.

Figure 5 is a cross-sectional view showing the first photoresist layer formed on the surface of the electroplated seed layer of Figure 4.

Fig. 6 is a cross-sectional view showing the first photoresist layer in Fig. 5 after patterning.

FIG. 7 is a cross-sectional view showing the second photoresist layer formed in the gap of the first photoresist layer in FIG. 5. FIG.

Figure 8 is a cross-sectional view showing the second photoresist layer of Figure 7 in a pattern.

Figure 9 is a cross-sectional view showing the formation of a conductive post in the blind via of Figure 8 and the formation of a conductive layer in the gap of the photoresist layer.

Figure 10 is a cross-sectional view showing the first and second photoresist layers of Figure 9 removed.

Figure 11 is a cross-sectional view showing the electroplated seed layer of Figure 10 not covered by a conductive layer.

Fig. 12 is a cross-sectional view showing the surface of the conductive layer in Fig. 11 after forming a solder resist layer.

Embodiments of the present invention provide a method for fabricating a circuit board, including the following steps:

In the first step, referring to FIG. 1 , a circuit substrate 10 is provided. The circuit substrate 10 includes a dielectric layer 11 and a conductive circuit layer 12 formed on one side of the dielectric layer 11 .

In this embodiment, the dielectric layer 11 includes an opposite first surface 111 and a second surface 112. The conductive circuit layer 12 is embedded in the first surface 111 of the dielectric layer 11, and the conductive circuit layer 12 includes a third surface 121 and a fourth surface 122 opposite to the third surface 121, the third surface 121 is flush with the first surface 111, and the fourth surface 122 is embedded in the medium surface Inside the electrical layer 11.

The circuit substrate 10 can be fabricated by a coreless process, that is, by providing a carrier plate, the conductive circuit layer 12 is formed on a carrier plate, and then the dielectric is formed on the conductive circuit layer 12. The layer 11 is such that the dielectric layer 11 covers the conductive wiring layer 12, and then the carrier plate is removed to form the circuit substrate 10.

In other embodiments, referring to FIG. 2 , the conductive circuit layer 12 may also protrude from the first surface 111 of the dielectric layer 11 .

In addition, the circuit board 10 may further include an alternating dielectric layer (not shown) and a conductive circuit layer (not shown) formed on the side of the conductive circuit layer 12 away from the second surface 112.

In the second step, referring to FIG. 3, a plurality of blind holes 13 are formed on the circuit substrate 10, and a portion of the fourth surface 122 of the conductive circuit layer 12 is exposed from the blind holes 13.

In the embodiment, the blind vias 13 are formed by a laser etching process, and the blind vias 13 have a substantially trapezoidal cross section along a direction perpendicular to the circuit substrate 10.

In the third step, referring to FIG. 4, a plating seed layer 14 is formed on the second surface 112 of the dielectric layer 11 of the circuit substrate 10 and the hole walls of the blind vias 13.

The plating seed layer 14 may be formed by a process such as blackening, black shadow, electroless plating, or the like. In this embodiment, the plating seed layer 14 is a thin copper layer formed by electroless plating.

In the fourth step, referring to FIG. 5-6, a patterned first photoresist layer 15 is formed on the circuit substrate 10 away from the conductive circuit layer 12 side.

Specifically, first, referring to FIG. 5, a first photoresist layer 15 is formed on the surface of the plating seed layer 14; afterwards, referring to FIG. 6, a portion of the first photoresist layer 15 is removed by an exposure and development process, thereby The first photoresist layer 15 is formed to form a patterned first photoresist layer 15. The patterned first photoresist layer 15 includes a first peripheral region 151 and a plurality of first strip regions 152 surrounded by the first peripheral region 151, the plurality of first strip regions 152 being spaced apart from each other, and The first peripheral regions 151 are also spaced apart, and the width of the gap between the adjacent two first strip regions 152 is defined as L1, and the width of each of the first strip regions 152 is defined as W1, wherein L1 and W1 are both Greater than 0. In this embodiment, the first photoresist layer 15 is a dry film.

In this embodiment, the area around the opening of the blind hole 13 and the blind hole 13 is exposed to the patterned first photoresist layer 15, and the portion of the plating seed layer 14 except the peripheral portion of the blind hole 13 and the blind hole 13 is also It is exposed to the first photoresist layer 15.

In the fifth step, referring to FIG. 7-8, a patterned second photoresist layer 16 is formed on the side of the circuit substrate 10 away from the conductive circuit layer 12, and at least a portion of the patterned second photoresist layer 16 is formed. The gap between the patterned first photoresist layer 15 and the patterned first photoresist layer 15 are spaced apart from each other.

In this embodiment, first, referring to FIG. 7, the first photoresist layer 15 is patterned. a surface and a surface of the plating seed layer 14 exposed from the patterned first photoresist layer 15 forms a second photoresist layer 16; thereafter, referring to FIG. 8, a portion of the second photoresist is removed by an exposure and development process Layer 16, thereby forming the second photoresist layer 16 to form a patterned second photoresist layer 16. The patterned second photoresist layer 16 includes a second peripheral region 161 and a plurality of second strip regions 162 surrounded by the second peripheral region 161, the second peripheral region 161 and the first peripheral region 151 Correspondingly, the plurality of second strip regions 162 are spaced apart from each other and are also spaced apart from the second peripheral region 161, and the first strip regions 152 and the second strip regions 162 are alternately arranged and also The gaps between the adjacent two second strip regions 162 are defined as L2, the width of each second strip region 162 is defined as W2, and the adjacent first strip regions 152 and the second strip are defined. The width of the gap between the regions 162 is L3, wherein L2, L3 and W2 are each greater than zero. It can be understood that L1=2L3+W2, L2=2L3+W1, that is, L3 is much smaller than L1 and L2.

The area around the opening of the blind hole 13 and the blind hole 13 is exposed to the first and second photoresist layers 15 and 16, and a portion of the plating seed layer 14 except the peripheral portion of the blind hole 13 and the blind hole 13 is also exposed. The first and second photoresist layers 15 and 16 are described.

In this embodiment, the second photoresist layer 16 is a liquid photo-etching resist formed by a printing process.

In other embodiments, the patterned second photoresist layer 16 may not form the second peripheral region 161.

In a sixth step, referring to FIG. 9, a conductive pillar 17 is formed in the blind via 13 by a plating process, and a conductive layer 18 is formed in the gap between the patterned first and second photoresist layers 15 and 16; The conductive pillars 17 electrically connect the conductive circuit layer 12 and the plating seed layer 14 and the conductive layer 18.

Specifically, the surface of the conductive pillar 17 away from the conductive circuit layer 12 is flush with the surface of the conductive layer 18, wherein the thickness of the conductive layer 18 is much larger than the thickness of the plating seed layer 14.

In the seventh step, referring to FIG. 10, the first and second photoresist layers 15, 16 are removed.

In the eighth step, referring to FIG. 11, the plating seed layer 14 not covered by the conductive layer 18 is removed, thereby forming the plating seed layer 14 and the conductive layer 18 to form the second conductive wiring layer 19.

In this embodiment, the plating seed layer 14 is etched away by rapid etching. Since the thickness of the plating seed layer 14 is much smaller than the thickness of the conductive layer 18, the conductive layer 18 is only slightly thinned and The plating seed layer 14 and the conductive layer 18 formed on the surface of the dielectric layer 11 are etched to form the second conductive wiring layer 19 without being removed by etching.

It will be understood that the pattern of the plating seed layer 14 exposed in the first and second photoresist layers 15, 16 corresponds to the pattern of the second conductive wiring layer 19 to be formed.

The second conductive circuit layer 19 formed in the gap between the first strip region 152 and the second strip region 162 is a plurality of conductive traces 191, and the width of the conductive traces 191 is a corresponding adjacent The width of the gap between the first strip region 152 and the second strip region 162, that is, L3, it is understood that if only the first or second photoresist layer 15, 16 is formed, the conductive trace 191 The width of the film should be L1 or L2, and the width of the conductive line 191 obtained by forming the first photoresist layer 15 and the second photoresist layer 16 is L3, and L3 is much smaller than L1 and L2, that is, under the same conditions. The conductive layer 191 obtained by the method for manufacturing the circuit board of the present invention can be made thinner than the conductive line obtained by forming only the first or second photoresist layers 15 and 16.

In a ninth step, referring to FIG. 12, a solder resist layer 21 is formed on the surface of the conductive layer 18 and the surface of the dielectric layer 11 exposed in the conductive layer 18, thereby obtaining the circuit board 20.

A part of the conductive layer 18 is exposed to the solder resist layer 21 to form an electrical connection pad 22 .

In another embodiment, the plating seed layer 14 may not be formed in the third step, but after being patterned in the fifth step to form the patterned first and second photoresist layers 15, 16, after being exposed to the patterned The surface of the dielectric layer 11 in the first and second photoresist layers 15 and 16 is formed by electroplating, black shadow or electroless plating, and then electroplating is performed on the surface of the sixth step. The surface of the layer 14 is formed with a step of forming the conductive layer 18. At this time, since the conductive layer 18 corresponds to the plating seed layer 14, the conductive layer 18 and the plating seed layer 14 form the second conductive wiring layer 19 without performing the above step 8. The step of removing the electroplated seed layer 14 that is not covered by the conductive layer 18 is removed.

In other embodiments, the electroplated seed layer 14 may not be formed, but the conductive layer 18 may be directly formed by other currentless plating methods.

In the method of fabricating the circuit board of the embodiment of the present invention, the first and second photoresist layers 15 and 16 are formed twice, and the second light is made, compared to the prior art, in which only one photoresist layer 15 or 16 is formed. The resist layer 16 is formed in the gap of the first photoresist layer 15 and forms a conductive line 191 in the gap between the adjacent first and second photoresist layers 15 and 16 by electroplating, and the first and second photoresists are formed twice. The gap between the first and second photoresist layers 15 and 16 obtained by the layers 15 and 16 can be made smaller. Therefore, the method for fabricating the circuit board of the embodiment of the present invention can produce a thinner conductive line.

In addition, in the prior art, a thinner conductive layer is obtained by thinning the photoresist layer. However, the thinned photoresist layer limits the thickening of the circuit layer when the circuit is formed by electroplating, that is, only a thin circuit layer can be obtained, and the thin circuit layer has a risk of disconnection and the like. The circuit board can be fabricated without thinning the thickness of the photoresist layer to produce a thinner conductive line.

However, the above description is only a preferred embodiment of the present invention, and the claim of the present invention cannot be limited thereby. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included in the following claims.

11‧‧‧Dielectric layer

12‧‧‧ Conductive circuit layer

17‧‧‧conductive column

19‧‧‧Second conductive circuit layer

21‧‧‧ solder mask

20‧‧‧ boards

Claims (10)

A method for manufacturing a circuit board, comprising the steps of: providing a circuit substrate, the circuit substrate comprising a dielectric layer and a conductive circuit layer formed on one side of the dielectric layer; forming a plurality of blind holes on the circuit substrate, and Forming a surface of a portion of the conductive circuit layer from the blind via; forming a patterned first photoresist layer on a side of the circuit substrate away from the conductive circuit layer; away from the conductive trace on the circuit substrate Forming a patterned second photoresist layer on the layer side, wherein the patterned second photoresist layer is formed in a gap of the patterned first photoresist layer and is opposite to the patterned first photoresist layer Intersecting a conductive pillar in the blind hole, and forming a conductive layer in the patterned gap between the first and second photoresist layers, the conductive pillar electrically connecting the conductive circuit layer and the conductive layer; And removing the first and second photoresist layers to form a circuit board. The method of manufacturing the circuit board of claim 1, wherein the dielectric layer comprises an opposite first surface and a second surface, and the conductive circuit layer is embedded on the first surface of the dielectric layer The conductive circuit layer includes a third surface and a fourth surface opposite to the third surface, the third surface is flush with the first surface, and the fourth surface is buried in the dielectric Within the layer. The method of manufacturing the circuit board of claim 2, wherein the manufacturing method of the circuit substrate comprises: providing a carrier board; forming a conductive circuit layer on a side of the carrier board; Forming the dielectric layer such that the dielectric layer covers the conductive wiring layer; removing the carrier plate to form the circuit substrate. The method of fabricating a circuit board according to claim 1, wherein the blinding is performed by an electroplating process The holes are filled to form the conductive pillars, and the conductive layers are formed in the patterned gaps of the first and second photoresist layers. The method for fabricating a circuit board according to claim 4, wherein a plurality of blind holes are formed on the circuit substrate, and a patterned first light is formed on the circuit substrate away from the conductive circuit layer side. Before the resist layer, further comprising the steps of: forming a plating seed layer on a surface of the dielectric layer of the circuit substrate remote from the conductive circuit layer and a hole wall of the blind hole; removing the first and second photoresists The layer further includes the step of removing the electroplated seed layer that is not covered by the conductive layer. The method of fabricating a circuit board according to claim 5, wherein the thickness of the plating seed layer is much smaller than the thickness of the conductive layer, and etching is performed by a rapid etching to remove the layer not covered by the conductive layer. Electroplating seed layer. The method of fabricating a circuit board according to claim 4, wherein after the circuit substrate is formed away from the conductive circuit layer side, the patterned second photoresist layer is formed, and the blind via is filled Forming the conductive pillars, and before the patterned first and second photoresist layer gaps form the conductive layer, further comprising the steps of: forming the inner wall of the blind via, and patterning the first And forming a plating seed layer with the second photoresist layer gap. The method of fabricating a circuit board according to claim 5, wherein the plating seed layer is formed by a blackening, black shadow or electroless plating process. The method of manufacturing the circuit board of claim 1, wherein after the removing the first and second photoresist layers, the method further includes: a surface on the conductive layer and a portion exposed to the conductive layer The surface of the dielectric layer forms a solder resist layer. The method of fabricating a circuit board according to claim 1, wherein the first photoresist layer is a dry film, and the second photoresist layer is a liquid photoresist layer formed by printing.