CN101325084A - Method for providing dynamic voltage bias to interleaved memory array and its realization circuit - Google Patents

Abstract

The invention belongs to the technical field of integrated circuits, in particular to a method for providing a dynamic bias voltage to an array of intersecting resistance conversion memory cells. The cross-type memory array relies on the electric signal applied to the two crossed metal wires to perform the selection operation. The present invention designs a resistance conversion that can dynamically generate voltage bias applied to other non-operating metal wire pairs according to the resistance distribution of the array and the difference of the external operation signal, so that the high and low resistance states have a larger ratio Interleaved arrays of type memory cells work reliably.

Description

Method for providing dynamic voltage bias to interleaved memory array and its realization circuit

technical field

The invention belongs to the technical field of large-scale digital integrated circuits, and specifically relates to a method for providing dynamic voltage bias to a cross-type resistive storage array and a circuit for realizing the same.

Background technique

Memory occupies an important position in the semiconductor market. Only DRAM (Dynamic Random Access Memory) and FLASH account for 15% of the market. With the continuous popularization of portable electronic devices, the non-volatile memory market is also growing. However, the size of traditional non-volatile memory is close to its physical limit. It is reported that the limit of FLASH technology is around 32nm, which forces people to look for the next-generation non-volatile memory with better performance. Recently, resistive random access memory (RRAM) has attracted high attention because of its high density, low power consumption, and low cost. The materials used include phase change materials [1], doped SrZrO3[2], ferroelectric material PbZrTiO3[3], ferromagnetic material Pr1-xCaxMnO3[4], binary metal oxide material[5], organic material[6], etc.

At present, resistance switching memory devices mainly adopt a 1T1R structure, that is, a gate device (such as a diode, a triode, a field effect transistor, etc.) and a storage resistor form a memory unit. This kind of storage unit has the advantages of simple structure, small inter-unit interference, fast reading speed, simple peripheral circuit design, etc., so it is widely used. Figure 1 shows a memory array composed of such 1T1R cells. However, for high-density mass storage, the cell structure of 1T1R does limit the further improvement of storage density. There are two reasons: 1) Generally speaking, the transistor area is larger than the area of the storage resistor, so the storage density is limited by the transistor area. 2) Since the gate transistor of each memory cell will consume the area of the silicon wafer, the memory resistors cannot be stacked to form a three-dimensional memory array.

For the above two problems, an ideal solution is to be able to manufacture a reliable cross-point storage array. The cross-point memory array means that there is no gating device in the memory cell, and the memory resistor is located at the intersection of two metal lines. By applying different voltages to the two intersecting metal lines, the memory resistor at the intersection Implement the action. As shown in Figure 2, it is a diagram of a cross-type storage array.

The key issue in designing a cross-point memory array is to reduce the influence of leakage current through the design of peripheral circuits. Because for the cross-type resistive memory array, a resistive network is actually formed. This network has a complicated leakage current path, so a large interference signal will be generated, which will affect the functional correctness of the memory array operation.

For interleaved memory arrays, in order to reduce the impact of leakage current, the usual practice is to provide a clamped bias voltage Veq[7], which is used to keep the two ends of the non-selected memory cells at the same potential. Thereby limiting the path of leakage current. In the traditional implementation, the bias voltage of this clamp generally adopts a fixed value, the most common ones are V/2 and V/3 bias schemes [8], and it is difficult to adapt the fixed bias voltage to the array. Coordination and the change of the added operation signal, so the reliable operation of the interleaved memory array cannot be guaranteed.

The present invention proposes to provide a dynamic bias voltage for the interleaved memory array, which is characterized in that the voltage bias can be adjusted according to the state of each resistor in the array and the external operating signal, so that the bias voltage Veq can obtain an optimal value . Such a dynamic bias scheme can ensure reliable operation of the interleaved memory array.

Contents of the invention

The object of the present invention is to propose a method for providing dynamic voltage bias to an interleaved memory array. This dynamic bias voltage can be dynamically adjusted according to the distribution of the array resistance and the external operating signal, so that it can suppress the leakage current with an optimal value and improve the reliability of the interleaved memory array. At the same time, a circuit for realizing the dynamic voltage bias is also provided.

The method for providing dynamic voltage bias to the interleaved memory array proposed by the present invention includes two parts: the dynamically biased interleaved memory array and the algorithm for generating the dynamic bias voltage. Wherein, the cells of the dynamically biased interleaved memory array are composed of resistance-switching memory media. In this array, a dynamic bias voltage is obtained by using an algorithm for generating a dynamic bias voltage. The algorithm samples the current flowing into the selection bit line of the memory array during operation, and generates a dynamic bias according to the sampled signal. This algorithm can efficiently find the optimal value of dynamic bias. Specific steps are as follows:

(1) First apply a voltage Vread on the bit line selected by the memory array, and the voltage Vread is 1V to 5V;

(2) Apply a dynamic bias voltage Veq on the unselected word line and the unselected bit line, and the initial value of the Veq voltage is zero;

(3) Sample the current flowing into the selected bit line, if the current is not zero, add a small step value ΔVeq to the voltage Veq, and repeat step (2); if the current is close to zero, continue Next step; here, ΔVeq is generally taken as 0.01V ~ 0.05V;

(4) Generate a small offset to the voltage Veq and apply it to the unselected word line and the unselected bit line; the size of this offset is generally 0.1V to 0.2V;

(5) The state of the selected memory cell is judged from the current flowing in the bit line.

The invention proposes a scheme for designing a cross-type resistance switching memory. This scheme can be applied to resistance switching memory cells with two-state resistance values that differ greatly.

Description of drawings

Fig. 1 adopts the memory array of 1T1R (one gating device and one storage resistance) cell structure.

Figure 2 Interleaved resistance switching memory array.

Fig. 3 The parasitic leakage current path in the interleaved resistive switching memory array.

Figure 4 is the peripheral circuit diagram of the cross-type resistance switching memory.

Fig. 5 The read operation clamping bias scheme of the interleaved resistance switching memory array.

Fig. 6 is an implementation diagram of a read operation of a cross-type resistance switching memory array.

Fig. 7 Simulation diagram of the signal noise of the read operation of the cross-type resistance switching memory array.

Fig. 8 The dynamic bias generation algorithm of the interleaved resistive switching memory array.

FIG. 9 is a logical block diagram of a dynamic bias generating circuit of a cross-type resistance switching memory array.

Fig. 10 is an embodiment of generating dynamic bias voltage.

FIG. 11 is a simulation of the read operation current of an interleaved resistive switching memory array using a dynamic bias scheme.

Detailed ways

The present invention will be described in more detail below with reference to the illustrations and examples. The present invention provides preferred embodiments, but should not be construed as being limited to the embodiments set forth herein.

Where the referenced figures are schematic illustrations of idealized embodiments of the invention, the illustrated embodiments of the invention should not be construed as limited to the specific shapes of the regions shown in the figures.

It will be understood that when an element is referred to as being "on" or "extending over" another element, the element may be directly "on" or "extend" directly on the other element, or it may also be There is an insert element. In contrast, when an element is referred to as being "directly on" or "directly extending over" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly "connected" or "directly coupled" to another element, there are no intervening elements present.

Figure 1 shows a resistance switching memory array using a 1T1R cell structure. The memory cell is composed of a programmable resistor 120 and a gating device 100 . The gating device 100 may be a diode as shown in the figure, or a device with a switching function such as a MOS transistor or a bipolar transistor. In this memory array, memory cells can be isolated from each other by gate devices, thereby reducing interference between cells. For example, in the operation 120, only the gating device 100 is turned on, and the rest of the gating devices are turned off, so only the storage resistor 120 can be affected by the external electrical signal.

FIG. 2 shows a cross-point resistive switching memory cell array. The memory cell 120 is connected between the metal wires 200 and 210 . A storage unit is positioned where the metal wires (200-201) intersect with the metal wires (210-213). Taking the operation of the storage unit 120 as an example, different voltage signals need to be applied to the metal wires 200 and 210 , and the two electrical signals act simultaneously to perform corresponding operations on it. For the units (such as 121 ) that do not need to be operated in the array, it is hoped that they will not be affected by the electrical signal and keep the original state. However, since these resistive memory cells form a resistive network, there are some paths for parasitic leakage currents. The parasitic leakage current will seriously degrade the performance of the memory, and even cause erroneous operation, which can be manifested as: 1) Misreading, because of the influence of leakage current, other sensitive devices cannot correctly distinguish the state of the storage resistor; 2) Miswriting In, the leakage current acts on unselected cells, causing them to flip their states undesirably.

FIG. 3 shows possible parasitic leakage current paths in an interleaved memory array. The storage unit 300 is a unit that needs to be operated, and the driving voltage 330 is applied to the corresponding metal wire 311 while the metal wire 321 is grounded. At this time, the voltage across the memory cell 300 is equal to the driving voltage. However, in this resistive network, there is a parasitic current path from 311 to 321 as shown by dashed line 350 . This parasitic path passes through the resistor 300 , the wire 320 , the resistor 302 , and the resistor 303 until it flows to the ground through the wire 321 . Assuming that the selected storage resistor 300 is high-resistance, but unfortunately the resistors 301, 302, and 303 are all low-resistance, then this leakage current has a great influence on the operating current, and even affects normal operation. If a read operation is applied to 300 , the resulting current is actually the sum of the current flowing through 300 and the leakage current, so it cannot represent the resistance state of 300 . If the write operation is applied to 300 , the storage resistors 301 - 302 will also pass a relatively large current or voltage signal, thereby causing their states to be deflected.

FIG. 4 shows a system circuit diagram of an interleaved array memory. 450-453 are resistance switching memory cells constituting the memory array, and they are simultaneously acted upon by the word line circuit (400, 401) and the bit line circuit (420, 421). The function of the word line circuit (400, 401) is to input according to the row address. Rows that need to be operated are selected, and offset Veq (410, 411) is provided to the rows that do not need to be operated. The bit line circuit (421, 422) selects the column to be operated according to the column address input, and selects the electric signal to be added to the selected bit line according to the data input. Sense amplifier 440 is used to sense the resistance state of the selected resistive memory cell. Since there will be a relatively large leakage current in the interleaved memory array, the sense amplifier must be able to eliminate the influence of the leakage current.

Figure 5 shows a biasing scheme for a read operation of an interleaved memory array. VBLsel 500 is the voltage bias applied to the selected bit line, and VWLsel 510 is the voltage bias applied to the selected word line, which is equal to the ground potential. The voltage bias applied to the unselected bit lines is Veqb (520-524), and the voltage bias applied to the unselected word lines is Veqw (511-514). It can be seen from the figure that the voltage signal applied to the storage resistor in the selection operation is equal to Vblsel500, and the voltage signal at both ends of the storage resistor at the intersection of the non-selected bit line and the selected word line is equal to Veqb. The voltage signals across the other storage resistors in the array are then equal to (Veqb-Veqw). The read operation of the resistance conversion memory cell is to apply a certain voltage to the memory cell, and then distinguish the magnitude of its current, so the influence of the leakage current on the signal current should be minimized. An ideal biasing method is to select Veqw=Veqb=VBLsel. In this case, theoretically, the current flowing from the selected bit line is equal to the current flowing through the selected storage resistor, and the storage resistor at the intersection of the selected word line and the non-selected word line also has a current flowing, but it does not affect the readout. signal current. The other memory resistors at the intersection of the unselected word line and the unselected bit line have no current flow because their ends are clamped at equal potential. However, because in the array, the parasitic path changes with the resistance of each memory cell, and due to the mismatch of the parameters of the switch tube and the resistance of the bit line, a fixed Veq cannot be well clamped. Therefore, the idea of generating dynamic Veq is proposed in this patent, so that Veq can perform dynamic self-adjustment according to the resistance network conditions and the applied operating voltage, and reduce the influence of leakage current as much as possible.

FIG. 6 shows a readout scheme of an interleaved memory. 600 is the clamping voltage, and its function is to limit the magnitude of the leakage current. 610 is a storage resistor to be read, and its two ends are connected to metal wires 632 and 643 . The selection is made by the cooperation of metal wires 632 and 643 . A certain voltage is applied to the metal wire 632, and the metal wire 643 is grounded, so a path from 632 to 643 is formed. The read current flows from the metal wire 632, through the storage resistor 610, and then to ground. The sense amplifier senses the current flowing into 632 to determine the resistance state of the selected memory cell. In this solution, the switch (such as 620) can be replaced by an N-type MOS transistor, and in order to satisfy its smaller on-resistance, it is selected to have a larger width-to-length ratio. Veq (600) is the clamping voltage that biases the ungated word line (eg, 640) and the ungated bit line (eg, 630) at equal potentials. If the voltage bias applied to the metal wire 632 is constant, the current flowing into it varies with Veq.

FIG. 7 shows the simulation results for the read operation of the 256×16 interleaved array in FIG. 6 . In the simulation, we adopted such parameters: the low resistance state resistor is 2k, and the high resistance state resistance is 100k. Since the resistance value of the low-resistance state is relatively low, there will be more parasitic leakage current branches. We simulated the leakage current in two cases, which are: 1) the case of the largest leakage current, that is, all unselected memory cells are in a low-resistance state; 2) the case of the smallest leakage current, that is, all unselected memory cells cells are in a high-impedance state. In both cases. We also simulated the cases where the selected cells are in the high-impedance state and the second-resistance state. Curves 800 and 810 show the variation of the current flowing in the selected bit line and the selected storage resistor as a function of Veq in case 1. Curve 840 represents the signal-to-noise ratio, that is, the ratio of the current actually flowing through the storage resistor to the leakage current. It can be seen from the figure that the signal-to-noise ratio increases with the increase of Veq, and reaches the maximum value at a certain value. This value approximates the read voltage on the selected bit line. At the same time, we also found that the current flowing into the selected bit line decreases with the increase of Veq, and the value of Veq with the largest signal-to-noise ratio is very close to the value of Veq when the current flowing into the selected bit line is 0. Let's briefly introduce the meaning of the other curves. 801, 811, 841 correspond to case 1 where the selected memory cell is low resistance. 802, 812, 842 correspond to the case that the selected memory cell in case 2 is high resistance, and 803, 813, 843 correspond to the case that the storage resistor is low resistance.

Figure 8 shows the basic algorithm for generating dynamic Veq. According to the simulation results in Figure 7, we have come to the conclusion that if a suitable Veq can be provided, the signal-to-noise ratio can reach a larger value, so that the difference between high resistance and low resistance can be distinguished, and the leakage current can be minimized Impact. The algorithm is described as follows:

(1) Apply a voltage Vread on the bit line selected by the memory array, and the size of Vread is between 1V and 5V;

(2) Apply a dynamic bias voltage Veq on the unselected word line and the unselected bit line, and the initial value of the Veq voltage is zero;

(3) Sample the current flowing into the selected bit line, if the current is not zero, add a small step value ΔVeq to the voltage Veq, and repeat the second step; if the current is close to zero, continue to the next step ; Here, ΔVeq is generally taken as 0.01V ~ 0.05V;

(4) Generate a small offset to the voltage Veq and apply it to the unselected word line and the unselected bit line; the size of this offset is generally 0.1V to 0.2V;

(5) The state of the selected memory cell is judged from the current flowing in the bit line.

FIG. 9 shows a logic block diagram of a circuit for generating dynamic Veq. The output terminal of a reading voltage generation module 900 is connected with the current sampling module 901, and the output of the latter is connected with the dynamic voltage Veq generation module 902 at the same time, and one end of the path selection switch S1 or S2 is connected with the output of the dynamic voltage Veq generation module, and the other end It is connected with the current sampling module 901. Through the following we analyze each circuit module. Block 900 is a read voltage block that generates a voltage that is applied to a selected bit line. Reading the voltage causes a current to flow into the selected bit line, and the current sampling module 901 samples this current signal. The signal generated by the sampling is used as the input of the module 902, and the module 902 generates the bias voltage Veq according to this signal. Variations in the bias voltage Veq in turn affect the amount of current flowing into the selected bit line. When the loop is balanced, the bias voltage Veq will cause the current flowing into the selected bit line to reach a very small value. At this time, we call the bias voltage Veq the balanced voltage Veq. When this balance point is found, we shift the bias voltage Veq a small amount, and then read the current value flowing into the bit line.

Figure 10 shows an implementation circuit diagram for generating dynamic bias. A sampling resistor 1000 with a size of several ohms to hundreds of ohms (such as 5 ohms-500 ohms) is connected in series on the bit line, one end of which is connected to the read voltage generating module, and the other end is connected to the bit line for selection operation. At the same time, the two ends of the sampling resistor 1000 are respectively connected to the source terminals (or drain terminals) of the MOS transistors 1040a and 1040b, and the drain terminals (or source terminals) of the MOS transistors 1040a and 1040b are connected to the positive and negative input terminals of the amplifier 1010 , and their gates are connected to the control signal 1020 . The output of the amplifier 1010 is connected to the gate of the PMOS transistor 1030 , the drain of the PMOS transistor is connected to the resistor 1031 , and is connected to the base and collector of the transistor 1032 , and the emitter of the transistor 1032 is connected to the resistor 1033 . The source terminal (or drain terminal) of the MOS transistor 1041 a is connected to the collector of the triode 1032 , and the source terminal (or drain terminal) of the MOS transistor 1041 b is connected to the emitter of the triode 1032 . The gates of the MOS transistors 1041 a and 1041 b are connected to the control signal 1021 . Its working principle is: the read current is sampled through Rsample1000, and then the potential at both ends of Rsample is input to Amp1 through S1 and S2, and the charges at these two points are stored in C1 (1050_a), C2 (1050_b) for use in S1 (1040_a) , S2(1040_b)g keeps the voltage difference between the two input terminals of the amplifier after it is turned off. During the process of finding the balance point of the bias voltage Veq, S3 is turned on. When the balance is reached, the generated Veq makes the read current tend to 0, because when the current flowing through Rsample is larger, the output potential of the amplifier Amp1 (1010) is higher, and the current flowing through R1 is smaller, so the output voltage Veq is also smaller. Conversely, the larger the current flowing through Rsample, the higher the output voltage Veq. Because the amplification factor of the amplifier is very large (100db), the current flowing through Rsample can be kept at a small value. When the control signal Φ(1020) is low level, S1, S2, S3 are turned off, and S4 is turned on. At this time, Veq is shifted by 0.1V~0.2V compared with the balanced state. The triode is obtained. At this time, the dynamic bias voltage Veq is gated and output by S4. When the bias voltage Veq is applied to the memory array, the read current will inevitably increase, but the signal-to-noise ratio at this time is the optimum value or close to the optimum value, because the resistance state of the selected memory cell can be read correctly.

Figure 11 shows the simulation results for the implemented circuit. Fig. 11(a) shows the variation of the bias voltage Veq, that is, the read operation bias level 1101 is obtained from the equilibrium point level (1100) through level shifting. Figure (b) shows the variation of the read current 1120 and the current 1121 flowing through the memory cell with Veq. Before Veq shifts, both currents are very small and tend to 0. When Veq shifts, an effective read current is obtained. It can be seen that 1120 is 5.3μA, while 1121 is 0.7μA, and the signal-to-noise ratio is 7, which is close to the optimal situation, and the state of the storage resistor can be correctly distinguished.

references

[1] J. Maimon, E. Spall, R. Quinn, S. Schnur, "Chalcogenide-based nonvolatile memory technology", IEEE Proceedings of Aerospace Conference, p.2289, 2001.

[2] C.Y.Liu, P.H.Wu, A.Wang, W.Y.Jang, J.C.Young, K.Y.Chiu, and T.Y Tseng, "Bistable resistive switching of a sputter-deposited Cr-doped SrZrO3 memory film", IEEEEDL vol.26, p.351 , 2005.

[3] J.R.Contreras, H.Kohlstedt, U.Pooppe, R.Waser, C.Buchal, and N.A.Pertsev, "Resistive switching inmetal-ferroelectric-metal junctions", Appl.Phys.Lett.vol.83, p.4595 , 2003.

[4] A.Asamitsu, Y.Tomioka, H.Kuwahara, and Y.Tokura, "Current switching of resistive states inmagnetoresistive manganites", Nature (London) vol.388, p.50, 1997.

[5] I.G.Baek, M.S.Lee, S.Seo, M.J.Lee, D.H.Seo, .S.Suh, J.C.Park, S.O.Park, H.S.Kim, I.K.Yoo, U-InChung, and J.T.Moon, “Highly scalable non-volatile resistive memory using simple binary oxide drivenby asymmetric unipolar voltage pulses”, IEDMTech.Dig.p.587(2004).

[6] L.P.Ma, J.Liu, and Y.Yang, "Organic electrical bistable devices and rewriteable memory cells", Appl.Phys.Lett.vol.80, p.2997, 2002; L.D.Bozano, B.W.Kean, V.R.Deline , J.R.Salem, and J.C.Scott, "Mechanism for bistability in organic memory elements", Appl.Phys.Lett.vol.84, p.607, 2004.

[7] W Reohr, H Honigschmid, R Robertazzi ect. "Memories of tomorrow", IEEE circuits and devices magazine [8755-3996] Reohr yr: 2002 vol: 18iss: 5pg: 17

[8]YC Chen, CF Chen, SH Chen, CT Chen, ect."A New Thin Film, Cross-point Non-volatile memory usingthreshold switching properties of phase change Chalcognide", SSIC 2004.Proceedings.Vol.1, p. 685-690

Claims (4)

1. A method for providing a dynamic voltage bias to an interleaved memory array, characterized in that it comprises an interleaved memory array adopting a dynamic bias, and two parts for generating a dynamic bias voltage algorithm; The storage array selects the current of the bit line for sampling, and generates a dynamic bias according to the sampled signal. 2. The dynamic voltage bias method for interleaved memory array according to claim 1, characterized in that the specific steps of the algorithm for generating the dynamic bias voltage are as follows: (1) First apply a voltage Vread on the bit line selected by the memory array, and the voltage Vread is 1V to 5V; (2) Apply a dynamic bias voltage Veq on the unselected word line and the unselected bit line, and the initial value of the voltage Veq is zero; (3) Sample the current flowing into the selected bit line, if the current is not zero, add a small step value ΔVeq to the voltage Veq, and repeat step (2); if the current is close to zero, continue Next step; here take ΔVeq as 0.01V～0.05V; (4) Generate a small offset to the voltage Veq and apply it to the unselected word line and the unselected bit line; the offset is 0.1V to 0.2V; (5) The state of the selected memory cell is judged from the current flowing in the bit line. 3. A realization circuit of the dynamic voltage biasing method to the interleaved memory array as claimed in claim 1, characterized in that the Veq module and path selection switches S1 and S2 are generated by the read voltage generation module, the current sampling module, and the dynamic voltage The output terminal of the read voltage generation module is connected to the current sampling module, and the output of the latter is connected to the dynamic voltage Veq generation module. One end of the path selection switch S1 or S2 is connected to the output of the dynamic voltage Veq generation module, and the other end is connected to the current sampling module. connected to the sampling module. 4. The implementation circuit according to claim 3, characterized in that the sampling resistor is connected in series on the bit line, one end of which is connected to the read voltage generation module, and the other end is connected to the bit line for selection operation; meanwhile, the two ends of the sampling resistor are respectively Connect to the source or drain of two MOS transistors, the drain or source of the two MOS transistors are connected to the positive and negative input terminals of the amplifier, and their gates are connected to a control signal. The output of the amplifier is connected to the gate of a PMOS transistor, the drain of the PMOS transistor is connected to a resistor, and connected to the base and collector of a triode, the emitter of the triode is connected to the resistor, and the source or drain of a MOS transistor One end is connected to the collector of the triode, and the source or drain of the other MOS transistor is connected to the emitter of the triode; the gates of the two MOS transistors are connected to a control signal.

Images