CN115312097A - Multi-bit resistive random access memory writing circuit, method and memory device - Google Patents

Abstract

The invention discloses a multi-bit resistance variable random access memory write-in circuit, a method and a memory device, wherein the multi-bit resistance variable random access memory write-in circuit is connected with a memory unit and comprises the following steps: the device comprises a first voltage clamping module, a second voltage clamping module, a write-in current sampling module, a current comparison module and a turn-off control module; the first voltage clamping module and the second voltage clamping module are used for controlling the voltage at two ends of the memory unit not to change along with the change of the writing current; the write current sampling module is used for sampling the magnitude of write current flowing through the memory unit and outputting the sampling current to the current comparison module; the current comparison module is used for providing a preset current and generating a write-in turn-off control signal when the sampling current is close to or reaches the preset current so as to control the magnitude of the write-in current; the turn-off control module is used for interrupting the writing process according to the writing turn-off control signal. The invention realizes the constant-voltage low-power-consumption writing of the multi-bit RRAM memory array.

Description

Multi-bit resistive random access memory writing circuit, method and memory device

technical field

The invention relates to the technical field of integrated circuits, in particular to a multi-bit resistive random access memory writing circuit, method and memory device.

Background technique

Resistive Random Access Memory (RRAM) is a new type of non-volatile memory. Due to the characteristics of non-volatility, high integration and compatibility with CMOS technology, it has been used in the recently emerging neuromorphic computing widely used in circuits. RRAM is a two-terminal device, which usually consists of an inert metal as the upper electrode (Top Electrode, TE), an active metal as the lower electrode (Bottom Electrode, BE), and a metal oxide (commonly HfO2) between the two metal electrodes. ). When a certain positive bias is applied to the two metal electrodes, the electrons of the active metal will move like one end of the inert metal, thereby gradually forming conductive filaments (filament) in the oxide medium in the middle, making the RRAM into a low-resistance state. Procedures become Set procedures. If a reverse bias is applied to the two metal electrodes of the RRAM, the conductive filaments formed will gradually disappear, making the RRAM into a high-resistance state. This process is called the Reset process. Since the conductive filament has a memory effect after Set, the conductivity of RRAM still exists, so RRAM is also called "memristor". In the RRAM memory unit, the RRAM and a switching MOS transistor are connected in series to form a 1T1R cell, and the switching MOS transistor is used to control the reading and writing of the RRAM. 1T1R cell has three ports, the end of the MOS tube is called the source line (Source Line, abbreviated as SL), the end of the RRAM is called the bit line (Bit Line is abbreviated as BL), and the gate of the MOS tube is called A word line (Word Line, abbreviated as WL) is connected to each other through SL, BL and WL to form a large-scale RRAM memory array.

The current RRAM memory writing circuit is mainly pulse-type writing, that is, a pulse voltage sequence is applied to both ends of the RRAM, so that the conductive filaments of the metal oxide in the middle layer of the RRAM are formed or eliminated. This method generally controls the size of the RRAM resistance by controlling the width and amplitude of the write pulse, which requires an additional pulse generator, and the write power consumption is high due to frequent flipping of the level.

Therefore, the prior art still needs to be improved and developed.

Contents of the invention

In view of the above-mentioned deficiencies in the prior art, the object of the present invention is to provide a multi-bit resistive random access memory write circuit, method and memory device to solve the problem caused by the need for an additional pulse generator in the existing RRAM memory write circuit. The frequent inversion of the level leads to the problem of high writing power consumption.

Technical scheme of the present invention is as follows:

A multi-bit resistive random access memory write circuit connected to a memory unit, comprising: a first voltage clamp module, a second voltage clamp module, a write current sampling module, a current comparison module and a shutdown control module;

The first voltage clamping module is connected to a first reference voltage and connected to one end of the memory unit to generate a write current; the second voltage clamping module is connected to a second reference voltage and connected to one end of the memory unit The other end is connected; the first voltage clamping module and the second voltage clamping module are used to control the voltage at both ends of the memory unit not to change with the change of the write current;

The write current sampling module is respectively connected to the second voltage clamping module and the current comparison module for sampling the magnitude of the write current flowing through the memory unit and outputting the sampling current to the current comparison module. module;

The current comparison module is respectively connected with the write current sampling module and the shutdown control module, and is used to provide a preset current and generate a write shutdown control when the sampling current approaches or reaches the preset current signal to control the magnitude of the write current;

The shutdown control module is respectively connected with the current comparison module, the second voltage clamp module and the memory unit, and is used for interrupting the write process according to the write shutdown control signal.

In a further setting of the present invention, the first voltage clamping module includes: a first operational amplifier and a first MOS transistor; wherein,

The non-inverting input terminal of the first operational amplifier is connected to the first reference voltage, the inverting input terminal of the first operational amplifier is connected to the drain of the first MOS transistor, and the output of the first operational amplifier The terminal is connected to the gate of the first MOS transistor;

The drain of the first MOS transistor is also connected to one end of the memory cell, and the source of the first MOS transistor is connected to the write current;

The second voltage clamping module includes: a second operational amplifier and a second MOS transistor; wherein,

The inverting input terminal of the second operational amplifier is connected to the second reference voltage, the non-inverting input terminal of the second operational amplifier is connected to the drain of the second MOS transistor, and the output terminal of the second operational amplifier is connected to the second reference voltage. The gate connection of the second MOS transistor;

The drain of the second MOS transistor is also connected to the other end of the memory cell, and the source of the second MOS transistor is grounded.

In a further configuration of the present invention, the writing current sampling module includes a third MOS transistor; the gate of the third MOS transistor is connected to the gate of the second MOS transistor, and the drain of the third MOS transistor is connected to the gate of the second MOS transistor. The current comparison module is connected, and the source of the third MOS transistor is grounded.

In a further configuration of the present invention, the current comparison module includes: several current sources and switch MOS transistors connected in series with the current sources, and the switch MOS transistors are respectively connected to the writing current sampling module and the shutdown control module.

In a further setting of the present invention, the shutdown control module includes: an even number of inverters and a fourth MOS transistor; wherein,

The input end of the inverter is connected to the output end of the current comparison module, and the output end of the inverter is connected to the gate of the fourth MOS transistor;

The drain of the fourth MOS transistor is connected to the other end of the memory unit, and the source of the fourth MOS transistor is connected to the second voltage clamping module.

In a further setting of the present invention, the shutdown control module includes: an odd number of inverters and a fourth MOS transistor; wherein,

The input end of the inverter is connected to the output end of the current comparison module, and the output end of the inverter is connected to the gate of the fourth MOS transistor;

The drain of the fourth MOS transistor is connected to the other end of the memory unit, and the source of the fourth MOS transistor is connected to the second voltage clamping module.

In a further setting of the present invention, the multi-bit resistive random access memory writing circuit further includes: a fifth MOS transistor and a sixth MOS transistor; wherein,

The gate of the fifth MOS transistor is connected to the gate of the fourth MOS transistor, the drain of the fifth MOS transistor is connected to the gate of the second MOS transistor, and the source of the fifth MOS transistor Pole access to supply voltage;

The sixth MOS transistor is connected between the output terminal of the second operational amplifier and the gate of the second MOS transistor.

In a further setting of the present invention, the multi-bit resistive random access memory writing circuit further includes: a seventh MOS transistor, the gate of the seventh MOS transistor accesses the enable signal, and the drain of the seventh MOS transistor connected to the source of the third MOS transistor, and the source of the seventh MOS transistor is grounded.

Based on the same inventive concept, the present invention also provides a writing method applied to the above-mentioned multi-bit resistive random access memory writing circuit, which includes:

Keeping the voltage at both ends of the memory cell constant through the first voltage clamping module and the second voltage clamping module;

Sampling the magnitude of the write current flowing through the memory unit through the write current sampling module and outputting the sampling current to the current comparison module;

When the sampling current is close to or reaches the preset current, the writing process is interrupted through the shutdown control module; wherein, the magnitude of the preset current is adjusted by the current comparison module to control the magnitude of the writing current.

Based on the same inventive concept, the present invention also provides a memory device, which includes several memory units arranged in an array, and the multi-bit resistive random access memory writing circuit as described above, the multi-bit resistive random access memory The memory writing circuits are correspondingly connected to the memory units.

A multi-bit resistive random access memory writing circuit, method and memory device provided by the present invention, the multi-bit resistive random access memory writing circuit is connected with the memory unit, which includes: a first voltage clamping module, a second voltage clamping module Two voltage clamping modules, a writing current sampling module, a current comparison module and a shutdown control module; the first voltage clamping module is connected to a first reference voltage, and is connected to one end of the memory unit to generate a writing current; The second voltage clamping module is connected to the second reference voltage and connected to the other end of the memory unit; the first voltage clamping module and the second voltage clamping module are used to control the two ends of the memory unit The voltage at the end does not change with the change of the write current; the write current sampling module is respectively connected with the second voltage clamping module and the current comparison module, and is used to sample the current flowing through the memory unit. Write the magnitude of the current and output the sampling current to the current comparison module; the current comparison module is connected to the writing current sampling module for providing a preset current and when the sampling current is close to or reaches the preset current Generate a write shutdown control signal to control the magnitude of the write current; the shutdown control module is respectively connected to the current comparison module, the second voltage clamp module and the memory unit for A write process is interrupted according to the write shutdown control signal. The present invention uses the first voltage clamping module and the second voltage clamping module to keep the voltage at both ends of the memory cell constant, so that the voltage at both ends of the memory cell will not change with the change of the writing current, so that the writing of the memory cell can be controlled. The magnitude of the current is used to control the magnitude of the write resistance, so as to avoid the problem of high write power consumption caused by pulse write. Moreover, the present invention can adjust the size of the preset current through the current comparison module to adjust the size of the writing current. Since the voltage at both ends of the memory is fixed by the clamping module, the resistance of the memory cell can be indirectly known according to the size of the writing current. , so as to realize multi-bit write operation.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to the structures shown in these drawings without creative effort.

FIG. 1 is a functional module architecture diagram of a multi-bit resistive random access memory writing circuit in the present invention.

FIG. 2 is a schematic circuit diagram of a Set operation performed by a multi-bit RRAM writing circuit in the present invention.

FIG. 3 is a time-domain waveform diagram of related signals during the Set operation performed by the multi-bit RRAM writing circuit in the present invention.

FIG. 4 is a schematic circuit diagram of a Reset operation performed by a multi-bit RRAM writing circuit in the present invention.

FIG. 5 is a time-domain waveform diagram of relevant signals during the reset operation performed by the multi-bit resistive random access memory writing circuit in the present invention.

FIG. 6 is a schematic flow chart of a multi-bit resistive random access memory writing method in the present invention.

FIG. 7 is a schematic circuit diagram of a memory device in the present invention.

Each mark in the drawings: 100, first voltage clamping module; 200, second voltage clamping module; 300, write current sampling module; 400, current comparison module; 500, shutdown control module; 600, memory unit.

Detailed ways

The present invention provides a multi-bit resistive random access memory writing circuit, method and memory device, and a multi-bit resistive random access memory writing circuit. In order to make the purpose, technical scheme and effect of the present invention clearer and clearer, refer to The accompanying drawings give examples to further describe the present invention in detail. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

In the embodiments and claims, unless the article is specifically limited, "a", "an", "the" and "the" may also include plural forms. If there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. Significance or implicitly indicates the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of these features.

It should be further understood that the word "comprising" used in the description of the present invention refers to the presence of said features, integers, steps, operations, elements and/or components, but does not exclude the presence or addition of one or more other features, Integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Additionally, "connected" or "coupled" as used herein may include wireless connection or wireless coupling. The expression "and/or" used herein includes all or any elements and all combinations of one or more associated listed items.

Those skilled in the art can understand that, unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this invention belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be understood to have meanings consistent with their meaning in the context of the prior art, and unless specifically defined as herein, are not intended to be idealized or overly Formal meaning to explain.

In addition, the technical solutions of the various embodiments can be combined with each other, but it must be based on the realization of those skilled in the art. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that the combination of technical solutions does not exist , nor within the scope of protection required by the present invention.

The inventors have found through research that the current RRAM memory write circuit is mainly pulse-type write, that is, a pulse voltage sequence is applied to both ends of the RRAM to form or eliminate the conductive filaments of the metal oxide in the middle layer of the RRAM. This method generally controls the size of the RRAM resistance by controlling the width and amplitude of the write pulse, which requires an additional pulse generator, and the write power consumption is high due to frequent flipping of the level. In addition, traditional RRAM has only two states: High Resistance State (High Resistance State, HRS) and Low Resistance State (Low Resistance State, LRS), which means that an RRAM cell can only represent 1 bit of information. Recently, emerging in-memory computing circuits have Multi-bit RRAM has been used to increase unit storage density, but the corresponding high-efficiency multi-bit RRAM memory writing technology is still lacking.

In view of the above technical problems, the present invention provides a multi-bit resistive random access memory constant voltage write circuit, method and memory device. The voltage at both ends of the memory unit is maintained by the first voltage clamping module and the second voltage clamping module. Fixed, so that the voltage at both ends of the memory cell will not change with the change of the write voltage, so that the write resistance can be controlled by controlling the write current of the memory cell, so as to avoid frequent flipping of the pulse write level The problem of high write power consumption is caused. Moreover, the present invention can adjust the magnitude of the preset current through the current comparison module to adjust the magnitude of the write current, so that the magnitude of the resistance of the memory unit can be obtained indirectly, and a multi-bit write operation can be realized.

Please refer to FIG. 1 to FIG. 5 at the same time. The present invention provides a preferred embodiment of a multi-bit RRAM writing circuit.

As shown in FIG. 1 , a multi-bit resistive random access memory writing circuit provided by the present invention is connected to a memory unit 600, and includes: a first voltage clamping module 100, a second voltage clamping module 200, a writing circuit The current sampling module 300 , the current comparison module 400 and the shutdown control module 500 . The first voltage clamping module 100 is connected to a first reference voltage and connected to one end of the memory unit 600 to generate a write current; the second voltage clamping module 200 is connected to a second reference voltage and connected to the The other end of the memory unit 600 is connected; the first voltage clamping module 100 and the second voltage clamping module 200 are used to control the voltage at both ends of the memory unit 600 not to change with the change of the write current; The writing current sampling module 300 is respectively connected with the second voltage clamping module 200 and the current comparison module 400, and is used for sampling the magnitude of the writing current flowing through the memory unit 600 and outputting the sampling current to the The current comparison module 400; the current comparison module 400 is respectively connected with the write current sampling module 300 and the shutdown control module 500, for providing a preset current and when the sampling current approaches or reaches the preset When the current is set, a write shutdown control signal is generated to control the magnitude of the write current; the shutdown control module 500 is connected to the current comparison module 400 and the memory unit 600 respectively, for Entering the shutdown control signal interrupts the write process.

The working principle of the present invention is: the first voltage clamping module 100 and the second voltage clamping module 200 are respectively connected to both ends of the memory unit 600, wherein the second voltage clamping module 200 passes through the The shutdown control module 500 is connected to the memory unit, the first voltage clamping module 100 is connected to the first reference voltage as the first clamping level, and the second voltage clamping module 200 is connected to the second reference voltage The voltage is used as the second clamping level, and is added to the two ends of the memory cell 600 respectively, so that the voltage at the two ends of the memory cell remains fixed and will not change with the change of the write current, so that the write of the memory cell can be controlled. The size of the input current is used to uniquely control the size of the write resistance. It can be seen that the method of constant voltage writing in the present invention does not require an additional pulse generator compared with pulse writing, and avoids power failure caused by frequent level reversals. high consumption problem. Wherein, the current comparison module 400 can provide a preset current, sample the write current flowing through the memory unit 600 through the write current sampling module 300, and output the sampled current to the current comparison module 400, when the When the sampling current approaches or reaches the preset current, the writing process is interrupted through the shutdown control module 500 . The output voltage of the current comparison module 400 will change with the change of the writing current, so the magnitude of the writing current can be controlled by adjusting the magnitude of the preset current, because the voltage at both ends of the memory is clamped and fixed, Therefore, the magnitude of the resistance of the memory unit 600 can be obtained indirectly according to the magnitude of the write current, thereby realizing the write function of the multi-bit RRAM. Therefore, the present invention implements the writing of multi-bit RRAM resistance values by means of low power consumption and constant voltage writing.

It should be noted that the memory unit 600 includes a resistive random access memory RRAM and a memory MOS transistor M1 connected in series with it to form a 1T1R cell, and the memory MOS transistor M1 is used to control reading and writing of the resistive random access memory RRAM. Wherein, the gate of the memory MOS transistor M1 is connected to the word line, the source of the memory MOS transistor M1 is connected to the source line, the drain of the memory MOS transistor M1 is connected to one end of the resistive random access memory RRAM, and the other end of the resistive random access random access memory RRAM Connect one end to the bit line.

The writing process of the memory unit 600 includes a Set process (RRAM changes from a high resistance state to a low resistance state) and a Reset process (RRAM changes from a low resistance state to a high resistance state). When the writing circuit performs the Set operation, the first voltage clamping module 100 is connected to the source of the memory MOS transistor M1, and a constant writing voltage is applied to both ends of the memory unit 600, and its resistance value will gradually decrease. Therefore, the write current flowing through the memory unit 600 will gradually increase, and with the increase of the write current, the sampling current will increase with the increase of the write current, so that the output voltage of the current comparison module 400 will gradually decrease. Limit the magnitude of the write current so that the write current reaches a certain value and then shut off, and the write process ends, so that the resistance of the write memory unit 600 can be controlled. When the writing circuit executes the Reset operation, the first voltage clamping module 100 is connected to the resistive random access memory RRAM. During this process, the resistance value of the resistive random access memory RRAM changes from small to large, and the writing current gradually As the sampling current becomes smaller, the sampling current also gradually decreases. Correspondingly, the output voltage of the current comparison module 400 changes from low to high until the sampling current is 0.

Please refer to FIG. 2. In a further implementation of an embodiment, the first voltage clamping module 100 includes: a first operational amplifier A1 and a first MOS transistor P1; wherein, the non-inverting phase of the first operational amplifier A1 The input terminal is connected to the first reference voltage Vwrite, the inverting input terminal of the first operational amplifier A1 is connected to the drain of the first MOS transistor P1, and the output terminal of the first operational amplifier A1 is connected to the drain of the first operational amplifier A1. The gate of the first MOS transistor P1 is connected; the drain of the first MOS transistor P1 is also connected to one end of the memory unit 600 , and the source of the first MOS transistor P1 is connected to the write current Iwrite. The second voltage clamping module 200 includes: a second operational amplifier A2 and a second MOS transistor N2; wherein, the inverting input terminal of the second operational amplifier A2 is connected to a second reference voltage Vclamp, and the second operational The non-inverting input end of the amplifier A2 is connected to the drain of the second MOS transistor N2, the output end of the second operational amplifier A2 is connected to the gate of the second MOS transistor N2; the second MOS transistor N2 The drain is also connected to the other end of the memory unit 600, and the source of the second MOS transistor N2 is grounded.

Specifically, the non-inverting input terminal of the first operational amplifier A1 is connected to the first reference voltage Vwrite as the first clamping level, and the output terminal of the first operational amplifier A1 is connected to the gate of the first MOS transistor P1, so The inverting input terminal of the first operational amplifier A1 is connected to the drain of the first MOS transistor P1 to form a negative feedback loop. Wherein, the write current Iwrite is connected through the source of the first MOS transistor P1. The inverting input terminal of the second operational amplifier A2 is connected to the second reference voltage Vclamp as the second clamping level. The output terminal of the second operational amplifier A2 is connected to the gate of the second MOS transistor N2, and the non-inverting input terminal of the second operational amplifier A2 is connected to the drain of the second MOS transistor N2 to form a negative feedback loop. Wherein, the first MOS transistor P1 is a P-type MOS transistor, and the second MOS transistor N2 is an N-type MOS transistor. Under the action of the first operational amplifier A1 and the second operational amplifier A2, the voltage at both ends of the resistive random access memory RRAM is kept stable, clamped at a fixed value, and will not change with the change of the write current Iwrite Variety.

Please refer to FIG. 2 , in a further implementation of an embodiment, the write current sampling module 300 includes a third MOS transistor N3; the gate of the third MOS transistor N3 is connected to the gate of the second MOS transistor N2 The gate is connected, the drain of the third MOS transistor N3 is connected to the current comparison module 400 , and the source of the third MOS transistor N3 is grounded.

Specifically, the gate of the third MOS transistor N3 is connected to the gate of the second MOS transistor N2 to sample the write current Iwrite flowing through the memory unit 600 to obtain a sampling current, and input the sampling current into To the current comparison module 400 , by comparing the sampled current with the preset current provided by the current comparison module 400 , if the sampled current reaches or approaches the preset current, the shutdown control module 500 interrupts the writing process.

Please refer to FIG. 2, in a further implementation of an embodiment, the current comparison module 400 includes: several current sources (I1, I2...In) and switch MOS transistors (b0) connected in series with the current sources , b1...bn), the switching MOS transistors are connected to the write current sampling module 300 and the shutdown control module 500 respectively.

Specifically, the current comparison module 400 is a current mirror structure with a current source as the load, and the output of the current comparison module 400 is the voltage of the middle node Vmid where the current source is connected in series with the switching MOS transistor, and the size of Vmid will vary with The write current Iwrite varies, and forms a closed write current shutdown control loop with the shutdown control module 500 .

Please refer to FIG. 2 and FIG. 3 , in a further implementation of an embodiment, when the writing circuit performs a Set operation, the shutdown control module 500 includes: an even number of inverters and a fourth MOS transistor SW1; , the input end of the inverter is connected to the output end of the current comparison module 400, the output end of the inverter is connected to the gate of the fourth MOS transistor SW1; the fourth MOS transistor SW1 The drain is connected to the other end of the memory unit 600 , and the source of the fourth MOS transistor SW1 is connected to the second voltage clamping module 200 .

Specifically, the fourth MOS transistor SW1 is an N-type MOS transistor, and there are an even number of inverters, as shown in FIG. The inverter C2 is connected in series between the fourth MOS gate and the node Vmid (the output of the inverter C1 is Vmid_i, and the output of the inverter C2 is Vmid_d). As the write current Iwrite increases, the sampling current increases with increases gradually, while the node voltage Vmid gradually decreases. When Vmid is close to 0V, the inverter outputs high and low levels to turn off the fourth MOS transistor SW1, thereby turning off the writing current path of the memory unit 600 and completing self-interruption During the writing process, the time-domain waveform diagram of the corresponding signal is shown in FIG. 3 .

It can be seen that the writing process of the memory cell 600 is a negative feedback process, and the magnitude of the write current Iwrite of the memory cell 600 when it is turned off can be determined by changing the current magnitude of the current source (I1, I2, ... In), and because the memory The voltage at both ends of the cell 600 is fixed, so the write resistance of the memory cell 600 can be determined, thereby realizing the write function of the multi-bit RRAM.

Please refer to FIG. 4 and FIG. 5. In some embodiments, when the writing circuit performs a Reset operation, the shutdown control module 500 includes: an odd number of inverters and a fourth MOS transistor SW1; The input terminal of the inverter is connected to the output terminal of the current comparison module 400, the output terminal of the inverter is connected to the gate of the fourth MOS transistor SW1; the drain of the fourth MOS transistor SW1 is connected to the gate of the fourth MOS transistor SW1 The other end of the memory unit 600 is connected, and the source of the fourth MOS transistor SW1 is connected to the second voltage clamping module 200 .

Specifically, the principle of the Reset operation is the same as the principle of Set’s circuit D, both of which keep the voltage across the RRAM constant, sample the write current Iwrite to know the resistance of the RRAM, and then use negative feedback to turn off the write current. . The difference from the Set operation is that the direction of the write voltage of the memory cell 600 is opposite, the resistance value of the memory cell 600 increases from small to large, the write current Iwrite gradually decreases, and the Vmid voltage increases from low to high. Finally, the gate voltage of the second MOS transistor N2 becomes 0, so that the second MOS transistor N2 is turned off, and the write current path of the memory unit 600 is turned off. The time domain waveform diagram of the corresponding signal is shown in FIG. 5 . Since the direction of the write voltage of the memory cell 600 is opposite, the number of inverters is an odd number. In an implementation manner, the number of inverters may be one, such as the inverter C3 in FIG. 4 .

Please refer to FIG. 2. In a further implementation of an embodiment, the multi-bit resistive random access memory writing circuit further includes: a fifth MOS transistor SW2 and a sixth MOS transistor SW3; wherein, the fifth MOS The gate of the transistor SW2 is connected to the gate of the fourth MOS transistor SW1, the drain of the fifth MOS transistor SW2 is connected to the gate of the second MOS transistor N2, and the source of the fifth MOS transistor SW2 The pole is connected to the power supply voltage VDD; the sixth MOS transistor SW3 is connected between the output terminal of the second operational amplifier A2 and the gate of the second MOS transistor N2.

Specifically, when the write circuit performs the Set operation, there are two overlapping negative feedback loops, one is the negative feedback loop of the current comparison module 400 (N3→Vmid→SW1→N2→VG→N3), and the other is the bit The clamping voltage negative feedback loop of the line BL (Vin+→Amp1→VG→N2→Vin+, Vin+ is the node voltage of the common terminal of the fourth MOS transistor and the second MOS transistor). In the two negative feedback loops, the second MOS transistor N2 plays an important role, which may cause competition control and cause the loop to oscillate after writing. By adding the fifth MOS transistor SW2 and the sixth MOS transistor SW3 in the loop as switch tubes, the fifth MOS transistor SW2 is disconnected during the writing process, the sixth MOS transistor SW3 is closed, and normal writing is performed. The last sixth MOS transistor SW3 disconnects the clamping negative feedback loop, and the fifth MOS transistor SW2 closes so that the gate voltage VG of the second MOS transistor N2 has a fixed final value, thereby avoiding loop oscillation.

It should be noted that, when the write circuit executes the Reset operation, since the gate voltage VG of the second MOS transistor N2 will eventually become 0 and be turned off, there will be no oscillation problem, so when the Reset operation is executed, the The fifth MOS transistor SW2 and the sixth MOS transistor SW3 can be omitted.

Please refer to FIG. 2 and FIG. 4. In a further implementation of an embodiment, the multi-bit resistive random access memory writing circuit further includes: a seventh MOS transistor SW4, the gate of the seventh MOS transistor SW4 The enable signal W_EN is connected, the drain of the seventh MOS transistor SW4 is connected to the source of the third MOS transistor N3, and the source of the seventh MOS transistor SW4 is grounded.

Specifically, the seventh MOS transistor SW4 is an N-type MOS transistor, and the seventh MOS transistor SW4 is used as a switch to control the working state of the current comparison module 400. When the seventh MOS transistor SW4 is turned on ( That is, when the enable signal W_EN is at a high level), the current comparison module 400 can perform a current comparison operation, and when the seventh MOS transistor SW4 is turned off (that is, when the enable signal W_EN is at a low level), the current comparison module 400 stops work, that is to say, the working state of the entire writing circuit can be controlled by controlling the on-off of the seventh MOS transistor SW4.

Please refer to FIG. 6. In some embodiments, the present invention also provides a writing method applied to the above-mentioned multi-bit resistive random access memory writing circuit, which includes steps:

S100. Use the first voltage clamping module and the second voltage clamping module to keep the voltage at both ends of the memory unit constant; the details are as described in the embodiment of a multi-bit resistive random access memory writing circuit, and will not be repeated here.

S200. Sampling the magnitude of the writing current flowing through the memory unit through the writing current sampling module and outputting the sampling current to the current comparison module; specifically as described in an embodiment of a multi-bit resistive random access memory writing circuit, here No longer.

S300, when the sampling current approaches or reaches the preset current, interrupt the writing process by shutting down the control module; wherein, adjust the preset current through the current comparison module to control the writing current. The details are as described in the embodiment of a multi-bit resistive random access memory writing circuit, and will not be repeated here.

Please refer to FIG. 7. In some embodiments, the present invention also provides a memory device, which includes a plurality of memory cells arranged in an array, and the multi-bit resistive random access memory writing circuit as described above. The multiple Bit resistive random access memory writing circuits are correspondingly connected to the memory units.

Specifically, the multi-bit RRAM writing circuit is connected to the bit line BL, the source line SL, and the word line WL of the memory cells to form a memory array. In the memory array, by selecting the write voltage Vwrite of a certain column and setting it as a high level, and then turning on the word line WL voltage of a certain row, and by setting the current magnitude of different current sources, each memory cells one by one to perform multi-bit write.

In summary, a multi-bit resistive random access memory writing circuit, method and memory device provided by the present invention have the following beneficial effects:

The magnitude of the write current is controlled by adjusting the magnitude of the preset current, because the voltage at both ends of the memory is clamped and fixed, so that the resistance of the memory cell can be indirectly known according to the magnitude of the write current, thereby realizing a multi-bit resistance variable Write function of random access memory;

Compared with pulse writing, the method of constant voltage writing does not require an additional pulse generator, which avoids the problem of high power consumption caused by frequent level reversals, and thus can be a low-cost multi-bit RRAM memory array. power write.

It should be understood that the application of the present invention is not limited to the above examples, and those skilled in the art can make improvements or transformations according to the above descriptions, and all these improvements and transformations should belong to the protection scope of the appended claims of the present invention.

Claims (10)

1. A multi-bit resistive random access memory write circuit coupled to a memory cell, comprising: the device comprises a first voltage clamping module, a second voltage clamping module, a write-in current sampling module, a current comparison module and a turn-off control module;

the first voltage clamping module is connected with a first reference voltage and is connected with one end of the memory unit to generate a write-in current; the second voltage clamping module is connected with a second reference voltage and is connected with the other end of the memory unit; the first voltage clamping module and the second voltage clamping module are used for controlling the voltage of two ends of the memory unit not to change along with the change of the writing current;

the write current sampling module is respectively connected with the second voltage clamping module and the current comparison module and is used for sampling the magnitude of the write current flowing through the memory unit and outputting a sampling current to the current comparison module;

the current comparison module is respectively connected with the write current sampling module and the turn-off control module and is used for providing a preset current and generating a write turn-off control signal when the sampling current is close to or reaches the preset current so as to control the magnitude of the write current;

the turn-off control module is respectively connected with the current comparison module, the second voltage clamp module and the memory unit and is used for interrupting a writing process according to the writing turn-off control signal.

2. The multibit resistive random access memory write circuit of claim 1, wherein the first voltage clamping module comprises: the first operational amplifier and the first MOS tube; wherein,

the non-inverting input end of the first operational amplifier is connected to the first reference voltage, the inverting input end of the first operational amplifier is connected with the drain electrode of the first MOS tube, and the output end of the first operational amplifier is connected with the grid electrode of the first MOS tube;

the drain electrode of the first MOS tube is also connected with one end of the memory unit, and the source electrode of the first MOS tube is connected with the write-in current;

the second voltage clamping module comprises: the second operational amplifier and the second MOS tube; wherein,

the inverting input end of the second operational amplifier is connected with a second reference voltage, the non-inverting input end of the second operational amplifier is connected with the drain electrode of the second MOS tube, and the output end of the second operational amplifier is connected with the grid electrode of the second MOS tube;

the drain electrode of the second MOS tube is also connected with the other end of the memory unit, and the source electrode of the second MOS tube is grounded.

3. The multi-bit mram write circuit of claim 2, wherein the write current sampling module comprises a third MOS transistor; the grid electrode of the third MOS tube is connected with the grid electrode of the second MOS tube, the drain electrode of the third MOS tube is connected with the current comparison module, and the source electrode of the third MOS tube is grounded.

4. The multi-bit resistance random access memory write circuit of claim 1, wherein the current comparison module comprises: the current source switching circuit comprises a plurality of current sources and switch MOS tubes connected with the current sources in series, wherein the switch MOS tubes are respectively connected with a write-in current sampling module and a turn-off control module.

5. The multi-bit mram write circuit of claim 2, wherein the shutdown control module comprises: an even number of inverters and fourth MOS transistors; wherein,

the input end of the phase inverter is connected with the output end of the current comparison module, and the output end of the phase inverter is connected with the grid electrode of the fourth MOS tube;

the drain electrode of the fourth MOS tube is connected with the other end of the memory unit, and the source electrode of the fourth MOS tube is connected with the second voltage clamping module.

6. The multi-bit mram write circuit of claim 2, wherein the shutdown control module comprises: odd inverters and fourth MOS tubes; wherein,

the input end of the phase inverter is connected with the output end of the current comparison module, and the output end of the phase inverter is connected with the grid electrode of the fourth MOS tube;

the drain electrode of the fourth MOS tube is connected with the other end of the memory unit, and the source electrode of the fourth MOS tube is connected with the second voltage clamping module.

7. The multi-bit resistive random access memory write circuit of claim 4, further comprising: a fifth MOS transistor and a sixth MOS transistor; wherein,

the grid electrode of the fifth MOS tube is connected with the grid electrode of the fourth MOS tube, the drain electrode of the fifth MOS tube is connected with the grid electrode of the second MOS tube, and the source electrode of the fifth MOS tube is connected with a power supply voltage;

the sixth MOS tube is connected between the output end of the second operational amplifier and the grid electrode of the second MOS tube.

8. The multi-bit resistive random access memory write circuit of claim 3, further comprising: the grid electrode of the seventh MOS tube is connected with an enabling signal, the drain electrode of the seventh MOS tube is connected with the source electrode of the third MOS tube, and the source electrode of the seventh MOS tube is grounded.

9. A writing method applied to the multi-bit resistance random access memory writing circuit according to any one of claims 1 to 8, comprising:

the voltage at two ends of the memory unit is kept fixed through the first voltage clamping module and the second voltage clamping module;

sampling the magnitude of the write current flowing through the memory unit through a write current sampling module and outputting the sampling current to a current comparison module;

interrupting the writing process by turning off the control module when the sampling current approaches or reaches the preset current; the magnitude of the preset current is adjusted through the current comparison module to control the magnitude of the write current.

10. A memory device, comprising a plurality of memory cells arranged in an array, and the multi-bit resistance variable random access memory writing circuit according to any one of claims 1 to 8, wherein the multi-bit resistance variable random access memory writing circuits are respectively connected to the memory cells.

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