CN101309257A - Single board communication method and system based on internal integrated circuit bus - Google Patents
Single board communication method and system based on internal integrated circuit bus Download PDFInfo
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- CN101309257A CN101309257A CNA2008101330906A CN200810133090A CN101309257A CN 101309257 A CN101309257 A CN 101309257A CN A2008101330906 A CNA2008101330906 A CN A2008101330906A CN 200810133090 A CN200810133090 A CN 200810133090A CN 101309257 A CN101309257 A CN 101309257A
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Abstract
Disclosed are a single-board communication method and a system based on the internal integrated circuit bus; the communication method includes that an I2C device is divided into a plurality of groups; first in first out FIFO registers and I2C buses are respectively established for the groups; the I2C device is connected with the FIFO register of the group through the I2C bus of the group; the I2C device in the group obtains the bus right of use through the group arbitration, sends the data to the FIFO register of the group or reads data from the FIFO register of the group; a processor processes data interaction with the FIFO registers of the groups through sharing the random access memory RAM. The single-board communication method and the system solve the defect of the original arbitration applied in the inter-plate communication which adopts the I2C protocol when a plurality of single-plates are applied in a large transmission device; the inter-boards communication data is ensured to be in time and the transmission is reliable; the transmission quality is improved; compared with other methods used for solving the defect, the single-plate communication method and the system save the hardware cost of the device.
Description
Technical field
The present invention relates to the communications field, relate in particular to a kind of single-board communication method and system based on I2C (Inter Integrated-Circuit, internal integrated circuit) bus.
Background technology
Veneer One's name is legion in the large-scale transmission equipment network elements, the quality of communication between plates quality are the key factors that influences the system management quality.The method of current realization communication between plates is a lot, and a kind of more popular method is to adopt the I2C agreement to realize.But when veneer quantity more for a long time, the I2C arbitration by agreement mode of standard adopts the mode of " line with " to arbitrate, there is defective in this mode, causes the unusual and error code of bus easily, and the arbitration overlong time; This all might cause communication data to be lost or untimely, and communication quality can not get guaranteeing.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of single-board communication method and system based on the I2C bus, be applicable to the communication between plates of realizing in the large-scale transmission equipment network elements, solved the insecure problem of communication quality when adopting the I2C protocol communication in a fairly large number of equipment of veneer well, for large-scale transmission equipment provides a kind of reliable implementation method at veneer quantity communication between plates more for a long time.
In order to address the above problem, the invention provides a kind of single-board communication method based on internal integrated circuit I2C bus, comprising:
I2C equipment is divided into several groupings, sets up the first-in first-out register FIFO and the I2C bus of each grouping respectively; The I2C equipment of same grouping links to each other with the FIFO of this grouping by the I2C bus of this grouping; When the I2C equipment in the grouping is obtained the bus right to use by arbitration in organizing, data are sent among the FIFO of this grouping, or from this grouping FIFO reading of data;
Processor carries out data interaction by the FIFO of shared incoming memory RAM at random and each grouping.
Further, the FIFO of processor by RAM and each grouping carries out data interaction and is meant:
The FIFO of each grouping of poll receives data to RAM Shared from grouping FIFO successively;
Produce interrupt requests when having data to send to processor in the RAM Shared, notification processor receives; Processor is taken data away from RAM Shared, send to RAM Shared after the processing;
The data that RAM Shared is sent processor send to the FIFO of corresponding grouping.
Further, RAM Shared data that processor the is sent FIFO that sends to corresponding grouping is meant:
Processor sends in the data of RAM Shared and carries purpose I2C device address;
Preserve the corresponding situation of each I2C device address and grouping in the RAM Shared, determine the FIFO of the grouping of this data correspondence to send the data to this FIFO by purpose I2C device address.
Further, described method also comprises:
For the FIFO of each grouping a priority is set according to the importance of each group I2C equipment arbitration;
The FIFO of each grouping of poll is meant successively: according to each FIFO that divides into groups of order poll of priority.
Further, the FIFO of each grouping is divided into two sections, deposits the data that send to RAM Shared and receive from RAM Shared respectively;
RAM Shared is divided into two sections, deposits the data that send to processor and receive from processor respectively, reads and writes according to first in first out.
Further, described method also comprises:
Be unique sequence number of each packet allocation; For the FIFO of each grouping distribute one with the sequence number of this grouping sequence number one to one.
The present invention also provides a kind of single board communication system based on the I2C bus, comprises processor, several groupings, RAM Shared and processor;
Each grouping comprises a plurality of I2C equipment, first-in first-out register FIFO and I2C bus; The I2C equipment of same grouping links to each other with the FIFO of this grouping by the I2C bus of this grouping; When the I2C equipment in the grouping is obtained the bus right to use by arbitration in organizing, data are sent among the FIFO of this grouping, perhaps reading of data from this grouping FIFO;
FIFO, the processor of described RAM Shared and each grouping link to each other;
Described processor is used for carrying out data interaction by the FIFO of RAM and each grouping.
Further, the FIFO of processor by RAM and each grouping carries out data interaction and specifically is meant:
Processor is the FIFO of each grouping of poll successively, receives data to RAM Shared from each grouping FIFO; And when receiving the interrupt requests of RAM Shared, from RAM Shared, take data away, send to RAM Shared after the processing;
Described RAM Shared is used for producing interrupt requests when data will send to processor, and notification processor receives; And, these data are distributed to corresponding grouping FIFO when receiving after processor sends to the data of I2C equipment.
Further, carry purpose I2C device address in the data that processor sends;
RAM Shared is distributed to corresponding grouping FIFO with data and is meant:
Preserve the corresponding situation of each I2C device address and grouping in the RAM Shared, determine the FIFO of the grouping of this data correspondence to send the data to this FIFO by the purpose I2C device address of carrying in the data.
Further, the FIFO for each grouping is provided with a priority;
The processor FIFO of each grouping of poll successively is meant: processor is according to the FIFO of each grouping of order poll of priority.
Further, the FIFO of each grouping is divided into two sections, deposits the data that send to RAM Shared and receive from RAM Shared respectively;
RAM Shared is divided into two sections, deposits the data that send to processor and receive from processor respectively, reads and writes according to first in first out.
Further, each grouping has a unique sequence number; FIFO of each grouping have one with the sequence number of this grouping sequence number one to one.
The present invention is by reducing the number of equipment on the same bus to veneer grouping, increase bus, thereby the defective of original referee method when having solved large-scale transmission equipment card quantity effectively and adopting the I2C agreement to carry out communication between plates more for a long time, guaranteed that the communication between plates data are timely, reliable delivery, improved the quality of transmission, for the alternate manner that solves this defective, saved the hardware cost of equipment.
Description of drawings
Fig. 1 is the concrete enforcement block diagram of the single board communication system based on the I2C bus provided by the invention;
Fig. 2 is the flow chart of application example of the present invention.
Embodiment
Below in conjunction with drawings and Examples technical scheme of the present invention is described in detail.
Single-board communication method based on the I2C bus provided by the invention comprises:
I2C equipment all in the network element system is divided into several groupings, sets up the FIFO and the I2C bus of each grouping respectively; The I2C equipment of same grouping links to each other with the FIFO of this grouping by the I2C bus of this grouping, and the hanging equipment that is to say same grouping is on same I2C bus, and the equipment of different grouping is not on same I2C bus; When the I2C equipment in the grouping is obtained the bus right to use by arbitration in organizing, data are sent among the FIFO of this grouping, or from this grouping FIFO reading of data;
Processor carries out data interaction by the FIFO of shared incoming memory RAM at random and each grouping.
Wherein, the scheme of relatively optimizing is: the number of devices of assigning in each grouping is suitable substantially.
Wherein, the number of grouping more as much as possible, the number of I2C equipment lacks as far as possible in same group; Relatively the scheme of You Huaing is: under the total enough situations of I2C equipment, guarantee to be no less than in the grouping 4 I2C equipment as far as possible.
Wherein, the FIFO of each grouping can be divided into two sections, deposits the data that send to RAM Shared and receive from RAM Shared respectively; Also can adopt alternate manner, comprise two FIFO, deposit the data that send to RAM Shared and receive respectively from RAM Shared such as each grouping.
Wherein, can give unique sequence number of each packet allocation; For the FIFO of each grouping distribute one with the sequence number of this grouping sequence number one to one.
Wherein, processor carries out data interaction and can be meant by sharing at random the FIFO of incoming memory RAM and each grouping:
The FIFO of each grouping of poll receives data to RAM Shared from grouping FIFO successively;
Produce interrupt requests when having data to send to processor in the RAM Shared, notification processor receives; Processor is taken data away from RAM Shared, send to RAM Shared after the processing;
The data that RAM Shared is sent processor send to the FIFO of corresponding grouping.
Wherein, RAM Shared data that processor the is sent FIFO that sends to corresponding grouping can be meant:
Processor sends in the data of RAM Shared and carries purpose I2C device address; Preserve the corresponding situation of each I2C device address and grouping in the RAM Shared, determine the FIFO of the grouping of this data correspondence to send the data to this FIFO by purpose I2C device address.
Wherein, RAM Shared is divided into two sections, deposits the data that send to processor and receive from processor respectively, reads and writes according to first in first out.
Wherein, can for each grouping FIFO a priority be set according to each importance of organizing the I2C equipment arbitration; The FIFO of each grouping of poll is meant the FIFO according to each grouping of order poll of priority successively.
Single board communication system based on the I2C bus provided by the invention as shown in Figure 1, comprising:
Several groupings, RAM Shared and processor;
Each grouping comprises a plurality of I2C equipment, first-in first-out register FIFO and I2C bus; The I2C equipment of same grouping links to each other with the FIFO of this grouping by the I2C bus of this grouping; When the I2C equipment in the grouping is obtained the bus right to use by arbitration in organizing, data are sent among the FIFO of this grouping, perhaps reading of data from this grouping FIFO;
FIFO, the processor of described RAM Shared and each grouping link to each other;
Described processor is used for carrying out data interaction by the FIFO of shared incoming memory RAM at random and each grouping.
Wherein, each I2C equipment is meant a veneer that adopts the I2C agreement to communicate; Described processor refers generally to the CPU of veneer.
Wherein, the scheme of relatively optimizing is: the number of devices in each grouping is suitable substantially.
Wherein, the number of grouping more as much as possible, the number of I2C equipment lacks as far as possible in same group; Relatively the scheme of You Huaing is: under the total enough situations of I2C equipment, guarantee to be no less than in the grouping 4 I2C equipment as far as possible.
Wherein, the FIFO of each grouping can be divided into two sections, deposits the data that send to RAM Shared and receive from RAM Shared respectively; Also can adopt alternate manner, comprise two FIFO, deposit the data that send to RAM Shared and receive respectively from RAM Shared such as each grouping.
Wherein, each grouping has a unique sequence number; FIFO of each grouping have one with the sequence number of this grouping sequence number one to one.
Described processor is used for carrying out data interaction and specifically can being meant by sharing at random the FIFO of incoming memory RAM and each grouping:
Processor is the FIFO of each grouping of poll successively, receives data to RAM Shared from each grouping FIFO; And when receiving the interrupt requests of RAM Shared, from RAM Shared, take data away, send to RAM Shared after the processing;
Described RAM Shared is used for producing interrupt requests when data will send to processor, and notification processor receives; And, these data are distributed to corresponding grouping FIFO when receiving after processor sends to the data of I2C equipment.
Wherein, carry purpose I2C device address in the data that processor sends;
RAM Shared is distributed to corresponding grouping FIFO with data and is meant:
Preserve the corresponding situation of each I2C device address and grouping in the RAM Shared, determine the FIFO of the grouping of this data correspondence to send the data to this FIFO by the purpose I2C device address of carrying in the data.
Wherein, RAM Shared is divided into two sections, deposits the data that send to processor and receive from processor respectively, reads and writes according to first in first out.
Wherein, for the FIFO of each grouping a priority is set according to the importance of each group I2C equipment arbitration; The processor FIFO of each grouping of poll successively is the FIFO of finger processor according to each grouping of order poll of priority.
Further be illustrated with an application example of the present invention below.
As shown in Figure 2, be provided with 8 end I2C equipment, be equally divided into two groups, numbering is respectively 1,2,3,4 in the group.Group # is respectively first group and second group, and first group of equipment is on one group of identical bus, and second group of equipment is on the other bus, and two groups of buses are separate.
Set up 2 grouping FIFO: grouping FIFO 1 and grouping FIFO 2, corresponding first group and second group respectively, the priority arbitration of establishing second group of I2C equipment is higher than first group of I2C equipment.Allocation packets FIFO
2 priority is 1,1 to represent limit priority, and the priority of grouping FIFO 1 is 2.
To grouping FIFO 1, when the I2C equipment in first group 3 is arbitrated in by group, when obtaining the bus right to use, just can and 1 of FIFO carry out the reception or the transmission of data.
The priority of grouping FIFO 2 is higher than grouping FIFO 1, and when all having data to handle among grouping FIFO 1 and the grouping FIFO 2, the data that first poll is taken away among the FIFO 2 are put into RAM Shared, and then get the data among the FIFO 1.Perhaps the data in the RAM Shared send to FIFO 2 earlier, and then send to FIFO 1.If RAM Shared reads and writes according to the mode of first in first out, according to processor the order that data write RAM Shared is sent when then sending data to FIFO, rather than send according to priority.
Have two data to receive in the RAM Shared, by the interrupt notification processor, the data that processor takes out in the RAM Shared are in order handled, and result is sent to respectively in the RAM Shared, send to the FIFO that respectively divides into groups again by RAM Shared and handle.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of claim of the present invention.
Claims (12)
1, a kind of single-board communication method based on internal integrated circuit I2C bus comprises:
I2C equipment is divided into several groupings, sets up the first-in first-out register FIFO and the I2C bus of each grouping respectively; The I2C equipment of same grouping links to each other with the FIFO of this grouping by the I2C bus of this grouping; When the I2C equipment in the grouping is obtained the bus right to use by arbitration in organizing, data are sent among the FIFO of this grouping, or from this grouping FIFO reading of data;
Processor carries out data interaction by the FIFO of shared incoming memory RAM at random and each grouping.
2, the method for claim 1 is characterized in that, the FIFO of processor by RAM and each grouping carries out data interaction and be meant:
The FIFO of each grouping of poll receives data to RAM Shared from grouping FIFO successively;
Produce interrupt requests when having data to send to processor in the RAM Shared, notification processor receives; Processor is taken data away from RAM Shared, send to RAM Shared after the processing;
The data that RAM Shared is sent processor send to the FIFO of corresponding grouping.
3, method as claimed in claim 2 is characterized in that, the FIFO that the data that RAM Shared is sent processor send to corresponding grouping is meant:
Processor sends in the data of RAM Shared and carries purpose I2C device address;
Preserve the corresponding situation of each I2C device address and grouping in the RAM Shared, determine the FIFO of the grouping of this data correspondence to send the data to this FIFO by purpose I2C device address.
4, method as claimed in claim 2 is characterized in that, also comprises:
For the FIFO of each grouping a priority is set according to the importance of each group I2C equipment arbitration;
The FIFO of each grouping of poll is meant successively: according to each FIFO that divides into groups of order poll of priority.
5, method according to any one of claims 1 to 4 is characterized in that:
The FIFO of each grouping is divided into two sections, deposits the data that send to RAM Shared and receive from RAM Shared respectively;
RAM Shared is divided into two sections, deposits the data that send to processor and receive from processor respectively, reads and writes according to first in first out.
6, method according to any one of claims 1 to 4 is characterized in that, also comprises:
Be unique sequence number of each packet allocation; For the FIFO of each grouping distribute one with the sequence number of this grouping sequence number one to one.
7, a kind of single board communication system based on the I2C bus comprises processor, it is characterized in that, also comprises:
Several groupings, RAM Shared and processor;
Each grouping comprises a plurality of I2C equipment, first-in first-out register FIFO and I2C bus; The I2C equipment of same grouping links to each other with the FIFO of this grouping by the I2C bus of this grouping; When the I2C equipment in the grouping is obtained the bus right to use by arbitration in organizing, data are sent among the FIFO of this grouping, perhaps reading of data from this grouping FIFO;
FIFO, the processor of described RAM Shared and each grouping link to each other;
Described processor is used for carrying out data interaction by the FIFO of RAM and each grouping.
8, system as claimed in claim 7 is characterized in that, the FIFO of processor by RAM and each grouping carries out data interaction and specifically be meant:
Processor is the FIFO of each grouping of poll successively, receives data to RAM Shared from each grouping FIFO; And when receiving the interrupt requests of RAM Shared, from RAM Shared, take data away, send to RAM Shared after the processing;
Described RAM Shared is used for producing interrupt requests when data will send to processor, and notification processor receives; And, these data are distributed to corresponding grouping FIFO when receiving after processor sends to the data of I2C equipment.
9, system as claimed in claim 8 is characterized in that:
Carry purpose I2C device address in the data that processor sends;
RAM Shared is distributed to corresponding grouping FIFO with data and is meant:
Preserve the corresponding situation of each I2C device address and grouping in the RAM Shared, determine the FIFO of the grouping of this data correspondence to send the data to this FIFO by the purpose I2C device address of carrying in the data.
10, as each described system in the claim 8, it is characterized in that:
For the FIFO of each grouping is provided with a priority;
The processor FIFO of each grouping of poll successively is meant: processor is according to the FIFO of each grouping of order poll of priority.
11, as each described system in the claim 8 to 10, it is characterized in that:
The FIFO of each grouping is divided into two sections, deposits the data that send to RAM Shared and receive from RAM Shared respectively;
RAM Shared is divided into two sections, deposits the data that send to processor and receive from processor respectively, reads and writes according to first in first out.
12, as each described system in the claim 8 to 10, it is characterized in that:
Each grouping has a unique sequence number; FIFO of each grouping have one with the sequence number of this grouping sequence number one to one.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008101330906A CN101309257A (en) | 2008-07-08 | 2008-07-08 | Single board communication method and system based on internal integrated circuit bus |
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2008101330906A CN101309257A (en) | 2008-07-08 | 2008-07-08 | Single board communication method and system based on internal integrated circuit bus |
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| CNA2008101330906A Pending CN101309257A (en) | 2008-07-08 | 2008-07-08 | Single board communication method and system based on internal integrated circuit bus |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012097569A1 (en) * | 2011-01-21 | 2012-07-26 | 中兴通讯股份有限公司 | Method and apparatus for accessing i2c device |
| CN105975412A (en) * | 2016-05-13 | 2016-09-28 | Tcl移动通信科技（宁波）有限公司 | IIC bus-based equipment priority control method, device and system |
| CN106375239A (en) * | 2016-08-25 | 2017-02-01 | 北京智芯微电子科技有限公司 | Method and device for processing network data reception |
| CN106506069A (en) * | 2012-07-02 | 2017-03-15 | 华为技术有限公司 | Optical line terminal, optical transceiver module, system and optical fiber detecting method |
| CN107026801A (en) * | 2017-04-12 | 2017-08-08 | 国网黑龙江省电力有限公司信息通信公司 | Data transmission system and method |
-
2008
- 2008-07-08 CN CNA2008101330906A patent/CN101309257A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012097569A1 (en) * | 2011-01-21 | 2012-07-26 | 中兴通讯股份有限公司 | Method and apparatus for accessing i2c device |
| CN106506069A (en) * | 2012-07-02 | 2017-03-15 | 华为技术有限公司 | Optical line terminal, optical transceiver module, system and optical fiber detecting method |
| CN106506069B (en) * | 2012-07-02 | 2019-12-17 | 华为技术有限公司 | optical line terminal, optical transceiver module, system and optical fiber detection method |
| CN105975412A (en) * | 2016-05-13 | 2016-09-28 | Tcl移动通信科技（宁波）有限公司 | IIC bus-based equipment priority control method, device and system |
| CN106375239A (en) * | 2016-08-25 | 2017-02-01 | 北京智芯微电子科技有限公司 | Method and device for processing network data reception |
| CN106375239B (en) * | 2016-08-25 | 2019-02-12 | 北京智芯微电子科技有限公司 | A method and device for processing network data reception |
| CN107026801A (en) * | 2017-04-12 | 2017-08-08 | 国网黑龙江省电力有限公司信息通信公司 | Data transmission system and method |
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Open date: 20081119 |