CN104598430B - Network interface interconnection design and control system of CPU interconnection expansion system - Google Patents

Abstract

The invention particularly relates to a network interface interconnection design and control system of a CPU interconnection expansion system. The network interface interconnection design and control system of the CPU interconnection expansion system is interconnected through the network interface on each board to realize the interaction of internal protocol messages between multiple CPU interconnection expansion systems, and will be processed by the CACHE consistency processing module The final message is encapsulated into a network link layer message and sent to the link. At the same time, the message received from the network link is converted into an internal message format and sent to the CACHE consistency processing module. The network interface interconnection design and control system of the CPU interconnection expansion system makes full use of the channel capacity of the transmission media, reduces the required transmission channels and the number of device pins, and not only realizes internal protocol reporting between multiple CPU interconnection expansion systems. The interaction of documents also greatly reduces the communication cost.

Description

A network interface interconnection design and control system of a CPU interconnection expansion system

technical field

The invention relates to the technical fields of communication technology and CPU CACHE interconnection processing, in particular to a network interface interconnection design and control system of a CPU interconnection expansion system.

Background technique

As a node of the network, the server stores and processes 80% of the data and information on the network, so it is also called the soul of the network. To make an image metaphor: the server is like a switch in a post office, and fixed or mobile network terminals such as computers, notebooks, PDAs, and mobile phones are like telephones scattered in homes, various offices, and public places. Telephone communication and communication in daily life and work must go through the switchboard to reach the target phone. In the same way, network terminal devices such as microcomputers in households and enterprises access the Internet, obtain information, communicate with the outside world, entertain, etc., must also go through the server, so it can also be said that the server "organizes" and "leads" these devices. It is a high-performance computer that provides various services for client computers on the network. Under the control of the network operating system, it provides the hard disk, tape, printer, Modem and various special communication equipment connected to it to the network. It can also provide network users with services such as centralized computing, information publishing and data management. Its high performance is mainly reflected in high-speed computing capabilities, long-term reliable operation, and powerful external data throughput capabilities.

As the main frequency of the CPU is getting higher and higher, the speed of the CPU's external interfaces QPI, KTI, etc. has reached 6.4G to 10G or higher. However, the number of external interfaces output by a single CPU is very small, and it is not suitable for large-scale CPU integration to form a large CPU cluster. The traditional parallel interface technology has become a bottleneck for further improving the data transmission rate. It is replacing the traditional parallel bus and becoming the mainstream of high-speed interface technology.

Contents of the invention

In order to make up for the defects of the prior art, the present invention provides a simple and efficient network interface interconnection design and control system of a CPU interconnection expansion system.

The present invention is achieved through the following technical solutions:

A network interface interconnection design and control system of a CPU interconnection expansion system, characterized in that: according to the division of network levels, the CPU interconnection expansion system is divided into four levels from top to bottom through the network interfaces on the respective boards, which are respectively application layer, protocol layer, link layer and physical layer; the application layer, after classifying and processing the sent and received messages of the CACHE consistency processing module and the CACHE non-consistency processing module, is handed over to the protocol layer for processing; the protocol layer includes N A routing table module and a sending request arbiter module fill or remove routing field information for messages sent and received by the application layer; the link layer sets M different virtual channels according to the internal messages having M different message types, At the same time, the mapping of M virtual channels to T high-speed serdes is completed; the physical layer is used to realize the initialization and basic coding operation of the serdes. M, N, T are all natural numbers.

The application layer specifically includes a CACHE consistent message submission module, a CACHE non-consistent message submission module, an application layer credit processing module, an error checking module, a CACHE consistent message sending module, a CACHE non-consistent message sending module and Message packet encapsulation module;

The CACHE consistent message submission module: store the CACHE consistent message from the protocol layer after being processed by the application layer credit processing module and the error checking module into a FIFO with a depth of 128 and a width of 256, according to Submission and processing of requirements processed by the CACHE consistency processing module;

The CACHE inconsistent message submission module: store the CACHE inconsistent message from the protocol layer processed by the application layer credit processing module and the error checking module into a FIFO with a depth of 128 and a width of 128 , submit and process according to the requirements processed by the CACHE consistency processing module;

The application layer credit processing module: the network message received from the protocol layer is distinguished as a CACHE consistent message, a CACHE non-consistent message or a fault-tolerant instruction message according to the information in the message header, and submits them respectively To the CACHE consistent message submission module, the CACHE non-consistent message submission module and the error checking module;

The CACHE consistency message sending module: receives the CACHE consistency message output by the CACHE consistency processing module, and stores the CACHE consistency message in a FIFO with a depth of 128 and a width of 256, according to the message The requirement submission and processing of the encapsulation module;

The CACHE inconsistent message sending module: receives the CACHE inconsistent message output by the CACHE consistent processing module, and stores the CACHE inconsistent message into a FIFO with a depth of 128 and a width of 128, according to the Describe the requirement submission and processing of the message encapsulation module;

The message packet encapsulation module encapsulates different message header information according to different message types.

The message types include 6 categories, wherein the HOME message includes a request message and a monitoring response message, an SNP message represents a monitoring message, an NDR message represents a request, a response, a read and write operation completion message, and a DRS message文 means carrying data message, NCB means writing message without data, and NCS means reading message without data;

The message header encapsulation information of the message message type is a 128-bit register respectively, and its lower 6 bits, namely: 6'b000001 represents the HOME message, 6'b000010 represents the SNP message, and 6'b000100 represents the NDR message, 6'b001000 represents the DRS message, 6'b010000 represents the NCB message, and 6'b100000 represents the NCS message. The message header information and the network header information are combined to form the complete message header information.

The network message header information received by the application layer credit processing module from the protocol layer is a 128-bit wide register, and its lower 3 bits are respectively 3'b001 representing a CACHE consistency message and 3'b010 representing a CACHE non-consistency Message, 3'b100 represents fault-tolerant instruction message;

The error checking module: if the signal submitted by the application layer credit processing module is received, the error checking module directly submits the error information, and modifies the 4 to 6 bits of the 128-bit network message header information to 3'b111, At the same time, the packet encapsulation format is added and passed to the protocol layer for processing.

The protocol layer specifically includes a routing table access control logic module and a sending request arbiter module;

The routing table access control logic module: put the routing lookup result into the 8 to 64-bit area of the message header, which needs to be loaded and returned to the remote link when organizing the message message, and at the same time, the message sent to itself Perform error handling, drop packets if necessary, and handle link waiting timeout;

The sending request arbiter module is composed of a group of state machines, and according to the routing information obtained by the routing table access control logic module and the message message type and the error information delivered by the error checking module, the mapping of the arbitration message flow to the T-way high-speed serdes is scheduled one of them.

The mapping of the T high-speed serdes each has a link layer, and the link layer specifically includes a virtual channel division and message storage module, and a virtual channel sending request arbiter.

The virtual channel division and message storage module: establish T virtual channels according to the mapping of T high-speed serdes, and simultaneously use the message header information, CACHE consistent message information and CACHE non-consistent message information according to the T high-speed serdes The mapping is packaged into the respective virtual channel stations, and the enable signal is sent to the virtual channel sending request arbiter;

The virtual channel transmission request arbiter: according to the virtual channel division and the enable signal provided by the message storage module, cyclically forwards the mapping of T high-speed serdes.

The physical layer is a physical coding sublayer with high bandwidth, low delay, high reliability and high flexibility, which is used to transmit the data of the link layer to the receiving end through up to T high-speed serdes, and perform data alignment And recombination, the link layer specifically includes derdes reset processing module, serdes polarity, synchronization alignment and recombination processing module, crc processing module plus descrambling processing module;

The serdes reset processing module: generates a global reset to control the reset of the entire network interface. In addition, according to the out-of-synchronization signal generated by the serdes polarity, synchronous alignment and recombination processing module, the serdes self-reset signal is generated to control the serdes to restart;

Said serdes polarity, synchronous alignment and recombination processing module: judging the positive and negative polarity of serdes, and reorganizing valid data packets according to the alignment of the synchronous header;

The crc processing module: perform a 32-bit CRC check on the data message to determine the correctness of the transmission of the link;

The scrambling and descrambling processing module: generates a scrambling and descrambling algorithm program according to the 64/66 encoding and decoding principle, and scrambles and descrambles the data message.

The beneficial effects of the present invention are: the network interface interconnection design and control system of the CPU interconnection expansion system fully utilizes the channel capacity of the transmission medium, reduces the required transmission channels and the number of device pins, and not only realizes the interconnection of multiple CPUs The interaction of internal protocol messages between extended systems also greatly reduces communication costs.

Description of drawings

Accompanying drawing 1 is a schematic diagram of the structure of the protocol layer, the link layer and the physical layer in the logical hierarchical structure of the invention.

Figure 2 is a schematic diagram of the application layer structure in the logic hierarchy of the invention.

detailed description

The present invention will be described in detail below in conjunction with the accompanying drawings.

The network interface interconnection design and control system of the CPU interconnection expansion system is divided according to the network level, and the CPU interconnection expansion system is divided into four levels from top to bottom through the network interface on each board, which are application layer, protocol layer, Link layer and physical layer; Described application layer, hand over to protocol layer after classifying and processing to CACHE consistency processing module, CACHE inconsistency processing module sending and receiving message; Described protocol layer has included N routing table modules, The sending request arbiter module fills or removes the routing field information for the messages sent and received by the application layer; the link layer sets M different virtual channels according to the M different message types of the internal messages, and completes M virtual channels at the same time. Mapping of channels to T-channel high-speed serdes; the physical layer is used to implement initialization of serdes and basic coding operations.

The application layer specifically includes a CACHE consistent message submission module, a CACHE non-consistent message submission module, an application layer credit processing module, an error checking module, a CACHE consistent message sending module, a CACHE non-consistent message sending module and Message packet encapsulation module;

The CACHE consistent message submission module: store the CACHE consistent message from the protocol layer after being processed by the application layer credit processing module and the error checking module into a FIFO with a depth of 128 and a width of 256, according to Submission and processing of requirements processed by the CACHE consistency processing module;

The CACHE inconsistent message submission module: store the CACHE inconsistent message from the protocol layer processed by the application layer credit processing module and the error checking module into a FIFO with a depth of 128 and a width of 128 , submit and process according to the requirements processed by the CACHE consistency processing module;

The application layer credit processing module: the network message received from the protocol layer is distinguished as a CACHE consistent message, a CACHE non-consistent message or a fault-tolerant instruction message according to the information in the message header, and submits them respectively To the CACHE consistent message submission module, the CACHE non-consistent message submission module and the error checking module;

The CACHE consistency message sending module: receives the CACHE consistency message output by the CACHE consistency processing module, and stores the CACHE consistency message in a FIFO with a depth of 128 and a width of 256, according to the message The requirement submission and processing of the encapsulation module;

The CACHE inconsistent message sending module: receives the CACHE inconsistent message output by the CACHE consistent processing module, and stores the CACHE inconsistent message into a FIFO with a depth of 128 and a width of 128, according to the Describe the requirement submission and processing of the message encapsulation module;

The message packet encapsulation module encapsulates different message header information according to different message types.

The message types include 6 categories, wherein the HOME message includes a request message and a monitoring response message, an SNP message represents a monitoring message, an NDR message represents a request, a response, a read and write operation completion message, and a DRS message文 means carrying data message, NCB means writing message without data, and NCS means reading message without data;

The message header encapsulation information of the message message type is a 128-bit register respectively, and its lower 6 bits, namely: 6'b000001 represents the HOME message, 6'b000010 represents the SNP message, and 6'b000100 represents the NDR message, 6'b001000 represents the DRS message, 6'b010000 represents the NCB message, and 6'b100000 represents the NCS message. The message header information and the network header information are combined to form the complete message header information.

The network message header information received by the application layer credit processing module from the protocol layer is a 128-bit wide register, and its lower 3 bits are respectively 3'b001 representing a CACHE consistency message and 3'b010 representing a CACHE non-consistency Message, 3'b100 represents fault-tolerant instruction message;

The error checking module: if the signal submitted by the application layer credit processing module is received, the error checking module directly submits the error information, and modifies the 4 to 6 bits of the 128-bit network message header information to 3'b111, At the same time, the packet encapsulation format is added and passed to the protocol layer for processing.

The protocol layer specifically includes a routing table access control logic module and a sending request arbiter module;

The routing table access control logic module: put the routing lookup result into the 8 to 64-bit area of the message header, which needs to be loaded and returned to the remote link when organizing the message message, and at the same time, the message sent to itself Perform error handling, drop packets if necessary, and handle link waiting timeout;

The sending request arbiter module is composed of a group of state machines, and according to the routing information obtained by the routing table access control logic module and the message message type and the error information delivered by the error checking module, the mapping of the arbitration message flow to the T-way high-speed serdes is scheduled one of them.

The mapping of the T high-speed serdes each has a link layer, and the link layer specifically includes a virtual channel division and message storage module, and a virtual channel sending request arbiter.

The virtual channel division and message storage module: establish T virtual channels according to the mapping of T high-speed serdes, and simultaneously use the message header information, CACHE consistent message information and CACHE non-consistent message information according to the T high-speed serdes The mapping is packaged into the respective virtual channel stations, and the enable signal is sent to the virtual channel sending request arbiter;

The virtual channel transmission request arbiter: according to the virtual channel division and the enable signal provided by the message storage module, cyclically forwards the mapping of T high-speed serdes.

The physical layer is a physical coding sublayer with high bandwidth, low delay, high reliability and high flexibility, which is used to transmit the data of the link layer to the receiving end through up to T high-speed serdes, and perform data alignment And recombination, the link layer specifically includes derdes reset processing module, serdes polarity, synchronization alignment and recombination processing module, crc processing module plus descrambling processing module;

The serdes reset processing module: generates a global reset to control the reset of the entire network interface. In addition, according to the out-of-synchronization signal generated by the serdes polarity, synchronous alignment and recombination processing module, the serdes self-reset signal is generated to control the serdes to restart;

Said serdes polarity, synchronous alignment and recombination processing module: judging the positive and negative polarity of serdes, and reorganizing valid data packets according to the alignment of the synchronous header;

The crc processing module: perform a 32-bit CRC check on the data message to determine the correctness of the transmission of the link;

The scrambling and descrambling processing module: generates a scrambling and descrambling algorithm program according to the 64/66 encoding and decoding principle, and scrambles and descrambles the data message.

The following are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

The network interface device of the CPU interconnection expansion system includes a receiving device and a sending device. The two devices realize full-duplex communication and support ring, star, and chain connections.

As shown in Figure 1 and Figure 2, the message sending process of the network interface device of the CPU interconnection expansion system is as follows: as shown in the application layer, according to the data_valid signal in the 105CACHE consistent message sending module from the CACHE processing module Received 236-bit FLIT, because the data cache interface in 105 is 256-bit, the bits above the 236-bit data received are filled with 0 to maintain the consistency of the data path. According to the received FLIT type, that is: the message type described in Claim 3, input the message type into the register (last_flit_type[5:0]), and at the same time enter the current FLIT type (H/T) into the current FLIT In the type register (current_flit_type[127:0][5:0]), the reason why the register group is selected is to ensure that the message can run correctly when there may be a mismatch between the transmission speed and the processing speed. When the rising edge of each clock and the data_valid signal is valid, move the furthest effective insulation type attribute in current_flit_type to last_flit_type, and send the current FLIT type H/T signal into current_flit_type for registration.

According to the attribute of current_flit_type, the content of the message is stored in the relevant message register group. For example, the attribute of current_flit_type is b000001, which is the home type message. The register group of the message content is home_data_reg[31:0][229:0 ], the register set removes the 6bit message type attribute. The reason why the register group is selected is to ensure that the message can run correctly when there may be a mismatch between the transmission speed and the processing speed. Taking the above process as an example, define snp_data_reg[31:0][229:0], ndr_data_reg[31:0][229:0], drs_data_reg[31:0][229:0], ncb_data_reg[31:0] respectively [229:0], ncs_data_reg[31:0][229:0].

On each rising edge of the clock, if there is a valid attribute in last_flit_type, the valid FLIT message is sent to the 201 routing table access control logic module shown in FIG. 1 .

106 The data_valid signal in the CACHE non-consistent message sending module receives 115-bit FLIT from the reception of the CACHE processing module, because the data cache interface in 101 is 128 bits, and the bits above the 115-bit data received are filled with 0, so Maintain data path consistency. According to the received FLIT type, input the message type into the register (last_flit_type[5:0]), and at the same time enter the current FLIT type (H/T) into the current FLIT type register (current_flit_type[127:0][5: 0]), the reason why the register group is selected is to ensure that the message can run correctly when there may be a mismatch between the transmission speed and the processing speed. When the rising edge of each clock and the data_valid signal is valid, move the furthest effective insulation type attribute in current_flit_type to last_flit_type, and send the current FLIT type H/T signal into current_flit_type for registration.

According to the attribute of current_flit_type, the content of the message is stored in the relevant message register group. For example, the attribute of current_flit_type is b000001, which is the home type message. The register group of the message content is home_data_reg[31:0][108:0 ], the register set removes the 6bit message type attribute. The reason why the register group is selected is to ensure that the message can run correctly when there may be a mismatch between the transmission speed and the processing speed. Taking the above process as an example, define snp_data_reg[31:0][108:0], ndr_data_reg[31:0][108:0], drs_data_reg[31:0][108:0], ncb_data_reg[31:0] respectively [108:0], ncs_data_reg[31:0][108:0].

On each rising edge of the clock, if there is a valid attribute in last_flit_type, the valid FLIT message is sent to the 201 routing table access control logic module shown in FIG. 1 .

In 201 according to flit_type==last_flit_type and snp_data_c[229:0], ndr_data_c[229:0], drs_data_c[229:0], ncb_data_c[229:0], ncs_data_c[229:0], home_data_c[229:0] , these six registers represent the CACHE consistency message respectively; 108:0], these six registers represent CACHE inconsistency messages; they respectively correspond to the output values when the corresponding register group last_flit_type described in the previous paragraph is valid. At the same time, in 201, the home_data_c[229:0] and home_data_nc[108:0] messages are used as an example to introduce the routing generation process, and the expression forms of other messages are consistent with it.

Taking the system memory as 256G and taking the board with T=7 network interfaces as an example, we need to pay special attention to the fact that the memory capacity and network interfaces in our actual work must be much larger than this number. The allocation formula of the network interface: (memory capacity physical address/T+1), that is, the memory is divided into T+1 shares, and each share corresponds to the corresponding network interface. For example, the physical address of 256G is 2^38, which corresponds to home_data_c[229:166] and home_data_nc[108:45], and the address space of 0-(32G-1) of the register is allocated to the network interface of T=0; 32G The address space of -(64G-1) is allocated to the network interface of T=1; the address space up to 224G-(256G-1) is allocated to the network interface of T=7. Based on the above, we know that the address space of home_data_c[229:166] and home_data_nc[108:45] whose address is 0-(32G-1) should be handled by 203 and 204 of T=0 as shown in Figure 1.

In 203 and 204, the FLIT message is stored in the corresponding virtual channel according to the attribute of last_flit_type, and the message is sent to the 107 message encapsulation module for encapsulation and submitted to TX serial output through 205.

As shown in Figure 1 and Figure 2, the message receiving process of the network interface device of the CPU interconnection expansion system is as follows: Obtain the message header, tail, message data and valid signals from the 205 physical layer ports, and follow the message The text type is stored in data RAM in blocks, the depth of data RAM is 128, and the width is 256 (including 1 head flag and 1 tail flag). After receiving the rd_en or rd_done signal of the 201 routing table access control logic module, the data is taken out from the corresponding address of the corresponding message message type storage block, and each time a data is read, the corresponding free signal is sent to as shown in Figure 2 102 An application layer processing module. As long as the message counter is not 0, the avail signal of the output data can be set, and each time an rd_done signal is received, the avail signal is forced to be disabled for one beat. When the message counter is 0, for other cases, it is directly read from RAM.

As shown in FIG. 2 103, the error detection module processes error information from 205 physical layer as shown in FIG. 1, and returns the err_reset (error) signal and flit_type of the error data packet to an arbitration result to the link layer. At the same time, it is sent to the 102 application layer processing module. When receiving an err_reset (error) signal and flit_type from the application layer, if a part of the data body of a message is being sent, then continue to send, when the last FLIT of the message is sent. , the err_reset signal is set, and the error processing of the message sent to itself is processed at the physical layer by judging the information such as the destination node number, and notifying the remote receiving device to implement remedial measures. When the virtual channel in the link layer 203 and 204 shown in FIG. 1 is unavailable or the err_reset signal is received, the counter starts counting, and when the virtual channel becomes valid again or the err_reset signal becomes low, the counter is cleared. If the counter exceeds a certain threshold (the threshold is input by an external signal) or the err_reset signal is received at this time, it starts to enter the packet loss state. if:

1) The virtual channel is available again, and no packets are actually lost in the packet loss state, and the err_reset signal is not high;

2) A complete message has been lost. At this time, the virtual channel is available again, and the err_reset signal is not high;

3) The timeout counter is less than the threshold value (indicating that packet loss processing is performed when rework is received, and only one packet is lost), and in the packet loss state, no packet is actually lost or a complete packet has been lost, then the packet loss state End. In the state of packet loss, there is only one difference between the message processing process and the normal state, that is, the sending valid signal is not set.

As shown in Figure 2, the 102 credit processing module directly reads the message information from the RAM according to the above processing and stores it in flit_data_reg[255:0], and according to the flit_type type and FLIT message header corresponding to flit_data_reg[235:230] The lower 3 bits of the 128-bit message, that is, flit_data_reg[131:128], distinguishes whether the message is a CACHE non-consistent message or a CACHE consistent message, and stores them in the relevant RAM respectively. When the 102 application layer processing module receives the rd_en or rd_done signal of the 101 or 104 module as shown in Figure 2, the data is taken out from the corresponding address of the corresponding message message type storage block, and the corresponding data is sent every time a data is read out. The free signal is sent to module 101 or 104 shown in Fig. 2 . As long as the message counter of each (CACHE non-consistent message or CACHE consistent message) is not 0, the avail signal of the output data can be set, and each time an rd_done signal is received, the avail signal is forced to fail for one beat. When the message counter is 0, for other cases, it is directly read from RAM.

Taking the system memory as 256G and taking the board with T=7 network interfaces as an example, we need to pay special attention to the fact that the memory capacity and network interfaces in our actual work must be much larger than this number. The allocation formula of the network interface: (memory capacity physical address/T+1), that is, the memory is divided into T+1 shares, and each share corresponds to the corresponding network interface. For example, the physical address of 256G is 2^38, and its corresponding attributes of flit_data_reg [229:166], flit_data_reg [235:230] and flit_data_reg[131:128] are used to determine which network interface the message comes from and what type of message it is. arts. The CACHE inconsistent message is submitted to the 104 module for processing; the CACHE consistent message is submitted to the 104 module for processing.

Claims (6)

1. the network interface Networking Design and control system of a kind of CPU interconnections extension system, it is characterised in that：According to network layer Divide, CPU is interconnected into extension system by being divided into 4 levels from top to bottom with network interface on respective plate, respectively applied Layer, protocol layer, link layer and physical layer；The application layer, mould is handled to CACHE consistency treatments module, CACHE nonuniformities Block transmitting-receiving message transfers to protocol layer to handle after carrying out classification processing；The protocol layer contains N number of router table means, sends request Route field information is filled or rejected to arbitrator module, the message that application layer is received and dispatched；The link layer, has M according to built-in message Individual different type of message sets M different virtual channels, while completing M virtual channel to T roads high speed serdes mapping；Institute Physical layer is stated, initialization and basic coding operation for realizing serdes；

The application layer specifically includes CACHE uniformity message and submits module, CACHE nonuniformities message to submit module, application Layer credit processing module, error check module, CACHE uniformity messages sending module, CACHE nonuniformity message sending modules With message packet package module；

The CACHE uniformity message submits module：By after application layer credit processing module, error check module processing CACHE uniformity packet storage from the protocol layer is in the FIFO that 128, width is 256 to a depth, according to The demand of CACHE consistency treatment resume modules is submitted and processing；

The CACHE nonuniformities message submits module：Will be after application layer credit processing module, error check module processing The CACHE nonuniformities packet storage from the protocol layer be in the FIFO that 128, width is 128 to a depth, according to The demand of CACHE consistency treatment resume modules is submitted and processing；

The application layer credit processing module：The network message received from protocol layer is to distinguish according to information in its heading CACHE uniformity message, CACHE nonuniformities message or fault-tolerant instruction message, and it is submitted to the CACHE mono- respectively Cause property message submits module, the CACHE nonuniformities message to submit module and the error check module；

The CACHE uniformity message sending module：The CACHE uniformity messages of CACHE consistency treatments module output are received, And be in the FIFO that 128, width is 256, according to the message package module by CACHE uniformity packet storage a to depth Demand submit handled with it；

The CACHE nonuniformities message sending module：Receive the CACHE nonuniformities of CACHE consistency treatments module output Message, and be in the FIFO that 128, width is 128, according to the message by CACHE nonuniformities packet storage a to depth The demand of package module is submitted and handled with it；

The message packet package module, different message headers are encapsulated into according to the difference of type of message.

2. the network interface Networking Design and control system of CPU interconnections extension system according to claim 1, its feature exist In：The type of message includes 6 six major classes, and wherein HOME messages include request message and monitor response message, the representative of SNP messages Monitor message, NDR messages and represent request, response, read-write operation completion message, DRS messages representative carrying data message, NCB generations Table writes the text of reading the newspaper of message, NCS without data without data；

The heading packaging information of the message type is respectively the register of 128, and its is low 6, i.e.,：6’b000001 HOME messages are represented, 6 ' b000010 represent SNP messages, and 6 ' b000100 represent NDR messages, and 6 ' b001000 represent DRS messages, 6 ' b010000 represent NCB messages, and 6 ' b100000 represent NCS messages, and this message packet header and network message header are closed And whole message header is constituted together.

3. the network interface Networking Design and control system of CPU interconnections extension system according to claim 1 or 2, it is special Levy and be：The network message header that the application layer credit processing module is received from protocol layer is the deposit of 128 bit widths Device, its is low 3, is that 3 ' b001 represent CACHE uniformity message, 3 ' b010 and represent CACHE nonuniformities message, 3 ' b100 respectively Represent fault-tolerant instruction message；

The error check module：If receiving the signal that the application layer credit processing module is submitted, the error checking mould The direct submittal error information of block, and it is 3 ' b111 to change 4 to 6 of network message header of 128, while adding message envelope Dress form passes to protocol layer processing.

4. the network interface Networking Design and control system of CPU interconnections extension system according to claim 1, its feature exist In：The protocol layer specifically includes routing table access control logic module and sends request arbitrator module；

The routing table access control logic module：By route searching result be put into message packet head 8 to 64 regions, it is necessary to Distal end link is returned in the when carrying of organizing messages message, while carrying out error handle, necessity to being sent to the message of itself When packet loss, processing link wait time-out；

The request arbitrator module that sends is made up of a group state machine, the road obtained according to routing table access control logic module The error message transmitted by information and message type and error check module flows to T roads at a high speed come scheduling arbitration message One of serdes mapping.

5. the network interface Networking Design and control system of CPU interconnections extension system according to claim 1, its feature exist In：The mapping of the T roads high speed serdes each possesses a link layer, the link layer specifically include pseudo channel divide and Message storage module, pseudo channel sends request moderator；

The pseudo channel is divided and message storage module：T virtual channel is set up according to T roads high speed serdes mapping, simultaneously By message header, CACHE uniformity message information and CACHE nonuniformities message information reflecting according to T roads high speed serdes Penetrate and be bundled in respective virtual channel station, and signal will be enabled and be sent to pseudo channel transmission request moderator；

The pseudo channel sends request moderator：The enable signal provided according to pseudo channel division and message storage module, Mapping to T roads high speed serdes circulates forwarding.

6. the network interface Networking Design and control system of CPU interconnections extension system according to claim 1, its feature exist In：The physical layer, which is one, has high bandwidth, low latency, the Physical Coding Sublayer of highly reliable and high flexible feature, for inciting somebody to action The data of link layer, travel to receiving terminal, and carry out the alignment and restructuring of data, link layer by most T roads high speed serdes Derdes reset processings module, serdes polarity, synchronous alignment and reorganization module are specifically included, crc processing modules add solution Disturb processing module；

Institute serdes reset processing modules：Global reset is produced, to control whole network interface to reset；According further to described The of-step signal that serdes polarity, synchronous alignment and reorganization module are produced produces serdes Self-resetting signals, control Serdes restarts；

The serdes polarity, synchronous alignment and reorganization module：Serdes positive-negative polarities are judged, according to pair of synchronous head It is neat to recombinate effective data packets；

The crc processing modules：32bit CRC check is done to data message, to judge that the transmission correctness of link is verified；

The Reinforced turf processing module：Reinforced turf algorithm routine is produced according to 64/66 encoding and decoding principle, data message is scrambled, Descrambling.