CN101308642B - Flat panel display device with narrow-edge driving structure and driving method thereof - Google Patents

Abstract

The invention provides a flat panel display device with a narrow-edge driving framework and a driving method thereof. The display area is used for displaying images. The ASIC is used for outputting P data voltage signals. A first data shift register and multiple first switch units arranged at the second side of the display region for generating a first control signal, and sequentially outputting signals from 1 st to the second when the first switch units receive the first control signalA data voltage signal. A second data shift register and multiple second switch units arranged at the third side of the display region for generating a second control signal, and sequentially outputting a first control signal and a second control signal when the second switch units receive the first control signal

And a P-th data voltage signal.

Description

Flat panel display device with narrow-edge driving structure and driving method thereof

technical field

The invention relates to an analog buffer circuit, in particular to an ability to compensate component variation produced by an analog buffer circuit manufactured by a low-temperature polysilicon process.

Background technique

Display devices with advanced functions have gradually become an important feature of today's consumer electronics products. Liquid crystal display devices have gradually been used in various electronic devices such as televisions, mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or notebook computer screens. widely used. Low Temperature Poly-Silicon (LTPS) liquid crystal display devices are currently the mainstream of consumer product development, and are mainly used in highly integrated and high-quality display devices.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a liquid crystal display device 10 in the prior art. The liquid crystal display device 10 includes a substrate 12 , an application-specific integrated circuit (ASIC) 14 , a source driver 16 , a gate driver 18 , a printed circuit board 22 and a liquid crystal display area 20 . The source driver 16 , the gate driver 18 and the liquid crystal display area 20 are all disposed on the substrate 12 , and the ASIC 14 is disposed on the printed circuit board 22 . The display area 20 with m×n pixels is coupled to the gate driver 18 and the source driver through m gate lines (scan lines) GL ₁ -GL _m and n data lines (data lines) DL ₁ -DL _n respectively 16.

Please refer to FIG. 1 and FIG. 2 together. FIG. 2 is a timing diagram of data voltage signals of the shift register unit and the ASIC 14 in the source driver 16 of FIG. 1 . When the scanning signal generated by the gate driver 18 is transmitted to the liquid crystal display area 20 through the gate lines GL ₁ -GL _m , the application-specific integrated circuit 14 will transmit multiple data voltage signals to the liquid crystal display area 20 through the P transmission wires SL ₁ -SL _P source driver 16. The source driver 16 includes n switch units 162 and n/p shift register units HSR ₁ ˜HSR _n/p , each shift register unit HSR ₁ ˜HSR _n/p corresponds to P switch units 162 , and Each switch unit 162 corresponds to one data line. When the liquid crystal display area 20 receives the scan signal, the switch unit 162 controls whether the data voltage signal from the application-specific integrated circuit 14 will pass through according to the control signal provided by the shift register unit HSR ₁ ˜HSR _n/p. Transmission wires SL ₁ -SL _P enter data lines DL ₁ -DL _P . Each shift register unit HSR ₁ ˜HSR _n/p can drive P switch units at a time. The shift register unit HSR ₁ first turns on the corresponding switch unit 162 , so that the data voltage signal enters the data lines DL ₁ -DL _P sequentially through the P transmission wires SL ₁ -SL _P respectively. Next, the shift register unit HSR ₂ will turn on the corresponding switch unit 162 again, so that the data voltage signal enters the data lines DL _P+1 -DL _2P sequentially through the P transmission wires SL ₁ -SL _P respectively, and so on Proceed until the HSR _n/p turns on the corresponding switch unit 162, so that the data voltage signal enters the data lines DL _n*P+1 -DL _n sequentially through the P transmission wires SL ₁ -SL _P respectively.

Under the high-resolution panel design, multiple transmission wires will be required (P is a positive integer and P is not greater than n). It can be noted from FIG. 1 that the traditional wiring method is to place the source driver 16 next to the first side 201 (not shown in the figure) of the liquid crystal display area 20, and connect the gate driver 18 and the application-specific integrated circuit 14 They are respectively placed next to the second side 202 (not shown in the figure) and the third side 203 (not shown in the figure). Once the resolution of the liquid crystal display area 20 increases, the number of transmission wires SL ₁ -SL _P will inevitably increase, so the number of transmission wires SL ₁ -SL _P will cause the width W1 to increase accordingly and occupy the use space of the substrate 12 . This will cause the side of the liquid crystal display device 10 where the transmission wires SL ₁ -SL _P are arranged to have a wider width, resulting in a visually unsightly appearance. Therefore, how to achieve the design requirement of slim border of the panel is an urgent problem to be overcome.

Contents of the invention

In view of this, the purpose of the present invention is to provide a liquid crystal display device and its driving method, which can make the widths of both sides of the display area of the display device narrow and even, so as to solve the above-mentioned problems in the prior art.

个数据电压信号。该第二数据移位暂存器设置于该第三侧边，其包含多个第二移位暂存单元，每一第二移位暂存单元用来产生一第二控制信号时。该多个第二开关单元设置于该第三侧边，每一第二开关单元用来于接收该第二控制信号时，依序输出从该第个至第P个数据电压信号。The present invention provides a display device, which includes a substrate, a display area, a display area, a first data shift register, a second data shift register, a plurality of first switch units and a plurality of a first switch unit. The display area is disposed on the substrate and includes a first side, a second side and a third side, the first side is perpendicular to the second side and the third side, and the first side is perpendicular to the second side and the third side. The two sides are opposite to the third side, and the display area is used to display images. The application-specific integrated circuit is disposed on the first side for outputting P data voltage signals. The first data shift register is disposed on the second side, and includes a plurality of first shift register units, and each first shift register unit is used to generate a first control signal. The plurality of first switch units are arranged on the second side, and each first switch unit is used to sequentially output from the first to the first control signal when receiving the first control signal.

A data voltage signal. The second data shift register is disposed on the third side, and includes a plurality of second shift register units, and each second shift register unit is used to generate a second control signal. The plurality of second switch units are arranged on the third side, and each second switch unit is used to sequentially output the to the Pth data voltage signal.

个数据电压信号，且同时这些第二开关单元依序输出从该第

个至第P个数据电压信号。Another embodiment of the present invention provides a driving method of a display device, the display device includes a display area, a first data shift register, a second data shift register, a plurality of first switch units and a plurality of second switch units, the display area includes a first side, a second side and a third side, the first side is perpendicular to the second side and the third side, the The second side is opposite to the third side, the first data shift register includes a plurality of first shift register units, and each first shift register unit is coupled to the plurality of first switches The unit is arranged on the second side, the second data shift register includes a plurality of second shift register units and a plurality of second switch units, and each second shift register unit is coupled to multiple a second switch unit arranged on the third side, the method includes: using a special application integrated circuit to output P data voltage signals, the application specific integrated circuit is arranged on the first side; and when the first shifts When the bit temporary storage unit and the second shift temporary storage units generate a control signal, the first switch units sequentially output the first to the second

a data voltage signal, and at the same time, these second switch units sequentially output from the first

to the Pth data voltage signal.

In the present invention, the application-specific integrated circuit sends data signal voltages sequentially, and no additional mechanism is needed in the design of circuit timing, that is, no additional components are added to the display device. Moreover, compared with the width W1 of the prior art, the widths W2 and W3 of this embodiment are only half of W1, so in terms of the structure of the liquid crystal display device, the widths on both sides of the display area are narrow and average, and the visual effect is better. .

Description of drawings

FIG. 1 is a schematic diagram of a prior art liquid crystal display device.

FIG. 2 is a timing diagram of the shift register unit and data voltage signals in FIG. 1 .

FIG. 3 is a schematic diagram of a liquid crystal display device of the present invention.

FIG. 4 is a timing diagram of the shift register unit and data voltage signals of FIG. 3 .

Fig. 5 is a flowchart of the driving method of the present invention.

Figure number:

10, 100 LCD display device 20, 110 display area

18, 108 Gate Driver 16, 106, 116 Source Driver

12, 102 Substrate HSR ₁ ~ HSR _1-n/P shift temporary storage unit

162 Switching unit SL ₁ -SL _P transmission line

DL ₁ -DL _P data line 22, 114 printed circuit board

GL ₁ -GL _m gate line 1101 first side

1102 second side 1103 third side

1104 fourth side 1061, 1161 shift register

1062, 1162 switch unit

Detailed ways

In order to make the above and other purposes, features and advantages of the present invention more obvious and understandable, the detailed description is as follows in conjunction with the accompanying drawings:

条传输导线

至源极驱动器106，以及经过

条传输导线传递

个数据电压信号至源极驱动器116。源极驱动器106设置于显示区域110的第二侧边1102旁，其包含一第一数据移位暂存器1061与个开关单元1062，第一数据移位暂存器1061由移位暂存单元HSR_1-1～HSR_1-n/p组成，每一移位暂存单元HSR_1-1～HSR_1-n/p对应

个开关单元1062。源极驱动器116设置于显示区域110的第三侧边1103旁，其包含一第二数据移位暂存器1161与

个开关单元1162，第二数据移位暂存器1161由移位暂存单元HSR_2-1～HSR_2-n/p组成，每一移位暂存单元HSR_2-1～HSR_2-n/p对应控制

个开关单元1162。每一个开关单元1062、1162都对应到一条数据线，并依据移位暂存单元HSR_1-1～HSR_1-n/p与HSR_2-1～HSR_2-n/p所产生的控制信号对数据线进行充电动作。栅极驱动器108则设置于显示区域110的第四侧边1104旁，用来产生多个扫描电压信号至显示区域110。在本实施例中，因为二源级驱动器106、116分别设置于显示区域110相对的两侧边1102、1103旁，而且与特殊应用集成电路104分别通过传输导线连接，所以传输导线在显示面板110两侧的个数减半。相较于现有技术的宽度W1，本实施例的宽度W2、W3仅有W1的一半，所以液晶显示装置100在构造上，显示区域110两侧的宽度较窄也较平均，其视觉效果较佳。Please refer to FIG. 3 , which is a schematic diagram of a display device 100 of the present invention. The display device 100 includes a substrate 102 , an ASIC 104 , source drivers 106 , 116 , a gate driver 108 and a display area 110 . The source drivers 106, 116 and the gate driver 108 are arranged on the flexible circuit board by chip on film (COF), or arranged on the glass substrate 102 by chip on glass (COG). The flexible circuit board is then electrically connected to the circuit board 114 . The ASIC 104 is disposed on the circuit board 114 . The ASIC 104 is disposed on the circuit board 114 and coupled to the source drivers 106 , 116 . The display area 110 may be a liquid crystal display panel, which includes m×n pixels (pixels), and passes through m gate lines (scanline) GL ₁ -GL _m and n data lines (data line) DL ₁ -DL respectively. _n is coupled to the gate driver 108 and the source drivers 106 , 116 . The ASIC 104 is disposed beside the first side 1101 of the display area 110 for passing through

transmission wire

to source driver 106, and through

transmission wire transfer

data voltage signal to the source driver 116. The source driver 106 is disposed beside the second side 1102 of the display area 110 and includes a first data shift register 1061 and switch units 1062, the first data shift register 1061 is composed of shift register units HSR _1-1 ~ HSR _1-n/p , each shift register unit HSR _1-1 ~ HSR _{1-n/ p} corresponds to

switch unit 1062. The source driver 116 is disposed beside the third side 1103 of the display area 110, and includes a second data shift register 1161 and

switch unit 1162, the second data shift register 1161 is composed of shift register units HSR _2-1 ~ HSR _2-n/p , each shift register unit HSR _2-1 ~ HSR _{2-n/ p} corresponds to control

switch unit 1162. Each switch unit 1062, 1162 is corresponding to a data line, and according to the control signal pair generated by the shift temporary storage unit HSR _1-1 ~ HSR _1-n/p and HSR _2-1 ~ HSR _2-n/p The data line performs the charging action. The gate driver 108 is disposed beside the fourth side 1104 of the display area 110 for generating a plurality of scanning voltage signals to the display area 110 . In this embodiment, because the two source drivers 106, 116 are respectively arranged beside the two opposite sides 1102, 1103 of the display area 110, and are connected to the application-specific integrated circuit 104 through transmission wires respectively. connection, so the number of transmission wires on both sides of the display panel 110 is reduced by half. Compared with the width W1 of the prior art, the widths W2 and W3 of this embodiment are only half of W1, so in terms of the structure of the liquid crystal display device 100, the widths on both sides of the display area 110 are narrower and more even, and its visual effect is better. good.

(步骤508)。移位暂存单元HSR_1-1会先送出控制信号开启对应的开关单元1062，使得数据电压信号依序经过

条传输导线

分别依序进入数据线同时，移位暂存单元HSR_2-1也会送出控制信号开启对应的开关单元1162，使得数据电压信号经过

条传输导线

依序进入数据线

接下来，移位暂存单元HSR_1-2再送出控制信号开启对应的开关单元1062，使得数据电压信号依序经过

条传输导线

分别依序进入数据线

同时，移位暂存单元HSR_2-2也会再送出控制信号开启对应的开关单元1162，使得数据电压信号经过

条传输导线

依序进入数据线

如此依序进行直到HSR_n/P开启对应的开关单元1162，使得数据电压信号经过条传输导线

分别依序进入数据线

为止。Please refer to FIG. 3 , FIG. 4 and FIG. 5 together. FIG. 4 is a timing diagram of the shift register unit and data voltage signals in FIG. 3 , and FIG. 5 is a flow chart of the driving method of the present invention. During the display process (that is, the period when the scan signal VCK is at a high voltage level), the gate driver 108 generates a scan signal to the display area 110 (step 502 ). Afterwards, the ASIC 104 outputs P data voltage signals (step 504 ). Next, the first shift register units HSR ₁ to HSR _1-n/P and the second shift register units HSR _2-1 to HSR _2-n/P respectively generate a first control signal and a second control signal signal (step 506). When the display area 110 receives a scan signal, the switch units 1062 and 1162 will control the signals from the shift register units HSR ₁ ˜HSR _1-n/P and HSR _2-1 ˜HSR _2-n/P respectively according to the control signals provided by Whether the data voltage signal of ASIC 114 enters the transmission wire

(step 508). The shift register unit HSR _1-1 will first send a control signal to turn on the corresponding switch unit 1062, so that the data voltage signal passes through

transmission wire

Enter the data line in sequence At the same time, the shift register unit HSR _2-1 will also send a control signal to turn on the corresponding switch unit 1162, so that the data voltage signal passes through

transmission wire

data line

Next, the shift register unit HSR _1-2 sends a control signal to turn on the corresponding switch unit 1062, so that the data voltage signal passes through

transmission wire

Enter the data line in sequence

At the same time, the shift register unit HSR _2-2 will also send a control signal to turn on the corresponding switch unit 1162, so that the data voltage signal passes through

transmission wire

data line

This is performed in sequence until the HSR _n/P turns on the corresponding switch unit 1162, so that the data voltage signal passes through transmission wire

Enter the data line in sequence

until.

也就是说，本实施例的特殊应用集成电路114输出的P个数据信号电压的时序不需要另外再调整，仍旧只是依序输出从该第1个至第P个数据电压信号至开关单元1062、1162。当移位暂存单元HSR_1-1～HSR_1-n/P以及移位暂存单元HSR_2-1～HSR_2-n/P接收控制信号时，移位暂存单元HSR_1-1～HSR_1-n/P依序输出从该第1个至第P/2个数据电压信号，且同时移位暂存单元HSR_2-1～HSR_2-n/P依序输出从该第

个至第P个数据电压信号。Please note that ASIC 114 sequentially writes P data signal voltages (as shown by arrow A in FIG. 3 ) into transmission lines SL ₁ -SL _P at the same time, and then when switch units 1062 and 1162 receive signals from shift When the control signals of the temporary storage units HSR _1-1 and HSR _2-1 are turned on, the data voltage signals enter the data lines in sequence

That is to say, the timing sequence of the P data signal voltages output by the application-specific integrated circuit 114 of this embodiment does not need to be further adjusted, and it is still only sequentially output from the first to the Pth data voltage signals to the switch unit 1062, 1162. When the shift temporary storage units HSR _1-1 ~ HSR _1-n/P and the shift temporary storage units HSR _2-1 ~ HSR _2-n/P receive the control signal, the shift temporary storage units HSR _1-1 ~ HSR _1-n/P sequentially outputs the data voltage signals from the first to P/2th, and at the same time, the shift temporary storage units HSR _2-1 ~ HSR _2-n/P sequentially output from the first

to the Pth data voltage signal.

Of course, in other embodiments of the present invention, the transmission wires can also be arranged in an odd-numbered and even-numbered arrangement, that is, when the control signals of HSR _1-1 and HSR _2-1 are turned on, the data voltage signals are respectively Enter the data lines DL ₁ , DL _{3 .} . . and DL ₂ , DL ₄ .

连接，而且每一传输导线分别用以依序驱动一行的像素，所以特殊应用集成电路104可以顺着箭头A的方向依序发送P个数据信号电压而不需要调整发送P个数据信号电压的顺序，故在电路时序的设计上可以不需设计额外的机制以迁就特殊应用集成电路104的输出次序。Since the ASIC 104 respectively passes through the transmission wire

connection, and each transmission wire They are respectively used to sequentially drive a row of pixels, so the application-specific integrated circuit 104 can sequentially send P data signal voltages in the direction of arrow A without adjusting the order of sending P data signal voltages, so in the design of circuit timing Therefore, there is no need to design additional mechanisms to accommodate the output sequence of the ASIC 104 .

连接。因为传输导线在显示面板110两侧的个数减半，所以相较于现有技术液晶显示器的宽度W1，本实施例的宽度W2、W3仅有W1的一半。也因此本发明液晶显示装置在构造上，显示区域110两侧的宽度较窄也较平均，其视觉效果较佳。此外，特殊应用集成电路104仍依序输出从该第1个至第P个数据电压信号，其输出时序也不需再另外调整，所以不需要更动特殊应用集成电路的电路设计。Compared with the prior art, the liquid crystal display device of the present invention includes two source drivers 106, 116, and the two source drivers 106, 116 are respectively arranged beside the opposite sides 1102, 1103 of the display area 110, and are integrated with special applications circuit 104 respectively through transmission wires

connect. Because the number of transmission wires on both sides of the display panel 110 is reduced by half, compared with the width W1 of the liquid crystal display in the prior art, the widths W2 and W3 of this embodiment are only half of W1. Therefore, in terms of the structure of the liquid crystal display device of the present invention, the widths on both sides of the display area 110 are narrow and average, and the visual effect is better. In addition, ASIC 104 still outputs the first to Pth data voltage signals sequentially, and the output timing does not need to be adjusted, so the circuit design of ASIC does not need to be changed.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the claims.

Claims (9)

1. A display device, characterized in that the display device comprises: a substrate; A display area, set on the substrate, it includes a first side, a second side and a third side, the first side is perpendicular to the second side and the third side a side, the second side is opposite to the third side, and the display area is used to display images; An application-specific integrated circuit, disposed on the first side, for outputting P data voltage signals; a first data shift register, disposed on the second side, comprising a plurality of first shift register units, each first shift register unit is used to generate a first control signal; A plurality of first switch units are arranged on the second side, and each first switch unit is used to sequentially output from the first to the first control signal when receiving the first control signal.

a data voltage signal; A second data shift register, disposed on the third side, which includes a plurality of second shift register units, each second shift register unit is used to generate a second control signal; as well as A plurality of second switch units are arranged on the third side, and each second switch unit is used to sequentially output the second control signal from the second control signal.

to the Pth data voltage signal. 2. The display device according to claim 1, wherein the display device further comprises a gate driver disposed on a fourth side of the display area, the fourth side is opposite to the The first side is used to generate a plurality of scanning voltage signals to the display area. 3. The display device according to claim 1, wherein the first data shift register and the plurality of first switch units are disposed in a first source driver. 4. The display device as claimed in claim 1 , wherein the second data shift register and the plurality of second switch units are disposed in a second source driver. 5. The display device according to claim 1, wherein the ASIC outputs the P data voltage signals in sequence. 6. The display device according to claim 1, wherein the display area is a liquid crystal display panel. 7. The display device according to claim 1, wherein the application-specific integrated circuit is arranged on a chip using a chip on film (COF) or a chip on glass (COG) method. on the substrate. 8. A driving method of a display device, wherein the display device comprises a display area, a first data shift register, a second data shift register, a plurality of first switch units and A plurality of second switch units, the display area includes a first side, a second side and a third side, the first side is perpendicular to the second side and the third side side, the second side is opposite to the third side, the first data shift register includes a plurality of first shift register units, and each first shift register unit is coupled to The plurality of first switch units are arranged on the second side, the second data shift register includes a plurality of second shift register units and a plurality of second switch units, each second The shift register unit is coupled to a plurality of second switch units and disposed on the third side, and the method includes: Utilizing an ASIC to output P data voltage signals; and When the first shift register units and the second shift register units generate a control signal, the first switch units sequentially output

a data voltage signal, and at the same time, the second switching units sequentially output from the first

to the Pth data voltage signal. 9. The method according to claim 8, wherein the display device further comprises a gate driver disposed on a fourth side of the display area, the fourth side is opposite to the first On the one hand, the method further includes: When the gate driver generates a plurality of scan voltage signals, and the first shift register units and the second shift register units receive a control signal, the first switch units are sequentially output from the 1st to the

a data voltage signal, and at the same time, the second switching units sequentially output from the first

to the Pth data voltage signal.

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