CN101278352B

CN101278352B - Daisy chain cascade device and method

Info

Publication number: CN101278352B
Application number: CN200680036482XA
Authority: CN
Inventors: 潘弘柏; 金镇祺; 吴学俊
Original assignee: Mosaid Technologies Inc
Current assignee: Mosaid Technologies Inc
Priority date: 2005-09-30
Filing date: 2006-09-29
Publication date: 2012-05-30
Anticipated expiration: 2026-09-29
Also published as: CN101278354A; CN107358974A; CN110047528A; CN101278352A; CN110096469A

Abstract

The present invention provides a technique for serially coupling devices in a daisy chain cascade arrangement. The devices are coupled in a daisy chain cascade arrangement such that an output of a first device is coupled to an input of a second device in the daisy chain to provide for the transfer of information, such as data, address and command information, and control signals from the first device to the second device. Devices coupled in a daisy chain cascade include a Serial Input and a Serial Output (SO). Information is input to the device via the SI. The information is output from the device via the SO. The SO of a preceding device in the daisy chain cascade is coupled to the SI of a succeeding device in the daisy chain cascade. Information input to a preceding device via the SI of the device is transmitted via the device and output from the device via the SO of the device. The information is then transferred to the SI of the following device via the connection between the SO of the preceding device and the SI of the following device.

Description

Daisy chain cascading devices and method

Background technology

With the computing machine is that basic system is seen everywhere current, and successfully enters into the employed many equipment of daily life, like mobile phone, laptop computer, automobile, medical treatment device, PC or the like.At large, it is the system on basis that society has depended on the computing machine when handling routine work in a large number, as working such as the work of relative complex such as forecast weather from the simple of balance bill.Along with the development of technology, it is the system on basis that increasing work is transferred to the computing machine.This also makes society more and more depend on these systems.

Typical is that basic system comprises system board and optional one or more peripherals with the computing machine, like display unit, and storage unit etc.System board can comprise one or more processors, storage subsystem and other logic, and like serial device interfaces, network equipment controller, hard disk controller etc.

The type of the processor that on the particular system plate, uses depends on the type of work performed in the system usually.For example, the system of the one group of work that carry out to limit by emission that car engine produced and adjust air/fuel mixture to guarantee the engine clean-burning fuel, can adopt simple application specific processor like monitoring, is used for carrying out these work specially.On the other hand; Carry out the system of many different operatings; As manage many users and move many different application, can adopt one or more more complex processing devices, it is general in essence for these processors; Through being configured to carry out supercomputing and deal with data, thereby the response time of service users request is reduced to minimum.

Storage subsystem is the storer that is used to preserve processor institute use information (like instruction, data value).Storage subsystem typical case comprises steering logic and one or more memory device.Steering logic typically is configured to the interface between memory device and processor, so that processor can store information to memory device and fetch information from memory device.Memory device has been preserved actual information.

Similar with processor, the type of the equipment that uses is usually by the type decided of the performed task of computer system on storage subsystem.For example, computer system possibly have the work of under the help that does not have disc driver, starting shooting and carrying out one group of software routines that seldom changes.At this moment, storage subsystem can adopt non-volatile equipment, and for example flash memory device comes the storing software routine.Other computer system possibly carried out very complicated work, needs a large amount of high-speed data storeies to preserve great deal of information.At this moment, storage subsystem can adopt high-speed and high-density dynamic RAM (DRAM) device to preserve great deal of information.

At present, hard disk drive has can store 20 high density to the 40G byte data, but volume is huge relatively.Yet flash memory (flash memory) also is called as solid-state drive, owing to its high density, non-volatile and receive an acclaim with respect to the small size of hard disk drive.Flash memory technology is based on EPROM and EEPROM technology.Selecting " sudden strains of a muscle " speech is because of in single job, wiping a large amount of storage unit, is different among the EEPROM single job and wipes a byte.With respect to the single-layer type storage unit, the appearance of multiple field storage unit (MLC) has further increased the density of flash memory.It will be understood by those skilled in the art that flash memory can be configured to NOR flash memory or nand flash memory, nand flash memory is wherein stored arrangement architecture more closely and is had higher density at each given area owing to it.For follow-up illustrative purposes, the flash memory of being mentioned can be considered to the flash memory of NOR or NAND or other type.

Equipment in the storage subsystem adopts the interconnection of parallel interconnection mechanism usually.This mechanism relates to and is connected to by this way on the equipment: address and data message and control signal are coupled on the equipment with parallel mode.Each equipment can comprise a plurality of I/O, so that parallel transfer data and address information and control signal are to equipment.

Summary of the invention

With the shortcoming that in storage subsystem, adopts parallel join dependency be that equipment room often needs a large amount of interconnection to transmit information and signal concurrently at equipment room.This has just increased the complexity of the plate that adopts these storage subsystems.In addition, the ill effect relevant with a large amount of interconnection, as crosstalk (crosstalk) tend to limit the performance of these subsystems.And, be included in the signal transmission delay that the amount of equipment in these subsystems may bring because of interconnection and be restricted.

Technology described herein has overcome above-mentioned defective through the technology that equipment is arranged coupling with daisy chain cascading is provided, and daisy chain cascading arrangement is wherein compared with in parallel realization and adopted less with short being connected.Because adopted less and short interconnection can make whole enforcement seldom receive the influence of ill effect; Like transmission delay and crosstalk, so the mode configuration device of arranging with daisy chain cascading can allow equipment more in parallel realization when operation to have faster speed.In addition, less with being connected of weak point often reduced the complicacy that realizes.The complicacy that is reduced further makes the subsystem that comprises this equipment on littler area, to implement, and therefore allows subsystem to take less area.

Some aspects according to said technology; Equipment is arranged coupling with daisy chain cascading; So that the output of the equipment formerly in the daisy chain cascading is coupled to the input at back equipment in the daisy chain cascading; With provide from equipment formerly to the information of back equipment (as, data, address and command information) and the transmission of control signal (like, enable signal).

In an embodiment of present technique, each equipment in the daisy chain cascading comprises serial input (SI) and serial output (SO).Information is input in the equipment through the SI of equipment.Similarly, information is through the SO equipment output of equipment.The SO of equipment is coupled to the SI of next equipment in the daisy chain cascading in the daisy chain cascading.In equipment, circuit is set so that the SI through equipment be input in the daisy chain cascading one formerly the information of equipment transmit through this equipment, and the SO through equipment is from this equipment output.Connection between the SI of SO and the next equipment of information through equipment formerly then is sent to the SI of next equipment in the daisy chain cascading.The information that is transmitted can be imported into through the SI of next equipment in the next equipment.

In addition, clock signal is coupled to the equipment in the daisy chain cascading.This clock signal is used so that the transmission of the equipment of information from daisy chain cascading to next equipment room to be provided by equipment.

According to the others of said technology, for the control signal (like enable signal) of equipment used (for example make data be input to equipment through SI and through SO with exporting in the data slave unit) transmits at the equipment room of foregoing daisy chain cascading.Here, circuit is set propagates through this equipment, and be sent to the input of the next equipment the daisy chain cascading from this equipment through an output with the control signal that enables to be input to the equipment formerly in the daisy chain cascading.The control signal that is transmitted then is input to next equipment through this input.

According to principle of the present invention, flash memory system can have a plurality of flash memory devices connected in series.Flash memory device in this system can comprise the serial data link interface with serial input data port and serial data output port; Be used to receive the control input end mouth of the first input enable signal, and the control output end mouth that is used to send the second input enable signal.The input enable signal is used in circuit, with the transmission of control data between serial data link interface and memory bank.Flash memory device is configured to receive serial input data and control signal and to external unit data and control signal are provided from external source.External source and external unit can be other flash memory devices in the system.In an embodiment of the present invention, when equipment in system during serially concatenated, these equipment are the output control terminal mouth further, these control ports " are passed received IPE and OPE signal back (echo) " to external unit.This permission system has the signal port of point-to-point connection, to form daisy chain cascading mechanism (with respect to broadcasting/multiple spot cascade mechanism).

These systems can adopt distinctive device identifier and target device to select addressing mechanism; And do not use the limited hardware physical equipment to select pin; Therefore total system is easy to aspect storage density, expand as much as possible, and need not the overall performance of sacrificial system.In some embodiments of the invention, each flash memory device can comprise a distinctive device identifier.This equipment can be configured to resolve the target device information territory in serial input data, is associated with the peculiar EIC equipment identification code with target address information and equipment, to confirm whether this equipment is target device.This equipment can be before handling received any other input data, first evaluating objects facility information territory.If memory device is not a target device, then can ignores serial input data, thereby save extra processing time and resource.

Description of drawings

Illustrate and describe,, make that aforementioned content is more clear through following more detailed description to exemplary embodiment of the present invention.In the accompanying drawing, same tag is meant the same section that spreads all among the different figure.These figure draw in proportion, but focus on the explanation embodiments of the invention.

Fig. 1 is the structured flowchart of example devices, and it comprises a plurality of single port equipment with the daisy chain cascading alignment arrangements of serial;

Fig. 2 is the structured flowchart of example devices, and it comprises a plurality of single port equipment with the serial daisy chain cascade arrangement configuration with cascade clock;

Fig. 3 is the structured flowchart of example devices, and it comprises a plurality of dual-port equipment with the configuration of serial daisy chain cascade arrangement;

Fig. 4 is the structured flowchart of example devices, and it comprises that this serial daisy chain cascade arrangement is that various enable signals provide input and output with a plurality of single port equipment of serial daisy chain cascade arrangement configuration;

Fig. 5 is the structured flowchart of example devices, and it comprises that this serial daisy chain cascade arrangement is that various enable signals provide input and output with the dual-port equipment of serial daisy chain cascade arrangement configuration;

Fig. 6 is the structured flowchart of example devices, and it comprises that this equipment has a plurality of serial input terminals and a plurality of serial output terminal with a plurality of equipment of serial daisy chain cascade arrangement configuration;

Fig. 7 be described in on the specific installation of serial daisy chain cascade arrangement configuration with a plurality of equipment of configuration on the sequential chart of correlation timing when carrying out read operation;

Fig. 8 is the sequential chart of the description sequential relevant with the equipment room transmission information that is disposed with the serial daisy chain cascade arrangement;

Fig. 9 is the high level block diagram of single port example of equipment property serial output control logic;

Figure 10 is the high level block diagram of dual-port example of equipment property serial output control logic;

Figure 11 is the detailed diagram that is used for example of equipment property serial output control logic;

The example of equipment property structured flowchart of Figure 12 for disposing and comprise exemplary serial output control logic with the serial daisy chain cascade arrangement;

Figure 13 is the sequential chart of description with the input and output correlation timing of the equipment that includes the exemplary series output control logic.

Figure 14 is the block diagram of exemplary series output control logic, and this steering logic can be used for the data that the storer in first equipment in the daisy chain cascading is stored are sent to second equipment in the daisy chain cascading;

Figure 15 will be included in the sequential chart that data in the storer of first equipment in the daisy chain cascading are sent to the correlation timing of second equipment in the daisy chain cascading for describe adopting the exemplary series output control logic.

Embodiment

Below preferred embodiment of the present invention is described:

Fig. 1 is the structured flowchart of example devices, and it comprises a plurality of single port equipment 110a-e with the daisy chain cascading alignment arrangements of serial.Equipment 110a-e is exemplary memory device, respectively includes storer (not illustrating in the drawings), and this storer can comprise dynamic RAM (DRAM) unit, static RAM (SRAM) unit, flash cell or the like.Each equipment 110 includes serial input (SI), serial output (SO), and clock (SCLK) input and sheet are selected (CS#) input.

The serial input is used to transmission information (like order, address and data message) to equipment 110.Serial output is used to slave unit 110 and spreads out of information.The SCLK input is used for to equipment 110 outside clock signal being provided, and the CS# input is used for to equipment 110 chip selection signal being provided.An example of the equipment that can use with technology described herein is how independent serial link (MISL) memory device in No. the 11/324th, 023, U.S. Patent application.

SI and SO that the equipment that daisy chain cascading is arranged is 110 are connected to each other, so that the SO in the more preceding equipment 110 is coupled to the SI of next equipment 110 in the daisy chain cascading in daisy chain cascading.For example, the SO of equipment 110a is connected to the SI of equipment 110b.The SCLK input of each equipment 110 is presented with the clock signal from for example memory controller (not illustrating in the drawings).This clock signal is assigned to each equipment 110 through common connection.Be described below, SCLK is used to the information of the equipment of being input to 110 is latched in the various registers that comprise especially.

The information that is input to equipment 110 can provide the different of clock signal to the SCLK input constantly to be latched.For example, in single data rate (SDR) was realized, the information that is input to equipment 110 through SI can be latched in SCLK rising edge of clock signal or negative edge.Interchangeable, in double data rate (DDR) (DDR) realized, the information that is input to equipment 110 through SI all can be latched in SCLK rising edge of clock signal and negative edge.

Being used to of each equipment selected the CS# of equipment to be input as traditional sheet to select.This input is coupled to public link so that sheet selects signal to be arrived all equipment 110 by parallel establish (assert), thereby simultaneously all devices 110 is selected.

Fig. 2 is the structural representation of example devices, and it comprises a plurality of single port equipment 210a-e with the serial daisy chain cascade arrangement configuration with cascade clock.Each equipment 210 comprises aforesaid SI, SO, SCLK input and CS# input.In addition, each equipment 210 comprises clock output (SCLKO).The output terminal that this SCLKO exports for the SCLK signal that will be input to equipment 210.

With reference to figure 2, as previously mentioned, the SI of equipment 210 and SO are coupled with the daisy chain cascading of serial.In addition, the SCLK of equipment input is also arranged with the daisy chain cascading of serial with SCLKO output and is coupled, and makes the SCLK that in the daisy chain cascading SCLKO in the more preceding equipment 210 is coupled to next equipment 210 in the daisy chain cascading import.Therefore, for example, the SCLKO of equipment 210a is coupled to the SCLK input of equipment 210b.

Notice that clock signal can produce delay when propagating through the device of daisy chain cascading.Can adopt the internal latency compensating circuit,, get rid of this delay like delay lock loop (DLL) circuit.

Fig. 3 is the structural representation of example devices, and it comprises a plurality of dual-port equipment 310a-e with the configuration of serial daisy chain cascade arrangement.Each equipment 310 respectively comprises a SI and SO at each port, also comprises foregoing SCLK input and CS# input.With reference to figure 3, the SI of first port is marked as " SI0 " on the equipment 310, and the SI of second fracture is marked as " SI1 ".Similarly, the SO of first port is marked as " SO0 ", and the SO of second port is marked as " SO1 ".The SO of each port and SI are connected between the equipment 310 as previously mentioned.Therefore, for example, the SO of the port 0 on the equipment 310a is fed to the SI of the port 0 on the equipment 310b, and so on.Similarly, the SO of the port one on the equipment 310a is fed to the SI of the port one on the equipment 310b, and so on.

Fig. 4 is the structural representation of example devices, and it comprises that this serial daisy chain cascade arrangement has the input and output that are used for various enable signals with a plurality of single port equipment of serial daisy chain cascade arrangement configuration.Each equipment 410 comprises foregoing SI, SO, CS# input, SCLK input.In addition, each equipment 410 comprises that also input port enables that (IPE) input, output port enable (OPE) input, input port enables output (IPEQ) and output port and enables output (OPEQ).The IPE input is used for the signal to equipment input IPE.The IPE signal is used for enabling SI by equipment, makes when IPE is established, and information can be input to equipment 410 through the SI serial.Similarly, the OPE input is used for the signal to equipment input OPE.The OPE signal is used for enabling SO by equipment, makes when OPE is established, and information can be through SO slave unit 410 serials output.IPEQ and OPEQ are the output terminal of difference slave unit output IPE and OPE signal.The IPEQ signal can be the IPE signal that postpones, or the modification of IPE signal.Similarly, the OPEQ signal possibly be the OPE signal that postpones, or the modification of OPE signal.The CS# input is imported with SCLK and is coupled to different links, and this link distributes CS# and SCLK signal to foregoing equipment 410a-d respectively.

As previously mentioned, SI and the SO device coupled of arranging from daisy chain cascading is to next equipment.In addition, an IPE input and an OPE input of being coupled to the next equipment 410 in the daisy chain cascading respectively during daisy chain cascading is arranged at the IPEQ and the OPEQ of preceding equipment 410.This arrangement permission IPE and OPE signal are sent to next equipment from an equipment 410 of daisy chain cascading.

Fig. 5 is the structural representation of example devices, and it comprises that this serial daisy chain cascade arrangement comprises the input and output that are used for various enable signals with the dual-port equipment 510a-d of serial daisy chain cascade arrangement configuration.Each equipment 510 comprises foregoing CS# input, SCLK input, and on each port, comprises SI, SO, IPE, OPE, IPEQ and OPEQ.SI, SO, IPE, OPE, IPEQ and OPEQ in port one and the port 2 is expressed as SI1, SO1, IPE1, OPE1, IPEQ1 and OPEQ1 respectively, and SI2, SO2, IPE2, OPE2, IPEQ2 and OPEQ2.

As stated, the CS# of each equipment 510 input is coupled to single link to select all devices 510 simultaneously.Similarly, as stated, the SCLK of each equipment 510 is coupled to single link, to be configured to distributing clock signal to arrive all devices 510 simultaneously.And as stated, SI, SO, IPE, OPE, IPEQ and OPEQ are coupled at equipment room, so that a SO at preceding equipment, IPEQ and OPEQ in the daisy chain cascading are coupled to SI, IPE and an OPE at back equipment in the daisy chain cascading.For example, the SO1 of equipment 510a, SO2, IPEQ1, IPEQ2, OPEQ1 and OPEQ2 are coupled to SI1, SI2, IPE1, IPE2, OPE1 and the OPE2 among the equipment 510b respectively.

SI, IPE and the OPE signal of SI, IPE and OPE input end that is input to equipment 510a respectively is provided for equipment 510a under the control of for example Memory Controller (not shown).Equipment 510d through SO, IPEQ and OPEQ output terminal among the equipment 510d to Memory Controller return data and control signal.

Fig. 6 is the structural representation of example devices, and it comprises that this equipment has a plurality of serial input terminals (SI0 is to SIn) and a plurality of serial output terminal (SO0 is to SOn) with a plurality of equipment 610a-d of serial daisy chain cascade arrangement configuration.In addition, each equipment 610 has aforesaid SCLK input and CS# input.

Each equipment 610 employed serial input terminals (SI0 is to SIn) and serial output terminal (SO0 is to the SOn) information that makes is distinguished input and output device 610 with the mode of serial.Each input is assigned with specific role to import certain type data (like the address, order, data) and/or signal (like enable signal) to equipment 610.Similarly, each output is assigned with data and the signal of specific role with certain type of slave unit 610 output.For example, one or more inputs can be assigned with the role that an ability is input to address information equipment 610.Similarly, for example, one or more outputs can be assigned with a role with 610 outputs of address information slave unit.

The serial input terminal on each equipment 610 and the quantity of serial output terminal depend on some factor usually, for example the quantity of address wire, order size and data width size.These factors can receive the influence how equipment uses in specific system applications.For example, and need compare, need can adopt equipment to the system applies that little information is carried out data storage, and therefore less I/O end arranged with less address wire and data line to the system applies that bulk information carries out data storage.

Fig. 7 be described in on the specific installation of serial daisy chain cascade arrangement configuration with configuration a plurality of equipment on the sequential chart of relevant sequential during the execution read operation.With reference to figure 7, CS# is established to select all equipment.Import into equipment to begin read operation through SI by the clock beat through establishing IPE and clock information that will be relevant with read operation.Exemplarily, these information comprise the order (CMD) of indication execution read operation and indicate column address of the memory starting address of reading of data (Col ADD) and row address (Row ADD) wherefrom.

At time " tR ", read the data of being asked and it is left in the specific internal data buffer the equipment of being included in from storer.The length of tR is determined by the characteristic of the unit that comprises storer usually.Behind time tR, OPE established so that data internally data buffer through the SO serial transmission to the next equipment of daisy chain cascading.Exemplarily, at the rising edge of SLCK, data are from being arranged in the inner buffer serial output of SO output terminal.The data delay that to export from the equipment that is positioned at daisy chain cascading clock period so long with control for example with propagate control signal (like IPE and OPE) relevant time delay (latency).As what will describe, adopt the clock synchronization latch to carry out control time delay.

The certain operations instance of the cascade memory device during the flash memory core architecture is implemented is presented at down in the tabulation 1.Table 1 has been listed destination device address (TDA), possible operation (OP) sign indicating number and column address, OK/corresponding states of body address, and import data.

Operation	Destination device address (1 byte)	OP sign indicating number (1 byte)	Column address (2 byte)	OK/body address (3 byte)	Input data (1 byte is to 2112 bytes)
						Page or leaf reads	tda	00h	Effectively	Effectively	-
Random data reads	tda	05h	Effectively	-	-
						The page or leaf that is used to duplicate reads	tda	35h	-	Effectively	-
The destination address input that is used to duplicate	tda	8Fh	-	Effectively	-
						The serial data input	tda	80h	Effectively	Effectively	Effectively
The random data input	tda	85h	Effectively	-	Effectively
						The page or leaf programming	tda	10h	-	-	-
Piece is wiped	tda	60h	-	Effectively	-
						Reading state	tda	70h	-	-	-
Read identification code (ID)	tda	90h	-	-	-
						Write configuration register	tda	A0h	-	-	Effectively (1 byte)
Write device title (DN) clauses and subclauses	00h	B0h	-	-	-
						Reset	tda	FFh	-	-	-
Body is selected	tda	20h	-	Effectively (body)	-

Table 1 command set

In some embodiments of the invention, each equipment of the system that in Fig. 1-6, is shown can have distinctive device identifier, to be used as the destination device address (tda) in the serial input data.When receiving serial input data, flash memory device is analyzed the destination device address in the serial input data, and comes through the distinctive device identification number of associated objects device address and equipment whether judgment device is target device.

Table 2 has shown the preferable input sequence according to the input traffic of embodiments of the invention (comprising the described system of combination Fig. 1-6).Order, address, and data begin serial ground shift-in or shift out each memory device from highest significant position.

With reference to figure 4, equipment 410a-d can enable (IPE) at input port and be utilized in the serial input signals (SIP) that serial clock (SCLK) rising edge samples when high and operate.Command sequence is with the destination device address (" tda ") of byte and the operational code of byte (also replacedly being called command code (" cmd " in the table 1)) beginning.Through in the highest significant position of serial input signals, adopting the byte destination device address as initial, equipment can be before handling any extra input data of being received, first evaluating objects address field.If memory device is not a target device, then can before processing, transmits this serial input data to another equipment, thereby save extra processing time and resource.

Operation

The 1st byte

The 2nd byte

The 3rd byte

The 4th byte

The 5th byte

The 6th byte

The 7th byte

The 8th byte

…

The 2116th byte

…

The 2119th byte

Page or leaf reads

tda

cmd

ca

ra

-

Random data reads

tda

cmd

ca

-

The page or leaf that is used to duplicate reads

tda

cmd

ra

-

The destination address input that is used to duplicate

tda

cmd

ra

-

The serial data input

tda

cmd

ca

ra

data

…

data

…

data

At random

tda

cmd

ca

data

…

data

-

The data input

?

The page or leaf programming

tda

cmd

-

Piece is wiped

tda

cmd

ra

-

Reading state

tda

cmd

-

Read ID

tda

cmd

-

Write configuration register

tda

cmd

data

-

Write the DN clauses and subclauses

tda

cmd

-

Reset

tda

cmd

-

List entries under table 2 byte mode

After the cmd of byte sign indicating number, TDA is displaced in the equipment with byte.Highest significant position (MSB) begins and latchs each position in the rising edge of serial clock (SCLK) from SIP.Depend on order, can follow column address byte, row address byte, body address byte after the byte command code, data byte, and/or combination or blank.

The sequential chart of the sequential that the data that Fig. 8 transmits for description and the equipment room that in the serial daisy chain cascade arrangement, is disposed are relevant.As stated, establish CS# with selection equipment.Through establishing IPE and at the rising edge of continuous SCLK clock data being sent into equipment by the clock beat, information is imported into first equipment in the serial daisy chain cascade arrangement.IPE passes through first device radiates to second equipment in less than the time of one-period.This makes in the one-period of information after getting into first equipment by the clock beat SI of second equipment that gets into by the clock beat from the SO of first equipment.This process repeats in the continuous device of serial daisy chain cascade.Therefore, for example, when the 3rd rising edge of the SCLK of a little counting latching of first equipment from data, information is input to the 3rd equipment in the serial daisy chain cascade.

Fig. 9 is the block diagram of the exemplary series output control logic 900 in the single port equipment.Logic 900 comprises the input buffer 902 that is used for IPE, the input buffer 904 that is used for SI (SIP), the input buffer 906 that is used for OPE, input and latch controller 908, is serial to parallel register 910, output latch controller 912, data register 914, address register 916, command interpreter 918, selector switch 920, page buffer 924, logical OR (OR) door 926, output state 928, selector switch 930 and storer 950.

Input buffer 902 be a kind of traditional low-voltag transistor to transistor logic (LVTTL) buffer, it is configured to buffer memory and presents the state of IPE signal that is positioned at the input end of buffer 902 to equipment.The output of buffer 902 offers input and latch controller 908, and it latchs the state of IPE signal and the state that latchs of IPE signal is provided to input buffer 904 and selector switch 920.Input buffer 904 is a kind of LVTTL buffers, and it is configured to buffer memory offers equipment through the SI input information.Input buffer 904 is enabled by input and latch controller 908.When being enabled, the information that offers the SI input is sent to an input that is serial to parallel register 910 and selector switch 930 by buffer 908.When the state that latchs of the IPE signal that is provided by input and latch controller 908 showed that the IPE signal is established, input buffer 904 was enabled.Offer the information that is serial to parallel register 910 and convert parallel form into from series form by register 910.The output that is serial to parallel register 910 offers data register 914, address register 916 and command interpreter 918.

Data register 914 and address register 916 are preserved the data and the address information of the equipment that offers through SI respectively.Command interpreter 918 is configured to explain the order of the equipment that is input to through SI.These orders are used for the operation of further opertaing device.For example, " memory write " orders the data that can be used to make equipment will be contained in data register 914 to write the storer 950 of the equipment of being arranged in via address register 916 specified addresses.

Input buffer 906 is the LVTTL buffer, and it is configured to the OPE signal that buffer memory offers the OPE input of equipment.The output of buffer 906 is sent to the output latch controller 912 of the state that is used to latch the OPE signal.The OPE signal condition of output latch controller output latch arrives or door 926.Or door 926 is traditional logic sum gate, and its output is used to the output of enable/disable output state 928.

Selector switch 920 selects 1 multiplexer for traditional 2, and it selects one of which as output from two inputs through signal DAISY_CHAIN.As previously mentioned, one of these inputs are the latch mode from input and latch controller 908 resulting IPE signals.Another input is set to logic low state.Whether signal DAISY_CHAIN display device is connected to one or more miscellaneous equipments with the serial daisy chain cascade arrangement.Exemplarily, if equipment is connected to one or more miscellaneous equipments with the serial daisy chain cascade arrangement, this signal is established.Establishing the feasible latch mode that offers the IPE signal of selector switch 920 of DAISY_CHAIN signal exports from selector switch 920.When the DAISY_CHAIN signal was not established, the logic low state that is input to selector switch 920 was exported from selector switch 920.

Page buffer 924 is the traditional data buffer, it be configured to preserve from storer 950 read information.Selector switch 930 selects 1 multiplexer for traditional 2, from two inputs, selects one as exporting through signal ID_MATCH.An input of selector switch 930 is provided by the output of page buffer 924, and another input is provided by the output of SI input buffer 904.The output of selector switch 930 offers output state 928.Signal ID_MATCH indication is sent to the particular command of equipment through SI, and whether addressing (addressed) is to this equipment.If this order is addressed to equipment, ID_MATCH is established so that the output of page buffer 924 is exported from selector switch 930.If ID_MATCH is not established, the output that then obtains from SI buffer 904 (that is, being input to the state of the SI signal of equipment) is from selector switch 930 outputs.

Storer 950 is traditional register, and it is configured to preserve data.Storer 950 can be the random-access memory (ram) that comprises a plurality of unit, like static RAM (SRAM) (SRAM), and dynamic ram (DRAM) or flash cell, it can use the address that is input to equipment through SI to carry out addressing.

Aspect when operation, the IPE signal of an establishment is carried out buffer memory and is sent to input and latch controller 908 by input buffer 902, and this controller latchs the state of the IPE that is established.This latch mode offers selector switch 920 and input buffer 904, to enable this buffer 904.Order, address and the data message that inputs to input buffer 904 is sent to then and is used for information is serial to parallel register 910 from what series form was transformed into parallel form, and respectively order, address and data message offered command interpreter 918, address register 916 and data register 914.The output of buffer 904 also is provided for selector switch 930.If ID_MATCH is not established, the output of buffer 904 can appear at the output of selector switch 930, and this output is provided for the input of output state 928.If DAISY_CHAIN is established, the latch mode of IPE can appear at the output of selector switch 920, and offer or the door 926 first the input.Or door 926 transmit IPE state to output state 928 to enable output state 928.This is again with the SO output of the information slave unit that allows to be input to the SI input end.

Through establishing OPE and ID_MATCH, will be from the data slave unit output of page buffer 924.Detailed says that the state of the OPE that is established offers input buffer 906, and this buffer provides this state to the output latch controller 912 that is used to latch this state again.The state of being established that latchs be provided for or the door 926 second the input, or the door 926 output signals to enable output state 928.Establish the output that output that ID_MATCH enables page buffer 924 appears at selector switch 930.The output of selector switch 930 is provided for the output state 928 that is enabled, and the SO output terminal of this buffer slave unit is exported this equipment with data.

Notice that if DAISY_CHAIN is not established, output state 928 is only enabled by OPE.This will allow this equipment in non-daisy chain serial concatenated structure, to use.

Figure 10 is the block diagram of the exemplary series output control logic 1000 in the dual-port equipment.For each port; This serial output control logic 1000 comprises IPE input buffer 1002, SI input buffer 1004, OPE input buffer 1006, input and latch controller 1008, serial-to-parallel register 1010, output latch controller 1012, data register 1014, address register 1016, command interpreter 1018, selector switch 1020, page buffer 1024, logic sum gate 1026, output state 1028 and selector switch 1030, they respectively with above-mentioned IPE input buffer 902, SIP input buffer 904, OPE input buffer 906, input and latch controller 908, to be serial to parallel register 910, output latch controller 912, data register 914, address register 916, command interpreter 918, selector switch 920, page buffer 924, logic sum gate 926, output state 928 identical with selector switch 930.

Figure 11 is the detailed diagram of another embodiment of the serial output control logic 1100 that together uses with technology described herein.Logical one 100 comprises SI input buffer 1104, IPE input buffer 1106, OPE input buffer 1108, SCLK input buffer 1110, logical and (AND)

door

1112 and 1114,

latch

1116,1118,1120 and 1122,

selector switch

1124 and 1130, logic sum gate 1126 and SO output state 1128.

Buffer

1104,1106,1108 and 1110 is traditional LVTTL buffer, is configured to buffer memory respectively and is imported into SI, IPE, OPE and SCLK signal in the equipment.

Be configured to when IPE is established, the information that is input to SI outputed to latch 1116 with door 1112.Latch 1116 is configured to when buffer 1110 provides clock signal (SCLK), latch this information.DATA_OUT representes from being included in the state of the data that Device memory reservoir (not shown) read.Be configured to when OPE is established the state of output DATA_OUT with door 1114.Offer latch 1118 with the output of door 1114, described latch 1118 is configured to when buffer 1110 provides clock signal, latch the state of DATA_OUT.Buffer 1106 is configured to the IPE signal that buffer memory offers equipment.The output of buffer 1106 is latched by latch 1120.Similarly, buffer 1108 is configured to the OPE signal that buffer memory offers equipment.Latch 1122 is configured to latch the state of the OPE that is exported by buffer 1108.Selector switch 1124 and 1130 selects 1 multiplexer for traditional 2, respectively comprises two inputs.The input of selector switch 1124 is selected from selector switch 1124 as output through above-mentioned ID_MATCH signal.An input is provided the latch mode of the DATA_OUT that is kept by latch 1118.When ID_MATCH was established, this input was selected from selector switch 1124 outputs.Another input is provided the latch mode of the SI that is kept by latch 1116.When ID_MATCH was not established, this input was selected from selector switch 1124 outputs.

The input of selector switch 1130 is selected from selector switch 1130 outputs through above-mentioned DAISY_CHAIN signal.An input of selector switch 1130 is provided the latch mode of the IPE that is kept by latch 1120, and another input is connected to logical zero.When DAISY_CHAIN was established, the latch mode of IPE was selected the output as selector switch 1130.Similarly, when DAISY_CHAIN was not established, logical zero was selected from the output of selector switch 1130.

Or door 1126 is traditional logic sum gate, and it is configured to output state 1128 the enable/disable signal is provided.Or door 1126 output that is provided selector switch 1130, and the latch mode of the OPE that is kept by latch 1122.Any of these two outputs can be used to when buffer 1128 provides can signal to enable the output of this buffer.Buffer 1128 is traditional buffer, and it is used for buffer memory output signal SO.As stated, buffer 1128 through or door 1126 output be enabled/forbid.

In operating aspect, when IPE was established, the information that is imported into equipment through SI was provided for latch 1116.Exemplarily, latch 1116 latchs this information when IPE is upwards changed by first of the SCLK after establishing.Similarly, latch 1120 latchs the state of IPE when current SCLK changes.Suppose that ID_MATCH is not established, the output of latch 1116 is provided for buffer 1128 through selector switch 1124.Similarly, the IPE of establishment is sent to latch 1120 from buffer 1106, in latch 1120, also exemplarily when first of SCLK upwards changes, latchs.When supposing that DAISY_CHAIN is established, the latch mode of IPE is provided to the output of selector switch 1130, and be sent to or door 1126 enable signal to be provided to buffer 1128.Then, the latch mode of SI spreads out of as output SO through buffer 1128 slave units.

When DAISY_CHAIN is not established, select to be input to the logical zero of selector switch 1130, from selector switch 1130 output logics 0.This has forbidden that effectively IPE enables buffer 1128.

Exemplarily, when OPE was upwards changed by the next one of the SCLK after establishing, the state of being established of OPE was latched at latch 1122, and the state of DATA_OUT is latched at latch 1118.Suppose that ID_MATCH is established, the latch mode of DATA_OUT is selected the input that buffer 1128 was selected and be added to device 1124.Simultaneously, the state of being established that latchs of the OPE that obtains from latch 1122 through or door 1126 be sent to and enable buffer 1128, this makes the latch mode slave unit output of DATA_OUT as output SO.

The example of equipment property structured flowchart of Figure 12 for disposing and comprise exemplary serial output control logic with the serial daisy chain cascade arrangement.This arrangement comprises three equipment 1210, and it is configured in the daisy chain cascading one as previously mentioned, and formerly the output terminal of equipment and the input end of the next equipment in the daisy chain cascading are coupled.Figure 13 below the transport process reference from an equipment to next equipment of information and data describes.

Figure 13 is the exemplary sequential chart that is used to the input and output correlation timing of the equipment described in Figure 12 of explaining.Specifically, about being sent to the SO output terminal of equipment 1210, this Figure illustrates the operation of the serial output control logic 1100 in each equipment in the information that the SI of each equipment 1210 input end is imported.

With reference to Figure 11,12 and 13, suppose that DAISY_CHAIN is established.When equipment 1210a establishes IPE, be sent to the SO output terminal of equipment 1210a as previously mentioned through the serial output control logic 1100 of equipment in the data of equipment SI input end.Detailed, by each the SCLK rising edge after establishing, data are exemplarily imported among the equipment 1210a by the clock beat at IPE.The information of IPE and state are propagated through logical one 100 as previously mentioned, and leave equipment 1210a at the SO and the IPEQ output terminal of equipment respectively.These outputs are represented with S1 and P1 respectively in the drawings.As previously mentioned, these outputs are provided for SI and the IPE input of equipment 1210b, and through the serial output control logic 1100 of equipment 1210b, and SO and the IPEQ output terminal slave unit 1210b from equipment 1210b exports after a clock period.These outputs are represented with S2 and P2 respectively in the drawings.Similarly; The SO of equipment 1210b and IPEQ output are provided for SI and the IPE input of equipment 1210c respectively; Through the serial output control logic 1100 of equipment 1210c, and the SO of slave unit and IPEQ output terminal slave unit 1210c output respectively after a clock period.These outputs are represented with S3 and P3 respectively in the drawings.

In aforesaid daisy chain cascading was arranged, the signal output delay time (latency) that operates in the daisy chain cascading for SDR can adopt following formula to confirm:

output_latency＝N*clock_cycle_time

Wherein:

" output_latency " is the output delay time of data,

" N " is the amount of equipment during daisy chain cascading is arranged, and

" clock_cycle_time " is time clock period of clock operation.

For example, the clock_cycle_time that supposes the daisy chain cascading described in Figure 12 was 10 nanoseconds.For the data of the SO in equipment 1210c, total output delay time is 3*10 nanosecond or 30 nanoseconds.

In the example of DDR operation, output delay time can determine through following mode:

output_latency＝N*(clock_cycle_time/2)

In the DDR operation, two edges of clock all can be used as the change point of latching a little of input data and output data.Therefore, be the half the of time delay in the SDR operation total time delay.

Notice that in above-mentioned explanation, the information that operation is input in the equipment 1210 for SDR is exported after a clock period, export after operating in half period for DDR.Introducing this type of postpones so that the required time of output state 1128 that starts to be provided.

Figure 14 is the block diagram that is used for the data that the storer of the first equipment 1450a of daisy chain cascading is stored are sent to the logical one 400 of the second equipment 1450b in the daisy chain cascading.Logical one 400 comprises data output register 1402, OPE input buffer 1404, SCLK input buffer 1406; With door 1408, data output latch 1410, OPE status latch 1412; Selector switch 1414, SO output state 1416 and OPEQ output state 1418.

Data output register 1402 is traditional register, and it is configured to store the self-contained data that storer read in equipment 1450.Register 1402 exemplarily is and walks to serial data register that it is transferred to the input end of door 1408 from the memory load data and with data serial with parallel mode.SCLK provides register 1402 to be used for transferring data to the clock signal that door was adopted at 1408 o'clock.As shown in, data register 1402 is configured to preserve and comprises the byte data of a D0 to D7, wherein D0 is the least significant bit (LSB) (LSB) in the byte, and the position D7 be the highest significant position (MSB) in the byte.Register 1402 is with the data of parallel mode from memory load one byte wide.These data begin to shift out and offer door 1408 input bit by bit with serial mode from register from highest significant position.

Buffer

1404 and 1406 is traditional LVTTL buffer, is respectively applied for buffer memory input signal OPE and SCLK.The OPE signal is sent to door 1408 from the output (OPEI) of buffer 1404.The SCLK signal is sent to data output register 1402 from the output of buffer 1406, and latch 1410 and 1412, clock to be provided to these assemblies.

Door 1408 be traditional logical AND gate, and it is configured to arrive latch 1410 when the output (DATA_OUT) of OPE transmission data output register 1402 when establishing.The output of door 1408 is represented as " DBIT ".Latch 1410 and 1412 is traditional latch, and it is configured to latch respectively the state of DBIT and OPE signal.Selector switch 1414 selects 1 multiplexer for traditional 2, and it is controlled by signal ID_MATCH.One of them data is input as the latch mode of DBIT.When ID_MATCH was established, this state was from selector switch 1414 outputs.Another is input as the serial data (SI0) that is transferred to this equipment through the SI of equipment 1450a.When ID_MATCH was not established, this information was exported from selector switch 1414.

Buffer

1416 and 1418 is traditional buffer, and they are configured to the output of difference buffer memory selector switch 1414 and latch 1406.The output of buffer 1416 is left the output of equipment 1450a and buffer 1418 and is left equipment 1450a as OPEQ (OPEQ0) as SO (SO0).

Figure 15 is for being sent to the data of a byte wide the relevant sequential chart of exemplary sequential of equipment 1450b with adopting logical one 400 from the storer that is included in equipment 1450a.Refer to figs. 14 and 15, OPE after input buffer 1404 offers equipment 1450a soon, OPEI is established.OPEI is provided for door 1408 and in latch 1410, is latched at the next rising edge of SCLK with the data of the D7 that enables to be currently located at data output register 1402.In addition, the next rising edge of this SCLK makes data shift right advance data output register, so that the data of D6 move to D7, the data of D5 move to D6, and the rest may be inferred.The output of latch 1410 appears at selector switch 1414, supposes that ID_MATCH is established, and the latch mode of selector switch 1414 output datas is to buffer 1416.As SO0 slave unit 1450a output, SO0 is provided for the SI input (SI1) of the next equipment in the daisy chain cascading to buffer 1416 with this latch mode.Simultaneously, same at OPE by the rising edge of first clock after establishing, the state of OPE is latched in latch 1412.The output of latch 1412 is sent to buffer 1418, and this buffer is exported the latch mode of OPE as OPEQ (OPEQ0) slave unit 1450a, and this OPEQ is provided for the OPE input (OPE1) of the next equipment 1450b in the daisy chain cascading.Bit position D6 repeats said process to D0.

Though show and description the present invention that with reference to preferred embodiment of the present invention is special those skilled in the art should recognize the various variations that on form and details, can carry out, and does not break away from the claimed scope of accompanying claims.

Claims

1. An apparatus having a plurality of serially connected devices, comprising at least a first and a second device,

The first device has:

memory;

a first input configured to receive data; and

a first output configured to output data input in said first input of said first device or data included in said memory;

a first control input configured to receive a first input enable signal to enable said first input of said first device to input data; and

A second control input configured to receive a first output enable signal to enable input of data on said first input of said first device or data included in said memory on said first input of said first device output on the first output,

The second device has:

The first input is configured to input data output from the first device.

2. The device according to claim 1, characterized in that,

the first input is configured to receive address information associated with a storage location in memory; and

The first output is configured to output data contained in a storage location.

3. The arrangement as claimed in claim 1 or 2, characterized in that data is transferred from the first output of the first device to the first input of the second device synchronously with the clock signal.

4. The apparatus of claim 3, wherein the synchronization of the data transfer is performed in response to a clock signal edge.

5 . The device according to claim 4 , wherein the clock signal edge includes any one or all of a rising edge and a falling edge of a clock cycle.

6. The apparatus of claim 1, wherein the data received by the first input of the second device includes device address information, the device address information being associated with the second device.

7. The apparatus of claim 6, wherein the data received by the first input of the second device further comprises command and data information.

8. The apparatus according to claim 1, wherein said first device further comprises:

A first control output configured to output a second input enable signal.

9. The apparatus according to claim 8, wherein said first device further comprises:

A second control output configured to output a second output enable signal.

10. The apparatus according to claim 8, wherein the second input enable signal of the first device is derived from the first input enable signal of the first device.

11. The apparatus according to any one of claims 8-10, wherein the second device further comprises a first control input configured to input a second input enabling signal from the first device.

12. The apparatus according to claim 1, wherein said first device further comprises:

The second output is configured to output a second output enable signal from the first device.

13. The apparatus of claim 12, wherein the second device further comprises a second input coupled to the second output of the first device, configured to receive the second output from the first device so that can signal.

14. The apparatus of claim 1, wherein each of the first device and the second device further comprises a clock input configured to receive a clock signal to synchronize the data from the first device to the first device of the first device. A transfer of the output to the first input of the second device.

15. The apparatus according to claim 1, wherein each of the first device and the second device is further configured to receive a common clock signal at a clock input.

16. The apparatus of claim 1, wherein the first device further comprises a clock output coupled to a clock input of the second device, configured to transmit a clock signal from the first device to the second device .

17. The apparatus of claim 1, wherein the input data comprises serial input data, and the first device and the second device are each configured to:

convert serial input data to parallel data and transfer the parallel data to memory; or

Converts parallel data from memory to serial output data.

18. The apparatus according to claim 14, wherein said first device further comprises:

a data blocking circuit configured to block received data in response to a clock signal; and

A selection circuit configured to select one of the latch data in the data latch circuit and the data from the memory, the selected one is transmitted to the second device.

19. The device according to claim 1, wherein the memory comprises a non-volatile memory.

20. The device according to claim 19, wherein the non-volatile memory comprises a flash memory.

21. A method of accessing memory in a plurality of serially connected devices comprising at least a first device and a second device, the method comprising:

a first input to the first device inputs input data comprising address information associated with a storage location of a memory contained in the first device;

inputting a first input enable signal to a first control input of the first device, enabling input data to be input to the first input of the first device;

accessing data contained in the memory of the first device at the memory location;

inputting a first output enable signal to a second control input of the first device, enabling the accessed data to be output from the first device;

Outputting the accessed data from the first output of the first device and

The accessed data output by the first device is input to a first input of the second device to transfer the accessed data from the first device to the second device.

22. The method according to claim 21, further comprising: inputting a clock signal to the clock inputs of the first device and the second device to synchronize the accessed data from the first output of the first device to the second Transmission of the first input of the device.

23. The method of claim 22, further comprising: transmitting the clock signal received by the first device from the clock output of the first device to the clock input of the second device.

24. The method of claim 21, further comprising:

outputting a second input enable signal from the first control output of the first device; and

Inputting a first input enable signal to the first control input of the second device enables transfer of the accessed data from the first output of the first device to the first input of the second device.

25. The method of claim 24, wherein the second input enable signal of the first device is derived from the first input enable signal of the first device.

26. The method of claim 21, further comprising:

outputting a second output enable signal from the first control output of the first device; and

A second output enable signal is input to the second control input of the second device, enabling the first output of the second device to output the accessed data from the first device.

27. The method of claim 26, wherein the second output enable signal of the first device is derived from the first output enable signal of the first device.

28. A method as claimed in claim 22 or claim 23, characterized in that the synchronization of the data transmission is performed in response to a clock signal edge.