CN101232067B

CN101232067B - Light emitting diode and manufacturing method thereof, integrated light emitting diode, and display

Info

Publication number: CN101232067B
Application number: CN2007101868079A
Authority: CN
Inventors: 大前晓; 冨谷茂隆; 前田勇树; 盐见治典; 网隆明; 宫嶋孝夫; 簗嶋克典; 丹下贵志; 安田淳
Original assignee: Sony Corp
Current assignee: Sony Corp
Priority date: 2005-05-16
Filing date: 2006-05-16
Publication date: 2013-05-15
Anticipated expiration: 2026-05-16
Also published as: CN100438109C; CN1874022A; CN101232067A

Abstract

A method for making a light-emitting diode, which including the steps of: providing a substrate having at least one recessed portion on one main surface and growing a first nitride-based III-V group compound semiconductor layer through a state of making a triangle in section having a bottom surface of the recessed portion as a base thereby burying the recessed portion; laterally growing a second nitride-based III-V group compound semiconductor layer from the first nitride-based III-V group compound semiconductor layer over the substrate; and successively growing a third nitride-based III-V group compound semiconductor layer of a first conduction type, an active layer and a fourth nitride-based III-V group compound semiconductor layer of a second conduction type on the second nitride-basedIII-V group compound semiconductor layer.

Description

Light-emitting diode and manufacture method thereof, integrated light-emitting diode and display

The application is to be on May 16th, 2006 applying date, application number is 200610099847.5, and title is the dividing an application in first to file of " light-emitting diode, integrated light-emitting diode, its method for making, growing method, light source cell unit, back lighting device, display and electronic device ".

Technical field

The present invention relates to the manufacture method of light-emitting diode and light-emitting diode, and relate to the manufacture method of integrated light-emitting diode and integrated light-emitting diode.As mentioned above, the invention still further relates to the method for growing nitride base III-IV compound semiconductor and the electronic device of light source cell unit (cell unit), LED backlight device (backlight), light emitting diode indicator and use light-emitting diode.More particularly, the present invention relates to use the light-emitting diode of nitride based III-V compound semiconductor and device or the device of multiple this light-emitting diode of use.

Background technology

On such as the dissimilar substrate of Sapphire Substrate in the semi-conductive situation of extensional mode growing GaN, high density crystal defect, especially threading dislocation (threading dislocation) that the meeting generation causes due to the very big-difference between lattice constant or thermal coefficient of expansion.

For fear of this situation, up to the present, a kind of dislocation density of utilizing the selectivity lateral growth reduces technology and is widely used.According to this technology, epitaxial growth GaN semiconductor, then remove substrate from crystal growing apparatus on Sapphire Substrate or other substrate.By SiO ₂Form on the GaN semiconductor layer Deng the growth mask of making, then substrate is turned back to crystal growing apparatus, wherein by utilizing growth mask to make the extensional mode growth again of GaN semiconductor.

Although this technique guarantee dislocation density reduce in the GaN semiconductor layer of top, need twice extensional mode growth cycle, and then cause that cost increases.

In order to overcome this problem, a kind of method has been proposed, wherein to process different substrates in advance, with dentation (indented) surface that a kind of patterning is provided, GaN semiconductor extensional mode on the substrate that process is so processed is grown (for example referring to Report of Mitsubishi Cable Industries, LTD., No.98, October, 2001, entitled " Developments of High-power UV LEDUsing A LEPS Technique " and Japanese Patent Laid-Open No.2004-6931 and 2004-6937).This method schematically shows in Figure 36 A to 36C.As shown in Figure 36 A, c Sapphire Substrate 101 is processed, so that a kind of toothed surfaces of patterning to be provided on an one first type surface.Reference marker 101a represents recess, and reference marker 101b represents jut.These recesses 101a and jut 101b along Sapphire Substrate＜1-100 direction extends.Then, for example, through the step of Figure 36 B and 36C, GaN semiconductor 102 is grown on Sapphire Substrate 101.In Figure 36 C, dotted line represents the growth interface in growth course.The characteristics of this method are shown in Figure 36 C, and for example, gap 103 is forming in each recess 101a between Sapphire Substrate 101 and GaN semiconductor layer 102.The crystal defect that Figure 37 has schematically shown on a kind of GaN semiconductor layer 102 growing according to this method distributes.As shown in figure 37, threading dislocation 104 occuring on the direction vertical with the interface of jut 101b upper surface at the GaN semiconductor layer 102 on each jut 101b, forms high defect concentration district 105.On the other hand, on recess 101a and the part between adjacent high defect concentration district 105 be fabricating low-defect-density district 106.

Note, in Figure 36 C, the shape of burying form that is located at the GaN semiconductor layer 102 under the gap 103 that forms in Sapphire Substrate 101 recess 101a is rectangle.This is buried can be also leg-of-mutton in some situation of form.In this case, the GaN semiconductor layer 102 that is buried among recess 101a contacts with the GaN semiconductor layer 102 that begins cross growth from jut 101b, and then forms the gap, buries the situation of form such as rectangle.

For reference, Figure 38 A to 38D show in the situation that the bearing of trend of recess 101a and jut 101b and Sapphire Substrate 101＜1-100 direction intersect at a right angle the fork＜11-20 direction, how GaN semiconductor layer 102 grows.

Figure 39 A has schematically shown the another kind of growing method in the correlation technique to 39F, different from above-mentioned method (for example referring to Japanese Patent Laid-Open No.2003-318441).As shown in Figure 39 A, utilize the Sapphire Substrate that is fabricated to the toothed surfaces with patterning, process Figure 39 B is to the step shown in 39F, at Grown GaN semiconductor layer 102.According to this method, form GaN semiconductor layer 102, but do not form the gap between sapphire surface 101 and GaN semiconductor layer 102.

Summary of the invention

As mentioned above, utilize the growing method in correlation technique shown in Figure 36 A～36C, form gap 103 between Sapphire Substrate 101 and GaN semiconductor layer 102.A problem appears in the result of the test according to the inventor carries out when forming light emitting diode construction by growing GaN semiconductor layer on GaN semiconductor layer 102, namely the luminous efficiency of this light-emitting diode is low.Can be according to following consideration: light-emitting diode be in case work, the light that active layer sends 103 reflections in the gap repeatedly, and then absorb light and cause the deterioration of light extraction efficiency.

On the other hand, utilize the another kind of growing method in correlation technique shown in Figure 39 A～39F, wherein propose: do not form the gap between Sapphire Substrate 101 and GaN semiconductor layer 102.Yet it is difficult that the dislocation density of GaN semiconductor layer 102 is reduced to the degree similar to the dislocation density of growing method in correlation technique shown in Figure 36 A～36C.This has caused the following fact, and when the growing GaN semiconductor layer used light emitting diode construction on by the GaN semiconductor layer 102 with high dislocation density, these GaN semiconductor layers also can increase dislocation density, and then cause the reduction of luminous efficiency.

A kind of light-emitting diode need to be provided, discussed above such as gap formation problem by solving, this light-emitting diode significantly improves on light extraction efficiency, and greatly improved the degree of crystallinity of the nitride based III-V compound semiconductor of light-emitting diode layer, thereby produced very high luminous efficiency, can by a kind of epitaxial growth method, make this light-emitting diode with low cost fabrication, and a kind of method of making the above-mentioned type diode need to be provided.

Also need to provide a kind of method that has the integrated light-emitting diode of above-mentioned advantage and make this integrated light-emitting diode.

In addition, also need to provide a kind of method of growing nitride base III-V compound semiconductor, this nitride based III-V compounds of group is applicable to make this light-emitting diode or integrated light-emitting diode.

In addition, also need to provide multiple high performance device, for example use light source cell unit, LED backlight device, light emitting diode indicator and other electronic device of above-mentioned light-emitting diode.

By description with reference to the accompanying drawings, other characteristics of the present invention will become obvious.

Below, will summarize some embodiment of the present invention.

According to the first embodiment of the present invention, it provides a kind of method of making light-emitting diode, the method comprising the steps of is: be provided at the substrate that has at least one notch part on an one first type surface, by forming on the cross section the bottom surface of the notch part leg-of-mutton state as the base, growth regulation mononitride base III-V compound semiconductor layer, thus notch part buried; On substrate from the first nitride based III-V compound semiconductor layer, the nitride based III-V compound semiconductor of cross growth second layer; The tetrazotization thing base III-V compound semiconductor layer of growing and having the 3rd nitride based III-V compound semiconductor layer, the active layer of the first conduction type and have the second conduction type successively on the second nitride based III-V compound semiconductor layer.

The first nitride based III-V compound semiconductor layer and the second nitride based III-V compound semiconductor layer can be any one types in p, n and i, can be also same conduction type or the conduction type that differs from one another.In addition, dissimilar two or more parts may be combined in the first nitride based III-V compound semiconductor layer and the second nitride based III-V compound semiconductor layer.

Typically, when the first nitride based III-V compound semiconductor layer growth, along with the perpendicular direction of a first type surface of substrate on, dislocation occurs from the interface of substrate notch part bottom surface.When this dislocation arrived near the inclined-plane of the first nitride based III-V compound semiconductor layer or its, wherein to be in Formation cross-section be leg-of-mutton state to this semiconductor layer, its bending with along with the direction of a described major surfaces in parallel away from gable.Equally typically, when forming respectively the first nitride based III-V compound semiconductor layer and the second nitride based III-V compound semiconductor layer, on the bottom surface of substrate notch part, formation has the first concave point of the first width, form the second concave point with second width at substrate notch part opposite side, the second width is larger than the first width.Mode as set forth above, the first nitride based III-V compound semiconductor layer by growth and the second nitride based III-V compound semiconductor layer reflect to form these the first and second concave points.Typically, notch part and jut should alternately be arranged on a surface of substrate.The notch part that forms can extend along a direction in banded mode, perhaps extend upward at first direction and second party in banded mode, it intersects at least mutually, and then the bidimensional pattern is provided, here jut is that triangle, quadrangle, pentagon, hexagon or other angle are clipped or the shape such as the shape of cavetto or circle, ellipse, point.In a preferred embodiment, jut is the hexaplanar shape, and such jut arranges on bidimensional with the honeycomb form, and notch part can be around each jut.This can make it extract light from active layer efficiently on the omnirange of 360 degree.As selection, notch part has the hexaplanar shape, and notch part form with honeycomb on two dimension is arranged, and jut is around each notch part.For example, the notch part of substrate be banded in, this notch part along the first nitride based III-V compound semiconductor layer＜1-100 direction extends.The cross section of notch part can have various shape, and for example rectangle, reversing are trapezoidal etc., and sidewall can comprise tabular surface, but also can comprise the curved surface with small slope, and the bight can be round.From improving the angle of light extraction efficiency, preferably: the cross section of notch part is that reversing is trapezoidal.In this case, angle from the dislocation density minimum that makes the second nitride based III-V compound semiconductor layer, preferably the degree of depth when notch part is d, the bottom width of notch part is Wg, when the angle that consists of between the inclined plane of the first nitride based III-V compound semiconductor layer (cross section is triangle) and first type surface of substrate was α, d, Wg and α were by concerning that 2d 〉=Wg tan α determines.Because α is generally constant, d and Wg are determined by inequality.If d is too large, the initial gas of notch part inside can not be supplied as requested, has therefore stoped from the bottom of notch part to form the first nitride based III-V compound semiconductor layer.On the contrary, if d is too little, the notch part that the first nitride based III-V compound semiconductor layer not only is grown in substrate also is grown in the part of its opposite side (normally jut).From preventing from forming the angle of this structure, usually, select the scope of d to be: 0.5 μ m＜d＜5 μ m, preferred d is in the scope of 1.0 ± 0.2 μ m.Wg is usually in the scope of 0.5～5 μ m, preferably in the scope of 2 ± 0.5 μ m.Although be substantially the upper surface width W t that selects arbitrarily jut, jut is the zone for the nitride based III-V compound semiconductor of cross growth second layer, and therefore larger width can form and have the larger zone that reduces the dislocation density part.The common scope of Wt is 1～1000 μ m, preferably in the scope of 4 ± 2 μ m.

For at the notch part growth regulation mononitride base III-V of substrate compound semiconductor layer, can form amorphous layer (amorphous layer) on the substrate of the opposite side of notch part.Amorphous layer will be growth mask.This be because when growth can not be on amorphous layer nucleation.For example, for decrystallized can carry out the superficial layer of single crystalline substrates Implantation or by any one film growing method on substrate to form amorphous layer.Amorphous layer is made of amorphous silicon (a-Si) film, and for example, amorphous silicon film comprises SiO ₂Film, the SiN film (not only comprises Si ₃N ₄Film comprises that also those pass through the film with different component that plasma chemical vapor deposition (CVD) forms) and SiON (comprise that ratio between O and N changes and refractive index and side view meet the situation of desired design), and amorphous layer dielectric film normally.In addition, can form successively the first amorphous layer, the second amorphous layer and the 3rd amorphous layer on the substrate of each notch part opposite side, the growth mask when it is used as the first nitride based III-V compound semiconductor layer growth.In this case, the second amorphous layer should be that relatively for example the first and the 3rd amorphous layer can be by the etched amorphous layer of selectivity.

After the nitride based III-V compound semiconductor of cross growth second layer, following process may be arranged, wherein, remove the part the part on second nitride based each notch part of III-V compound semiconductor layer, follow the horizontal nitride based III-V compound semiconductor of growth regulation three layer on the second nitride based III-V compound semiconductor layer on the notch part that stays, then grow successively active layer and tetrazotization thing base III-V compound semiconductor layer on the 3rd nitride based III-V compound semiconductor layer.as selection, after the nitride based III-V compound semiconductor of cross growth second layer, another process may be arranged, in this process, can remove the part the part on being positioned at second nitride based each notch part of III-V compound semiconductor layer, follow the horizontal nitride based III-V compound semiconductor of growth regulation five layer on the second nitride based III-V compound semiconductor layer on the notch part that stays, then the nitride based III-V compound semiconductor of growth regulation three layer successively on the 5th nitride based III-V compound semiconductor layer, active layer and tetrazotization thing base III-V compound semiconductor layer.

The 3rd nitride based III-V compound semiconductor layer that forms has the electrode of the first conduction type, and it is electrically connected to or contacts with the 3rd nitride based III-V compound semiconductor layer.Similarly, the electrode that has the second conduction type with the 4th layer of state that is electrically connected under be formed on tetrazotization thing base III-V compound semiconductor layer.

Substrate can be made of multiple material.For by the substrate that consists of with nitride based III-V compound semiconductor layer different kind of material, for example, should be mentioned that especially by sapphire and (have c, a, r face and idle face, off face), SiC (comprising 6H, 4H and 3C), Si, ZnC, ZnO, LiMgO, GaAs, MgAl ₂O ₄Deng the substrate that consists of.Preferably, use the hexagon or the cube substrate that are consisted of by these materials, more preferably the hexagon substrate.As selection, also can use the substrate that is consisted of by nitride based III-V compound semiconductor, for example GaN, InAlGaN, AlN etc.Those are by by the Grown nitride based III-V compound semiconductor layer that consists of with the dissimilar material of nitride based III-V compound semiconductor and form at nitride based III-V compound semiconductor layer the substrate that notch part obtains and also can be used as selection.In addition, can use the substrate of another kind of type, the composition material that wherein forms substrate is different from nitride based III-V compound semiconductor, has one deck on this substrate, the material that consists of this layer on type is different from nitride based III-V compound semiconductor, stacked polycrystalline or amorphous layer that this layer conduct is made of a kind of material at least then with the degree of depth of this layer segment patterning to substrate, have so just formed toothed pattern surperficial.

Attention: if necessary, can remove substrate.

The most usually, the nitride based III-V compound semiconductor layer that is used as the first to the 5th nitride based III-V compound semiconductor layer and active layer is Al by expression formula _xB _yGa _1-x-y-zIn _zAs _uN _1-u-vP _vSemiconductor consist of, wherein 0≤x≤1,0≤y≤1,0≤z≤1,0≤u≤1,0≤v≤1, and 0≤x+y+z＜1 and 0≤u+v＜1.Preferably, the expression formula of mentioning is Al _xB _yGa _1-x-y-zIn _zN, wherein 0≤x≤1,0≤y≤1,0≤z≤1, and 0≤x+y+z＜1.More preferably, semiconductor layer is by Al _xGa _1-x-zIn _zN consists of, wherein 0≤x≤1,0≤z≤1.Instantiation comprises GaN, InN, AlN, AlGaN, InGaN, AlGaInN etc.With the first nitride based III-V compound semiconductor layer of being buried in the substrate notch part preferably by GaN, In _xGa _1-xN, Al _xGa _1-xN, Al _xIn _yGa _1-x-yN consists of, at In _xGa _1-xIn N, 0＜x＜0.5; At Al _xGa _1-xIn N, 0＜x＜0.5; At Al _xIn _yGa _1-x-yIn N, 0＜x＜0.5,0＜y＜0.2.The first conduction type can be N-shaped or p-type, and correspondingly, the second conduction type can be p-type or N-shaped.

Consist of the nitride based III-V compound semiconductor layer of the first to the 5th nitride based III-V compound semiconductor layer and active layer in order to grow, for example, can use shallow lake, metal-organic chemical gas phase shallow lake method (MOCVD), hydride or halide vapour phase epitaxy method (HVPE), molecular beam epitaxy (MBE) and other many epitaxys.

According to second embodiment of the present invention, it provides a kind of light-emitting diode, and this light-emitting diode comprises: the substrate that has at least one notch part on an one first type surface; Be grown on substrate and do not form the 6th nitride based III-V compound semiconductor layer in gap in notch part; And the 3rd nitride based III-V compound semiconductor layer, the active layer with first conduction type of growing on the 6th nitride based III-V compound semiconductor layer and tetrazotization thing base III-V compound semiconductor layer with second conduction type.In this light-emitting diode, in the 6th nitride based III-V compound semiconductor layer, along with the perpendicular direction of a first type surface on, from and the notch part bottom surface between the interface dislocation occurs, this dislocation can arrive or approach with the leg-of-mutton inclined plane as the base, notch part bottom surface, and along crooked with the direction of a major surfaces in parallel.

According to the 3rd embodiment of the present invention, it provides a kind of light-emitting diode, and this light-emitting diode comprises: the substrate that has at least one notch part on a first type surface; Be grown on substrate and do not form the 6th nitride based III-V compound semiconductor layer in gap in notch part; And the 3rd nitride based III-V compound semiconductor layer, the active layer with first conduction type of growing on the 6th nitride based III-V compound semiconductor layer and tetrazotization thing base III-V compound semiconductor layer with second conduction type.In this light-emitting diode, substrate can form the first concave point (pit) with first width on the bottom surface of notch part, and forms the second concave point with second width at the opposite side of notch part, and the second width is larger than the first width.

According to second, third and the 5th, the 6th, the 8th to the 17 embodiment that occurs later of the present invention, the 6th nitride based III-V compound semiconductor layer is corresponding with the first nitride based III-V compound semiconductor layer and the second nitride based III-V compound semiconductor layer in the first embodiment respectively.

Be noted that except in indivedual embodiment in addition statement or need in addition, all explanations relevant to the first embodiment are set up equally for second, third embodiment of the present invention and the 4th to the 18 embodiment that occurs later.

A fourth embodiment in accordance with the invention, a kind of method of manufacturing integration light-emitting diode is provided, integrated a plurality of light-emitting diodes in this integrated light-emitting diode, the method comprises the following steps: by forming on the cross section the bottom surface of the notch part leg-of-mutton state as the base, growth regulation mononitride base III-V compound semiconductor layer at least one notch part on a first type surface of substrate, thus notch part buried; On substrate from the first nitride based III-V compound semiconductor layer, the nitride based III-V compound semiconductor of cross growth second layer; Grow successively on the second nitride based III-V compound semiconductor layer and have the 3rd nitride based III-V compound semiconductor layer, active layer, the tetrazotization thing base III-V compound semiconductor layer of the first conduction type.

According to a fifth embodiment of the invention, provide a kind of integrated light-emitting diode, wherein, integrated a plurality of light-emitting diodes in integrated light-emitting diode, its at least one light-emitting diode comprises: the substrate that has at least one notch part on a first type surface; Be grown on substrate and do not form the 6th nitride based III-V compound semiconductor layer in gap in notch part; And the 3rd nitride based III-V compound semiconductor layer, the active layer with first conduction type that form on the 6th nitride based III-V compound semiconductor layer and tetrazotization thing base III-V compound semiconductor layer with second conduction type.In this light-emitting diode, in the 6th nitride based III-V compound semiconductor layer, along with the perpendicular direction of first type surface on, from and the notch part bottom surface between the interface dislocation occurs, this dislocation arrives or approaches with the leg-of-mutton inclined plane as the base, notch part bottom surface, and to along crooked with the direction of a major surfaces in parallel.

According to a sixth embodiment of the invention, provide a kind of integrated light-emitting diode, wherein, integrated a plurality of light-emitting diodes in integrated light-emitting diode, at least one light-emitting diode comprises: the substrate that has at least one notch part on a first type surface; Be grown on substrate and do not form the 6th nitride based III-V compound semiconductor layer in gap in notch part; And the 3rd nitride based III-V compound semiconductor layer, the active layer with first conduction type of growing on the 6th nitride based III-V compound semiconductor layer and tetrazotization thing base III-V compound semiconductor layer with second conduction type.In this light-emitting diode, on the bottom surface of substrate notch part, can form the first concave point with first width, form the second concave point with second width at substrate notch part opposite side, the second width is larger than the first width.

In the 4th to the 6th embodiment of the present invention, integrated light-emitting diode can be applied in a plurality of fields.Typical purposes is LED backlight device, for example liquid crystal display, light emitting diode lighting equipment, light emitting diode indicator etc.Integrated light-emitting diode is arbitrarily about arrangement architecture and the mode of diode.For example, light-emitting diode can be arranged in the mode of two-dimensional array, and perhaps banded light-emitting diode is arranged with delegation or multirow.The form of integrated light-emitting diode comprises a kind of like this form, wherein according to a kind of so-called semiconductor fabrication, the wafer with semiconductor layers stack stack structure is carried out stripping and slicing and process (block processed), with each light-emitting diode that provides circuit pattern and integrated and a plurality of meticulous (microfinely) to arrange, perhaps comprise such form, each light-emitting diode that wherein will be divided in advance microplate (microchipped) on circuit pattern carries out a plurality of arrangements subtly.In addition, these light-emitting diodes can drive or driving simultaneously.Selectively, can carry out drive to one group of light-emitting diode piecemeal in random setting area (namely the zone drives).

According to a seventh embodiment of the invention, a kind of method of growing nitride base III-V compound semiconductor layer is provided, the method comprising the steps of: be provided at the substrate that has at least one notch part on an one first type surface, and by forming on the cross section the bottom surface of the notch part leg-of-mutton state as the base, growth regulation mononitride base III-V compound semiconductor layer, thus notch part buried; And on substrate from the first nitride based III-V compound semiconductor layer, the nitride based III-V compound semiconductor of cross growth second layer.

The growing method of this nitride based III-V compound semiconductor layer not only can be applied in the manufacturing of light-emitting diode and integrated light-emitting diode, but also can be applied in the manufacturing of various semiconductor device.

According to the eighth embodiment of the present invention, a kind of substrate for growing nitride base III-V compound semiconductor is provided, it comprises: the substrate that has at least one notch part on an one first type surface; And be grown on substrate and do not form the 6th nitride based III-V compound semiconductor layer in gap on notch part.On this substrate, in the 6th nitride based III-V compound semiconductor layer, along with the perpendicular direction of first type surface on, from and the notch part bottom surface between the interface dislocation occurs, this dislocation arrives or approaches with the leg-of-mutton inclined plane as the base, notch part bottom surface, and along crooked with the direction of a described major surfaces in parallel.

According to the ninth embodiment of the present invention, a kind of substrate for growing nitride base III-V compound semiconductor is provided, it comprises: the substrate that has at least one notch part on an one first type surface; And be grown on substrate and do not form the 6th nitride based III-V compound semiconductor layer in gap in notch part.Substrate can form the first concave point with first width on the bottom surface of notch part, can form the second concave point with second width at the notch part opposite side, and the second width is larger than the first width.

According to the tenth embodiment of the present invention, a kind of light source cell unit is provided, it comprises printed circuit board (PCB) and a plurality of unit (cell) that are formed on printed circuit board (PCB), and each unit comprises at least one red light emitting diodes, at least one green LED, at least one blue LED.In light source cell unit, at least one diode in red light emitting diodes, green LED, blue LED can comprise: the substrate that has at least one notch part on an one first type surface; Be grown on substrate and do not form the 6th nitride based III-V compound semiconductor layer in gap in notch part; And the 3rd nitride based III-V compound semiconductor layer, the active layer with first conduction type of growing on the 6th nitride based III-V compound semiconductor layer and tetrazotization thing base III-V compound semiconductor layer with second conduction type.In the 6th nitride based III-V compound semiconductor layer, along with the perpendicular direction of a described first type surface on, from and the notch part bottom surface between the interface dislocation occurs, this dislocation arrives or approaches with the leg-of-mutton inclined plane as the base, notch part bottom surface, and along crooked with the direction of a major surfaces in parallel.

According to the 11st embodiment of the present invention, a kind of LED backlight device is provided, it comprises a plurality of red light emitting diodes that are arranged in pattern, a plurality of green LED and a plurality of blue LED.In light-emitting diode, at least one diode in red light emitting diodes, green LED, blue LED comprises: the substrate that has at least one notch part on an one first type surface; Be grown on substrate and do not form the 6th nitride based III-V compound semiconductor layer in gap in notch part; And the 3rd nitride based III-V compound semiconductor layer, the active layer with first conduction type that form on the 6th nitride based III-V compound semiconductor layer and tetrazotization thing base III-V compound semiconductor layer with second conduction type.In the 6th nitride based III-V compound semiconductor layer, along with the perpendicular direction of a described first type surface on, from and the notch part bottom surface between the interface dislocation occurs, this dislocation arrives or approaches with the leg-of-mutton inclined plane as the base, notch part bottom surface, and along crooked with the direction of a described major surfaces in parallel.

According to the 12nd embodiment of the present invention, a kind of LED backlight device is provided, it comprises red light emitting diodes, green LED and the blue LED that is arranged in pattern, each diode is all a plurality of on number, wherein, at least one diode in red light emitting diodes, green LED, blue LED comprises: the substrate that has at least one notch part on an one first type surface; Be grown on substrate and do not form the 6th nitride based III-V compound semiconductor layer in gap in notch part; And the 3rd nitride based III-V compound semiconductor layer, the active layer with first conduction type that form on the 6th nitride based III-V compound semiconductor layer and tetrazotization thing base III-V compound semiconductor layer with second conduction type, wherein, substrate forms the first concave point with first width on the bottom surface of notch part, form the second concave point with second width at the notch part opposite side, the second width is larger than the first width.

according to the 13rd embodiment of the present invention, a kind of light emitting diode lighting equipment is provided, it comprises red light emitting diodes, green LED and the blue LED that is arranged in pattern, every kind of diode is all a plurality of on number, wherein, at least one diode in red light emitting diodes, green LED, blue LED comprises: the substrate that has at least one notch part on an one first type surface, be grown on substrate and do not form the 6th nitride based III-V compound semiconductor layer in gap in notch part, and the 3rd nitride based III-V compound semiconductor layer with first conduction type that forms on the 6th nitride based III-V compound semiconductor layer, active layer and the tetrazotization thing base III-V compound semiconductor layer with second conduction type, wherein, in the 6th nitride based III-V compound semiconductor layer, along with the perpendicular direction of first type surface on, from and the notch part bottom surface between the interface dislocation occurs, this dislocation arrives or approaches with the leg-of-mutton inclined plane as the base, notch part bottom surface, and along crooked with the direction of a major surfaces in parallel.

According to the 14th embodiment of the present invention, a kind of light emitting diode lighting equipment is provided, it comprises red light emitting diodes, green LED and the blue LED that is arranged in pattern, each diode is all a plurality of on number, wherein, at least one diode in red light emitting diodes, green LED, blue LED comprises: the substrate that has at least one notch part on an one first type surface; Be grown on substrate and do not form the 6th nitride based III-V compound semiconductor layer in gap in notch part; And the 3rd nitride based III-V compound semiconductor layer, the active layer with first conduction type that form on the 6th nitride based III-V compound semiconductor layer and tetrazotization thing base III-V compound semiconductor layer with second conduction type, wherein substrate forms the first concave point with first width on the bottom surface of notch part, form the second concave point with second width at the notch part opposite side, the second width is larger than the first width.

according to the 15th embodiment of the present invention, a kind of light emitting diode indicator is provided, it comprises red light emitting diodes, green LED and the blue LED that is arranged in pattern, each diode is all a plurality of on number, wherein, at least one diode in red light emitting diodes, green LED, blue LED comprises: the substrate that has at least one notch part on an one first type surface, be grown on substrate and do not form the 6th nitride based III-V compound semiconductor layer in gap in notch part, and the 3rd nitride based III-V compound semiconductor layer with first conduction type that forms on the 6th nitride based III-V compound semiconductor layer, active layer and the tetrazotization thing base III-V compound semiconductor layer with second conduction type, wherein in the 6th nitride based III-V compound semiconductor layer, along with the perpendicular direction of a described first type surface on, from and the notch part bottom surface between the interface dislocation occurs, this dislocation arrives or approaches with the leg-of-mutton inclined plane as the base, notch part bottom surface, and along crooked with the direction of a described major surfaces in parallel.

According to the 16th embodiment of the present invention, a kind of light emitting diode indicator is provided, it comprises red light emitting diodes, green LED and the blue LED that is arranged in pattern, each diode is all a plurality of on number, wherein, at least one diode in red light emitting diodes, green LED, blue LED comprises: the substrate that has at least one notch part on an one first type surface; Be grown on substrate and do not form the 6th nitride based III-V compound semiconductor layer in gap in notch part; And the 3rd nitride based III-V compound semiconductor layer, the active layer with first conduction type that form on the 6th nitride based III-V compound semiconductor layer and tetrazotization thing base III-V compound semiconductor layer with second conduction type, wherein, substrate forms the first concave point with first width on the bottom surface of notch part, form the second concave point with second width at the notch part opposite side, the second width is larger than the first width.

In the tenth to the 16 embodiment according to the present invention, for example, red light emitting diodes can be to use the semi-conductive light-emitting diode of AlGaInP.

according to the 17th embodiment of the present invention, a kind of electronic equipment that comprises at least one light-emitting diode is provided, this at least one light-emitting diode comprises: the substrate that has at least one notch part on an one first type surface, be grown on substrate and do not form the 6th nitride based III-V compound semiconductor layer in gap in notch part, and the 3rd nitride based III-V compound semiconductor layer with first conduction type that forms on the 6th nitride based III-V compound semiconductor layer, active layer and the tetrazotization thing base III-V compound semiconductor layer with second conduction type, wherein in the 6th nitride based III-V compound semiconductor layer, along with the perpendicular direction of a described first type surface on, from and the notch part bottom surface between the interface dislocation occurs, this dislocation arrives or approaches with the leg-of-mutton inclined plane as the base, notch part bottom surface, and along crooked with the direction of a described major surfaces in parallel.

According to the 18th embodiment of the present invention, a kind of electronic equipment that comprises at least one light-emitting diode is provided, this at least one light-emitting diode comprises: the substrate that has at least one notch part on an one first type surface; Be grown on substrate and do not form the 6th nitride based III-V compound semiconductor layer in gap in notch part; And the 3rd nitride based III-V compound semiconductor layer, the active layer with first conduction type that form on the 6th nitride based III-V compound semiconductor layer and tetrazotization thing base III-V compound semiconductor layer with second conduction type, wherein, substrate forms the first concave point with first width on the bottom surface of notch part, form the second concave point with second width at the notch part opposite side, the second width is larger than the first width.

In the of the present invention the 17 and the 18 embodiment, except LED backlight device (such as the back lighting device that is used for liquid crystal display etc.), light emitting diode lighting equipment, light emitting diode indicator etc., electronic equipment also comprises and uses light-emitting diode as the projection of light source instrument, rear-projection TV, grating light valve (GLV) etc.Usually, electronic equipment can be any type substantially, is used for demonstration, illumination, optical communication, light transmission etc. as long as electronic equipment has a light-emitting diode at least, and it can comprise portable and desk-top.Except above-described example, instantiation also comprises mobile phone, mobile device, robot, PC, mobile unit, various domestic electronic appliances, light-emitting diode optical communication equipment, light-emitting diode optical transmission device etc.Electronic equipment also comprises two kinds or more eurypalynous light emitting diode combined, on wave-length coverage, light-emitting diode can send different wave length, and wave-length coverage comprises far infrared wavelength scope, infrared wavelength range, red wavelength range, yellow wavelengths scope, green wavelength scope, blue wavelength region, purple wave-length coverage, UV wavelength range etc.Especially, LED device has two or more light-emitting diodes that can send the different wavelength range visible light, and the wave-length coverage of visible light is selected in red wavelength range, yellow wavelengths scope, green wavelength scope, blue wavelength region and purple wave-length coverage.Two or more light that these light-emitting diodes are sent are mixed to get natural daylight or white light.In addition, as light source, use can be luminous light-emitting diode, this light wavelength is at least a wave-length coverage of blue wavelength region, purple wave-length coverage, UV wavelength range, the irradiation fluorophor that this light-emitting diode sends, mixed natural daylight or the white light of obtaining of the light that obtains after phosphor excitation.

According to the 19th embodiment of the present invention, a kind of method of making electronic device is provided, the method comprising the steps of: be provided at the substrate that has at least one notch part on a first type surface; By forming on the cross section the bottom surface of the notch part leg-of-mutton state as the base, growth regulation one deck on notch part, and bury notch part; And on substrate from the first nitride-based compound semiconductor layer, the cross growth second layer.

According to the 20th embodiment of the present invention, a kind of electronic device is provided, this electronic device comprises: the substrate that has at least one notch part on a first type surface; Be grown on substrate and do not form the 3rd layer of gap in notch part, wherein, in the 3rd layer, along with the perpendicular direction of a described first type surface on, from and the notch part bottom surface between the interface dislocation occurs, this dislocation arrives or approaches with the leg-of-mutton inclined plane as the base, notch part bottom surface, and along crooked with the direction of a described major surfaces in parallel.

In the of the present invention the 19 and the 20 embodiment, except nitride based III-V compound semiconductor, first to the 3rd layer can be to have other type semiconductor of wurtzite (wurtzit) structure or be more generally hexagonal (hexagonalcrystal) structures such as ZnO, α-ZnS, α-CdS, α-CdSe and multiple semiconductor with other crystal structure.Use these semi-conductive semiconductor device to comprise luminescent device, light receiving element; Luminescent device for example has common light-emitting diode, middle sub-band transition (quanta cascade, quantum cascade) light-emitting diode, general semiconductor laser, middle sub-band transition (quanta cascade) semiconductor laser etc., light receiving element for example has photodiode, transducer, solar cell, electron transition device, typical electron transition device is transistor, this transistor comprise such as High Electron Mobility Transistor field-effect transistor (FET) and such as the bipolar transistor of heterojunction bipolar transistor (HBT).Can these devices be arranged on same substrate or chip single or a plurality ofly.If necessary, these devices can be arranged in can drive mode.On same substrate, use integrated light-emitting device and electron transition device can consist of optoelectronic integrated circuit (OEIC).As required, can form optical link.In addition, when using at least one luminescent device (light-emitting diode or semiconductor laser) to allow the light emission, can throw light on communication or optical communication.In this case, can use a plurality of light beams of different wavelength range throw light on communication (lighting communication) or optical communication.

Except these semiconductor device (such as luminescent device, light receiving element, electron transition device etc.), electronic device comprises piezoelectric device, thermoelectric device, optical device (such as the second harmonic generator that uses nonlinear optical crystal, comprise the dielectric device of ferro-electric device) and superconductive device etc.In this connection, the material of first to the 3rd layer can comprise multiple semiconductor recited above, particularly piezoelectric device and thermoelectric device, optical device, dielectric device and superconductive device, and can use multiple material such as the oxide with hexagonal crystallographic texture.

When the electronic device that utilizes these to comprise light-emitting diode or semiconductor laser, can provide LED backlight device, light emitting diode illuminator spare, light emitting diode indicator, use light-emitting diode or semiconductor laser as the projection of light source instrument or rear-projection TV with such as the electronic equipment of grating light valve.

For the of the present invention the 19 and the 20 embodiment, be applicable to too the 19 and the 20 embodiment as these application in the first to the 18 embodiment.

As indicated above, according to embodiments of the invention, from the bottom of substrate notch part, beginning growth regulation mononitride base III-V compound semiconductor layer.At growing period, by forming on the cross section the bottom surface of the notch part leg-of-mutton state as the base, formed the first nitride based III-V compound semiconductor layer, and then buried notch part, this layer does not form the gap at notch part.After this, horizontal growth regulation diammine base III-V compound semiconductor layer from the first nitride based III-V compound semiconductor layer.In this stage, in the first nitride based III-V compound semiconductor layer, along with the perpendicular direction of a first type surface of substrate on, from and substrate notch part bottom surface between the interface dislocation occurs.This dislocation arrives the inclined plane of the first nitride based III-V compound semiconductor layer or near the inclined plane of the first nitride based III-V compound semiconductor layer, in this case, when the second nitride based III-V compound semiconductor layer growth, the dislocation edge is crooked with the direction of a described major surfaces in parallel of substrate.When the second nitride based III-V compound semiconductor layer growth when the gratifying thickness, with the dislocation of the described major surfaces in parallel of substrate above part become a very little zone of dislocation density.According to the method, can utilize growth technology, growth the first to tetrazotization thing base III-V compound semiconductor layer.

More generally say, when the first nitride based III-V compound semiconductor layer during as just the second layer, also can be obtained similar result as just ground floor, the second nitride based III-V compound semiconductor layer.

According to embodiments of the invention, do not form space or gap between the first nitride based III-V compound semiconductor layer and the second nitride based III-V compound semiconductor layer and substrate, light extraction efficiency can be improved significantly.Because the degree of crystallinity of the second nitride based III-V compound semiconductor layer becomes well, so can significantly improve the degree of crystallinity of the 3rd nitride based III-V compound semiconductor layer, active layer and the tetrazotization thing base III-V compound semiconductor layer of growing on the second layer.At last, obtain having the very high light-emitting diode of light emission effciency.In addition, because light-emitting diode can be formed by an extension, so low cost of manufacture.Therefore, can realize the manufacturing of high-performance light sources cell arrangement, LED backlight device, light emitting diode lighting equipment and light emitting diode indicator and the various types of electronic equipments that make the high light-emitting diode of use light emission effciency.

More generally, when the first nitride based III-V compound semiconductor layer during as the second layer, can be obtained similar result as ground floor, the second nitride based III-V compound semiconductor layer.

Be described below by example and in conjunction with the accompanying drawing that the preferred embodiment of the present invention is described, will become apparent with its its feature, advantage above the present invention.

Description of drawings

Figure 1A is respectively that the sectional view of the method for GaN light-emitting diode is made in explanation according to first embodiment of the invention to Fig. 1 F.

Fig. 2 is plane graph, and it has shown in making the method for GaN light-emitting diode according to first embodiment of the invention, forms the example of the flat shape of notch part and jut on Sapphire Substrate.

Fig. 3 is schematic diagram, and it has shown how to extract light from the GaN light-emitting diode that obtains according to the first embodiment of the present invention.

Fig. 4 is schematic diagram, and it has shown Sapphire Substrate, and this Sapphire Substrate is used for making the method for GaN light-emitting diode according to first embodiment of the invention.

Fig. 5 is schematic diagram, and it has shown in making the method for GaN light-emitting diode according to first embodiment of the invention, how at Grown on Sapphire Substrates GaN layer.

Fig. 6 is schematic diagram, and it has shown in making the method for GaN light-emitting diode according to first embodiment of the invention, the distribution of crystal defect in the GaN of Grown on Sapphire Substrates.

Fig. 7 is photo, and it has shown in making the method for GaN light-emitting diode according to first embodiment of the invention, at the planar cathode luminescent image of the GaN of Grown on Sapphire Substrates layer.

Fig. 8 A and 8B are schematic diagrames, and it has illustrated respectively in making the method for GaN light-emitting diode according to first embodiment of the invention, has carried out by the GaN layer to Grown on Sapphire Substrates the dislocation behavior that tem observation obtains.

Fig. 9 is schematic diagram, and it has illustrated in making the method for GaN light-emitting diode according to first embodiment of the invention, at the estimated result of the GaN of Grown on Sapphire Substrates layer Dislocations density.

Figure 10 A and 10B are microphotos, and it has shown respectively in making the method for GaN light-emitting diode according to first embodiment of the invention, are grown in the cross section tem observation result of the GaN bed boundary on Sapphire Substrate.

Figure 11 is schematic diagram, and it has illustrated in making the method for GaN light-emitting diode according to first embodiment of the invention, the formation of the concave point when Grown on Sapphire Substrates GaN layer.

Figure 12 A is microphoto to 12C, and it has shown respectively in making the method for GaN light-emitting diode according to first embodiment of the invention, is grown in the cross section tem observation result of the GaN bed boundary on Sapphire Substrate.

Figure 13 A and 13B are schematic diagrames, and it has illustrated respectively the thickness distribution of GaN layer in Figure 12 B and 12C.

Figure 14 is schematic diagram, and it has shown the tracking simulation result of making the GaN light-emitting diode according to first embodiment of the invention.

Figure 15 is schematic diagram, and it has illustrated and has been used for optimal conditions that the light extraction efficiency according to the GaN light-emitting diode of first embodiment of the invention manufacturing is improved.

Figure 16 is curve chart, and it has shown in the GaN light-emitting diode of making according to first embodiment of the invention, the simulation result of the Area Ratio of the Sapphire Substrate inclined surface of use.

Figure 17 is curve chart, and it has shown in making the method for GaN light-emitting diode according to first embodiment of the invention, the simulation result of the Area Ratio of the Sapphire Substrate inclined surface of use.

Figure 18 is curve chart, and it has shown in making the method for GaN light-emitting diode according to first embodiment of the invention, the simulation result of the Area Ratio of the inclined surface of the Sapphire Substrate of use.

Figure 19 is schematic diagram, and it has illustrated the surface of the active layer of the GaN light-emitting diode of making according to first embodiment of the invention.

Figure 20 is schematic diagram, and it has illustrated the surface of the active layer of the GaN light-emitting diode of making according to first embodiment of the invention.

Figure 21 A is sectional view to 21E, and it has illustrated respectively the method for making the GaN light-emitting diode according to second embodiment of the invention.

Figure 22 A is sectional view to 22G, and it has illustrated respectively the method for making the GaN light-emitting diode according to third embodiment of the invention.

Figure 23 A is sectional view to 23F, and it has illustrated respectively the method for making the GaN light-emitting diode according to fourth embodiment of the invention.

Figure 24 A is sectional view to 24G, and it has illustrated respectively the method for making the GaN light-emitting diode according to fifth embodiment of the invention.

Figure 25 A is sectional view to 25G, and it has illustrated respectively the method for making the GaN light-emitting diode according to sixth embodiment of the invention.

Figure 26 A is sectional view to 26B, and it has illustrated respectively the method for making the GaN light-emitting diode according to seventh embodiment of the invention.

Figure 27 A is sectional view to 27J, and it has illustrated respectively the method for making the GaN light-emitting diode according to eighth embodiment of the invention.

Figure 28 A is sectional view to 28C, and it has illustrated respectively the method for making the GaN LED backlight according to ninth embodiment of the invention.

Figure 29 A and 29B are perspective views, and it has illustrated respectively the method according to ninth embodiment of the invention.

Figure 30 is perspective view, and it has illustrated the method for making LED backlight device according to tenth embodiment of the invention.

Figure 31 is perspective view, and it has illustrated the method according to eleventh embodiment of the invention manufacturing integration light-emitting diode.

Figure 32 is sectional view, and it has shown integrated light-emitting diode, and this integrated light-emitting diode is according to the eleventh embodiment of the invention manufacturing, and is arranged on pedestal (submount).

Figure 33 A and 33B are respectively the enlarged drawings that shows according to the unit of the plane graph of the light source cell unit of twelveth embodiment of the invention and light source cell unit.

Figure 34 A and 34B are respectively that demonstration is according to the plane graph of the instantiation of the light source cell unit of twelveth embodiment of the invention.

Figure 35 is plane graph, and it has shown an example, and this example is the arrangement according to another unit of the light source cell unit of twelveth embodiment of the invention.

Figure 36 A is respectively that explanation is at the sectional view of the correlation technique of dentation Grown GaN semiconductor layer to 36C.

Figure 37 is sectional view, and it has illustrated the problem of correlation technique shown in Figure 36.

Figure 38 A is the sectional view that illustrates respectively at another correlation technique of dentation Grown GaN semiconductor layer to 38D.

Figure 39 A is the sectional view that illustrates respectively at another correlation technique of dentation Grown GaN Semiconductor substrate to 39F.

Embodiment

The hereinafter with reference accompanying drawing is described embodiments of the present invention.Note, in accompanying drawing, identical Reference numeral represents identical parts.

Figure 1A according to step order, shows the method according to the manufacturing GaN light-emitting diode of first embodiment of the invention to 1F.

In the first embodiment, as shown in Figure 1A, provide one to have the Sapphire Substrate 11 of toothed pattern on an one first type surface.Reference marker 11a represents notch part or groove, and reference marker 11b represents jut or projection.In this case, notch part 11a has the inverted trapezoidal cross section.For example, the first type surface of Sapphire Substrate 11 is c-faces, and notch part 11a is along Sapphire Substrate 11＜1-100〉the direction bar shape of extending.Although the flat shape of notch part 11a and jut 11b can be respectively the shape of enumerating respectively hereinbefore, preferred example is shown in Figure 2.In this case, as shown in Figure 2, each jut 11b is hexagon on the plane, and these juts are shaped as two-dimensional shapes, forms cellular.Notch part 11a forms around each projection 11b.Hexagon jut 11b has certain distance between the hexagon relative edge, 3.8 to 4.2 μ m for example, preferred 4 μ m.Distance between adjacent hexagons projection 11b is set, and is for example 1.3 to 1.7 μ m, preferred 1.5 μ m, but be not restrictive.Typically, the direction of dotted line (the namely direction of the center connecting line of the most close jut 11b) is parallel with the m axle of the GaN layer that hereinafter will describe.The surperficial sawtooth of Sapphire Substrate 11 can be according to many methods realizations, and these methods comprise reactive ion etching (RIE) method, the technology of dusting, sandblast technology etc.The size of these notch parts 11a and jut 11b will be described in more detail below.

Then, utilize the surface of cleaning Sapphire Substrate 11 as the method for thermal cleaning (thermal cleaning), then on Sapphire Substrate 11 according to known procedure in growth temperature for example approximately under 550 ℃, growing GaN resilient coating (not shown) for example.Then, utilize a kind of for example the be method of MOCVD, extensional mode growing GaN.In this stage, as shown in Figure 1B, this growth is from the beginning of the bottom surface of notch part 11a, GaN layer 12 is according to this sample loading mode growth, take Formation cross-section as isosceles triangle, its bottom is as the base, and the face that tilts with respect to Sapphire Substrate 11 first type surfaces is as prism.For example, GaN layer 12 edge＜1-100〉the direction extension, the face of its inclined side or surface are (1-101) face.This GaN layer 12 can be undoped, also can be doped with N-shaped or p-type impurity.The growth conditions of GaN layer 12 will be described below.

Then, continue the growth of GaN layer 12, remain simultaneously the surface direction on inclined plane, notch part 11a is wherein all filled, as shown in Fig. 1 C.In Fig. 1 C, dotted line represents the growth interface (Hereinafter the same) in growth course.

Then, when growth continues, when setting simultaneously cross growth and be main condition, when GaN layer 12 distributes on jut 11b, its thickness increases, as shown in Fig. 1 D.At last, the GaN layer 12 that grows out from adjacent recesses part 11a is in contact with one another above jut 11b.

Afterwards, as shown in Fig. 1 E, 12 cross growth of GaN layer make the surface formation of GaN layer 12 and the flat surfaces of the major surfaces in parallel of Sapphire Substrate 11.The GaN layer 12 of growth has low-down dislocation density on notch part 11a like this.

Below, as shown in Fig. 1 F, for example N-shaped GaInN layer 13, N-shaped GaN layer 14, N-shaped GaInN layer 15, active layer 16, p-type GaInN layer 17, p-type AlInN layer 18, p-type GaN layer 19 and p-type GaInN layer 20 extensional mode growth on GaN layer 12 successively.Active layer 16 has, for example GaInN Quito layer quantum well (MQW) structure (for example GaInN quantum well layer and GaN barrier layer are alternately laminated).The In component of active layer 16 is to select according to the emission wavelength of light-emitting diode, for example during the 405nm emission wavelength during near (up to) 11%, 450nm wavelength during near 18%, 520nm wavelength near 24%.

Afterwards, in order to activate the p-type impurity in p-type GaInN layer 17, p-type AlInN layer 18, p-type GaN layer 19 and p-type GaInN layer 20, heat-treat in mixed-gas atmosphere, this mist is for example the N at 550 to 750 ℃ (for example 650 ℃) or 580 to 620 ℃ of (for example 600 ℃) temperature ₂And O ₂(component is for example 99% N ₂With 1% O ₂).At O ₂With N ₂During mixing, this activation more easily occurs.Heat treated time range, for example, from five minutes to two hours, perhaps 40 minutes to two hours.Usually, this time range is 10 to 60 minutes.The reason that heat treated temperature is suppressed to relatively low value is during heating treatment deteriorated in order to prevent active layer 16.

The parent material that is used for the growing GaN semiconductor layer comprises, for example, and as the triethyl-gallium ((C of Ga material ₂H ₅) ₃Ga, TEG) or trimethyl gallium ((CH ₃) ₃Ga, TMG), as the trimethyl aluminium ((CH of Al material ₃) ₃Al, TMA), as the trimethyl indium ((CH of In material ₃) ₃In, TMI) and as the ammonium (NH of N material ₃).Dopant comprises, for example as the silane (SiH of N-shaped dopant ₄) and as two (methyl cyclopentadiene) magnesium (bis (methylcyclopentadiene) the magnesium, (CH of p-type dopant ₃C ₅H ₄) ₂Mg), two (ethyl cyclopentadienyl group) magnesium (bis (ethylcyclopentadienyl) magnesium, (C ₂H ₅C ₅H ₄) ₂Mg) or two (cyclopentadienyl group) magnesium (bis (cyclopentadienyl) magnesium, (C ₅H ₅) ₂Mg).

Be used for the carrier gas of growing GaN semiconductor layer, for example can adopt H ₂

Next, remove Sapphire Substrate 11 from the MOCVD device, wherein the GaN Semiconductor substrate is formed on this substrate in the manner described before.

Afterwards, form p lateral electrode 21 on p-type GaInN layer 20.The material that is used for p lateral electrode 21 is comprised of the ohmic metal with high reflectance, and is preferably Ag or Pd/Ag.Note, p lateral electrode 21 can form after N-shaped GaInN layer 13, N-shaped GaN layer 14, N-shaped GaInN layer 15, active layer 16, p-type GaInN layer 17, p-type AlInN layer 18, p-type GaN layer 19 and the 20 extensional mode growth of p-type GaInN layer again, but will be early than the heat treatment of the p-type impurity that is used for activation p-type GaInN layer 17, p-type AlInN layer 18, p-type GaN layer 19 and p-type GaInN layer 20.

Then, such as according to RIE method, powder injection process, sand-blast etc., N-shaped GaN layer 14, N-shaped GaInN layer 15, active layer 16, p-type GaInN layer 17, p-type AlInN layer 18, p-type GaN layer 19 and p-type GaInN layer 20 are according to the desired form patterning, thus formation platform part 22.

Then, form n lateral electrode 23 at adjacent with platform part 22 part place on N-shaped GaInN layer 13.N lateral electrode 23 be a kind of have for example be the electrode of Ti/Pt/Au structure.

Then, if necessary, be formed with the Sapphire Substrate 11 of light emitting diode construction as above on it, can sheared or grind from its dorsal part, to reduce its thickness, delineated subsequently Sapphire Substrate 11 and form bar.Afterwards, this is scored into chip.

In the GaN of gained light-emitting diode, as shown in Figure 3, carry out the light emission by apply forward voltage between p lateral electrode 21 and n lateral electrode 23 to transmit betwixt electric current, light transmission Sapphire Substrate 11 is extracted to the outside.In Fig. 3, as shown in the figure only towards top ejaculation, so Sapphire Substrate 11 be arranged on uppermost.Can guarantee to launch to the appropriate selection of the In component of active layer 16 red to ultraviolet, especially blue light, green glow or ruddiness.In this connection, light component the reflecting at the interface between Sapphire Substrate 11 and GaN layer 12 in notch part 11a towards Sapphire Substrate 11 that active layer 16 produces is mapped to the outside through Sapphire Substrate 11 afterwards.On the other hand, what active layer 16 produced reflects at p lateral electrode 21 places towards the light component of p lateral electrode 21, and towards Sapphire Substrate 11, passes Sapphire Substrate 11 and be mapped to the outside.Note, the refractive index of only getting GaN in the refractive index of the GaN semiconductor layer that consists of light-emitting diode shown in Fig. 3, namely 2.438, the refractive index of Sapphire Substrate 11 adopts 1.785, and the refractive index of air adopts the light in 1 situation.

In the first embodiment, for the threading dislocation density that makes GaN layer 12 minimizes, GaN layer 12 inclined plane under the state shown in the width W g of notch part 11a, depth d, Figure 1B and the angle [alpha] between Sapphire Substrate 11 first type surfaces satisfy following inequality (referring to Fig. 4)

2d≥W _gtanα

For example, work as W _g=2.1 μ m, when α=59 are spent, d 〉=1.75 μ m.Equally, at W _g=2 μ m, in the situation of α=59 degree, d 〉=1.66 μ m are at W _g=1.5 μ m, in the situation of α=59 degree, d 〉=1.245 μ m are at W _g=1.2 μ m, in the situation of α=59 degree, d 〉=0.966 μ m.In any case, preferred d＜5 μ m.

In the stage of growing GaN layer 12 in the step shown in Figure 1B and 1C, the ratio that is used between the parent material V/III of growth is set as higher value, and for example in 13000 ± 2000 scopes, and growth temperature is set as lower value, for example at 1050 ± 50 ℃.This has guaranteed the growth of GaN layer 12, to be used for covering notch part 11a fully, allows simultaneously to appear on inclined surface with respect to the face that substrate 11 first type surfaces tilt, as shown in Figure 1B and 1C.Under this condition, growing GaN layer 12 not almost on jut 11b.The growth of GaN layer 12 is being for example under 1.0 to 2.0 atmospheric pressure, preferably approximately carries out under 1.6 atmospheric pressure.This makes cross growth be suppressed, and easily is chosen in the growth that the GaN layer occurs in notch part 11a.The general range of the speed of growth is from 1.0 to 5.0 μ m/ hours, preferably approximately 3.0 μ m/ hours.The flow of initial gas, for example, TMG is 20SCCM, NH ₃Be 20SLM.On the other hand, the growth (cross growth) of the GaN layer 12 shown in Fig. 1 D and 1E in step is carried out according to following manner: the ratio between parent material V/III is set as lower value, for example in 5000 ± 2000 scopes, growth temperature is set as higher value, for example at 1150 ± 50 ℃.If growth temperature is higher than top scope, it is coarse that the GaN layer 12 of acquisition easily becomes in its surface.On the other hand, if temperature is lower, in GaN layer 12 interconnective position, pit appears easily.The flow of initial gas is for example that TMG is 40SCCM, NH ₃Be 20SLM.By this way, GaN layer 12 cross growth as shown in Fig. 1 D and 1E is to have obtained smooth surface.Very close to each other or empty appearance between GaN layer 12 and Sapphire Substrate 11.

It is how to flow, how to spread on Sapphire Substrate 11 in GaN layer 12 growth course that Fig. 5 has schematically shown initial gas.The most important part of this growth course is: in starting stage of growth, locate not growing GaN layer 12 at the jut 11b of Sapphire Substrate 11 (step part), but on notch part 11a beginning growing GaN layer 12.The following consideration of its reason.Usually, the parent material and the NH that are used as Ga as TMG ₃When being used as the parent material of N, pass through NH ₃And the direct reaction growing GaN between Ga, this reaction is represented by following reaction equation:

Ga (CH ₃) ₃(gas)+3/2H ₂(gas) → Ga (gas)+3CH ₄(gas)

NH ₃(gas) → (1-α) NH ₃(gas)+α/2N ₂(gas)+3 α/2H ₂(gas)

Ga (gas)+NH ₃(gas)=GaN (solid)+3/2H ₂(gas)

During reaction, produced H ₂Gas.This H ₂Growth has reaction, i.e. etching action to gas to crystal.In the step shown in Figure 1B and 1C, in correlation technique, utilizing is not the condition of GaN growth of carrying out on the flat substrate of using, and namely strengthens etching action, is difficult for producing the condition (increasing the condition of V/III value) of growth, and the growth at jut 11b place is suppressed.About this point, this etching action alleviates in notch part 11a, has therefore produced the crystal growth.In order to improve the surface flatness of growing crystals, in correlation technique, usually under the condition that increases cross growth degree (perhaps at higher temperature), grown crystal.According to the first embodiment, for by along with the crooked threading dislocation of the direction of Sapphire Substrate 11 major surfaces in parallel and in early days the stage adopt GaN layer 12 to bury the quantity that notch part 11a reduces threading dislocation, grow at lower than the temperature (for example 1050 ± 50 ℃) of mentioning in correlation technique above.

Fig. 6 schematically shows the crystal defect distribution results by the definite GaN layer 12 of transmission electron microscope (TEM).The planar cathode luminous (planarcathode luminescence) that Fig. 7 shows GaN layer 12 surface is image (CL).As can be seen from Figure 6, although uprise in the interrelated part dislocation density from the GaN layer 12 of adjacent recesses part 11a growth, the dislocation density step-down at the other parts place that comprises notch part 11a upper section.For example, in the width W of the depth d of notch part=1 μ m, basal surface _gThe upper surface width W of=2 μ m, jut 11b _tIn the situation of=2 μ m, partly locate at this low-dislocation-density, dislocation density is 1 * 10 ⁷/ cm ²Therefore, compare with the situation that adopts the Sapphire Substrate 11 of not carrying out surperficial sawtooth, dislocation density has reduced one or two orders of magnitude.Also can find out, on the direction vertical with notch part 11a sidewall, dislocation not occur.In planar cathode illuminated diagram shown in Fig. 7 and Fig. 6, result is very consistent.

In Fig. 6, the average thickness in and zone that degree of crystallinity poor high with the dislocation density of the contacted GaN layer 12 of Sapphire Substrate 11 at notch part 11a place is 1.5 times of average thickness in the zone that dislocation density is high, degree of crystallinity is poor of the GaN layer 12 that contacts with the Sapphire Substrate 11 at jut 11b place.This result has reflected the cross growth of GaN layer 12 on jut 11b.

Fig. 8 A and 8B have schematically shown the dislocation behavior in GaN layer 12 growth course, as finding in the tem analysis result.Fig. 8 A is sectional view, and Fig. 8 B is the plane graph corresponding with the sectional view shown in Fig. 8 A.Generally speaking, dislocation can be divided into two classes.

First kind dislocation ((a+c) Types of Dislocations) is as follows.In Fig. 8 A and 8B, from and notch part 11a bottom between the interface produce dislocation (1), the bottom is upper as the face (a) of the isosceles triangle hypotenuse on base, along continuous straight runs (namely the edge is parallel to the direction of Sapphire Substrate 11 first type surfaces) bending utilizing for dislocation (1).Dislocation (1) continues to extend to the sidewall of notch part 11a, and disappears at this place.From and notch part 11a bottom between generation dislocation at the interface (2), locate the along continuous straight runs bending on surface (a), and extend near the center of jut 11b.Then, dislocation (2) is located towards the top (along the direction perpendicular to Sapphire Substrate 11 first type surfaces) bending on the surface (c) that links with jut 11b center, vertically rise at the part place of linking again, and then formed threading dislocation in the center of jut 11b.This (a+c) type threading dislocation has 1/3＜11-23〉Burgers vector, and concentrate on the center of jut 11a.

The following describes Equations of The Second Kind dislocation (a type dislocation).As shown in Fig. 8 A and 8B, from and notch part 11a bottom between the interface dislocation (3) occurs, then along continuous straight runs is crooked near face (d), then continues to extend to the sidewall of notch part 11a, disappears at last.Attention: the bending of along continuous straight runs may not necessarily appear at face (d).Machine-processed similar to dislocation (3), dislocation (4) along continuous straight runs is crooked, extend near the center of jut 11b, and the part place of being associated at the center of jut 11b vertically rises, thereby formed threading dislocation in the center of jut 11b.Be extension on along continuous straight runs with the difference part of dislocation (2).Machine-processed similar with dislocation (3), dislocation (5) along continuous straight runs is crooked also to be extended near the center of jut 11b, and take advantage of a situation at this place (incidentally) is vertical to be extended.Dislocation (5) causes threading dislocation in the center of jut 11b.This a type threading dislocation has 1/3＜11-20〉Burgers vector.

Except (a+c) type dislocation and a type dislocation, the part place of linking at jut 11b center has observed the upper new threading dislocations (existing (a+c) type dislocation also has a type dislocation) that produce in GaN layer 12 surface.

Below, the estimated result of GaN layer 12 Dislocations density is described.As shown in Figure 9, angle between the sidewall of notch part 11a and Sapphire Substrate 11 first type surfaces represents with γ, the joint face of the upper growth of jut 11b and the angle between Sapphire Substrate 11 first type surfaces represent with β, the following expression of ratio in the high density of defects district on GaN floor 12:

R＝cotβ((W _g/2)tanα-d)/(1/2)(W _t+W _g+dcotγ)

In this case, dislocation density is estimated as W _Initial* (R+U (1-R)), wherein U represents to rise to the frequency of the lip-deep a type of GaN layer 12 dislocation (c dislocation) and is about 1/10 to 1/100 by experience.For example, near 59 degree, γ is close to 67 degree, W as α and β _gNear 2.1 μ m, Wt is near 2 μ m, and d is during near 1 μ m, and R is near 0.195, so W _InitialNear 3 * 10 ⁸/ cm ²Near 1/50 the time, dislocation density is close to 6.3 * 10 as U ⁷/ cm ²

In Figure 10 A and 10B, show the cross section TEM photo of the near interface between Sapphire Substrate 11 and GaN layer 12.Figure 11 shows the sectional view of near zone.Figure 10 A corresponding to dashed lines on the jut 11b that represents in Figure 11 around the zone, Figure 10 B corresponding to dashed lines on the notch part 11a that represents in Figure 11 around the zone.As shown in Figure 10 A and 10B, on the interface between Sapphire Substrate 11 and GaN layer 12, the concave point shape of observing in Sapphire Substrate 11 sides is different between notch part 11a and jut 11b.The width P of the concave point 13 that forms in notch part 11a is shown especially as Figure 11 _gThe width P of expression, the upper concave point 14 that forms of jut 11b _tDuring expression, P _t＞P _g, typical P _t＞1.2P _gThe width P of the concave point 14 that forms on jut 11b _tWidth P greater than the concave point that forms 13 in notch part 11a _gReason be: GaN layer 12 was not grown on jut 11b in the starting stage of growth, and jut 11b is exposed to the NH with etching action like this ₃In for a long time.In the method for correlation technique, this situation can not occur.

Figure 12 A shows the notch part 11a of Sapphire Substrate 11 and the cross section TEM photo (dark field image of jut 11b near zone, dark field image), Figure 12 B is the amplification cross section TEM photo of the upper surface near zone of the jut 11b shown in Figure 12 A, Figure 12 C is the enlarged drawing of the lower surface near zone of the notch part 11a shown in Figure 12 B, and wherein the black part in each figure is divided expression Sapphire Substrate 11.Figure 13 A has schematically shown the cross section of the upper surface near zone of the jut 11b shown in Figure 12 B, in GaN layer 12 on jut 11b the thickness in the relatively poor part zone of degree of crystallinity close to 37nm.Figure 13 B has schematically shown the basal surface of notch part 11a shown in Figure 12 C near zone cross section, in GaN layer 12 on notch part 11a the thickness range in the relatively poor part zone of degree of crystallinity close to from 18nm to 56nm.Find out from above, the thickness in the zone that the degree of crystallinity of the GaN layer 12 on notch part 11a and jut 11b is poor is different each other.This is because GaN layer 12 cross growth on jut 11b.In the method for correlation technique, do not show obvious difference.

In Figure 14, show an example, this example is to carrying out from the outside extraction light of GaN light-emitting diode (green LED) result (data represent with ■) that emulation (tracking emulation) obtains.In Figure 14, suppose that in the situation that get the size range of 20 μ m * 20 μ m on Sapphire Substrate 11, abscissa represents the area S on notch part 11a side-walls inclined plane, represents that also area S is with respect to 400 μ m ²Ratio (Area Ratio on inclined plane), ordinate represents light extraction efficiency η.As seen from Figure 14, the efficiency eta of extracting in order to improve light, the face S on inclined plane will be increased to large as far as possible degree.In Figure 14, show notch part 11a and be formed on Sapphire Substrate 11 similarly simulation result along three directions (for example in the situation that of equal value three＜1-100 each other on crystallography〉direction) with 60 degree intervals.In this case, the flat shape of jut 11a forms triangle.Result shows, in the situation that notch part 11a forms with 60 degree intervals along three directions, light extraction efficiency η is greater than the light extraction efficiency in the situation that notch part 11a extends to form with strip form along a direction.

With reference to Figure 15, again consider to make the area S of inclined surface maximize to improve light extraction efficiency η.Suppose in Figure 15 the unit length part along notch part 11a bearing of trend, on one-period, the shared area of the notch part 11a of Sapphire Substrate 11 and jut 11b is with (W _t+ W _g)+d/tan γ represents, the area of sidewall slope face represents with d/sin γ.Therefore, in order to improve light extraction efficiency η, make the ratio (d/sin γ) of inclined plane area/((W _t+ W _g)+d/tan γ) it is effective maximizing.

Figure 16 shows hypothesis d=1 μ m and W _t+ W _gWhen the angle γ between the sidewall of=4 μ m, notch part 11a and Sapphire Substrate 11 first type surfaces changes, the situation of change of inclined surface Area Ratio (data that heavy line represents).In Figure 16, the differential value of the data representation inclined plane Area Ratio that is represented by fine line.From Figure 16, when spending in γ=69, the inclined plane area ratio is 0.24.

Figure 17 shows hypothesis γ=67 degree, W _t+ W _gWhen the depth d of=4 μ m, notch part 11a changes, the situation of change of inclined plane Area Ratio (data that represent with heavy line).In Figure 17, the data representation that represents with fine line be differential value with the inclined plane Area Ratio.From Figure 17, at the dislocation density step-down of GaN layer 12 (for example d=1.66 μ m, α=59 degree, W _g=2 μ m) under this advantage, the inclined plane Area Ratio is 0.24.On the contrary, for example during d=1 μ m, the inclined plane Area Ratio is 0.18.

Figure 18 shows γ=67 degree, W _t+ W _gWhen the depth d of the notch part 11a of=7 μ m changes, the situation of change of inclined plane Area Ratio (data that represent with heavy line).In Figure 18, the data representation that represents with fine line be the differential value of inclined plane Area Ratio.From Figure 18, at the dislocation density step-down of GaN layer 12 (for example d=1.66 μ m, α=59 degree, W _g=2 μ m) under this advantage, the inclined plane Area Ratio is 0.18.On the contrary, for example during d=1 μ m, the inclined plane Area Ratio is 0.12.

Then, consider the situation of the growing surface of active layer 16 near zones.Usually, when the grown layer existence penetrates defective, can produce the growth concave point, and then cause that the flatness of growing surface worsens, as shown in figure 19.Higher threading dislocation density causes the increase of deterioration degree.If have threading dislocation in active layer 16, so planar the component of section and thickness fluctuate, and then cause the inhomogeneities of emission wavelength in the plane and flat crystal defective such as antiphase boundary defective (antiphase boundary defect) occurs, therefore cause the reduction (namely reduce internal quantum) of emission effciency.On the other hand, according to the first embodiment of the present invention, the threading dislocation density on GaN layer 12 can reduce as previously mentioned like that significantly, and therefore, the threading dislocation density of growth active layer 16 thereon can be equally very low.Therefore, the meeting that the emission effciency that causes due to threading dislocation reduces is very little, and then has obtained than emission effciency higher in correlation technique.

The threading dislocation of GaN layer 12 concentrates near the center of Sapphire Substrate 11 jut 11b, and is regularly arranged according to the array of jut 11b.Therefore, the threading dislocation of active layer 16 is correspondingly regularly arranged.Like this, compare with the situation of threading dislocation random alignment, in the zone that forms tabular surface, the area of active layer 16 parts significantly increases, and has therefore improved emission effciency.

In addition, for example, new crystal defect easily appears in the place that the In composition is high and growing surface is coarse in active layer 16, such as flat crystal defective and the dislocation combination of antiphase boundaries defective, and then causes emission effciency to reduce at this crystal defect place.On the contrary, according to the first embodiment, as mentioned above, the flatness on active layer surface is significantly improved, so just suppressed the appearance of crystal defect, emission effciency can not occur yet reduce.

For the flatness of improving active layer 16 growing surfaces, the quantity that reduces crystal defect, the barrier layer of making active layer 16 with AlGaN is effective.

As mentioned above, according to the first embodiment, do not form the gap between Sapphire Substrate 11 and GaN layer 12, can prevent that the light extraction efficiency that causes due to the gap from reducing.Threading dislocation in GaN layer 12 concentrates near the center of jut 11b of Sapphire Substrate 11, and the dislocation density of other parts is little of approximately 10 simultaneously ⁷/ cm ², therefore, the correlation technique that is subject to the substrate of patterning indentation with use is compared, and has reduced significantly dislocation density.Thereby, improve significantly on it degree of crystallinity such as the GaN semiconductor layer of GaN layer 12 and active layer 16 of growth, and then greatly reduced the quantity at non-emissive center.Like this, can obtain having the very GaN light-emitting diode of high emission efficiency.In addition, epitaxially grown one-period is enough to make the GaN light-emitting diode and does not need growth mask, and manufacture process becomes simple and can be with low cost fabrication GaN light-emitting diode like this.

Below, we will describe second embodiment of the present invention.

In a second embodiment, as shown in Figure 21 A, from the whole surface of smooth Sapphire Substrate 11, it is carried out Implantation, and then make the superficial layer of Sapphire Substrate 11 decrystallized, thereby form amorphous layer 31.The atom, energy and the dosage that are used for Implantation chosen will be enough to make Sapphire Substrate 11 decrystallized.For example, the atom that is used for Implantation comprises inert atom, such as He, Ne, Ar, Kr, Xe etc., and Si, H, N, Ga etc.For example, if with the atom of Si as Implantation, the energy range that is used for so Implantation is 10～30 kiloelectron-volts (KeV), and its dosage is 1 * 10 ¹⁸/ cm ²Perhaps.

Then, as shown in Figure 21 B, the pattern indentation occurs in the Sapphire Substrate 11 that is formed with amorphous layer 31, forms notch part 11a and jut 11b, is similar to the first embodiment.

Then, to as shown in 21E, growing GaN layer 12 on Sapphire Substrate 11 is similar to the first embodiment as Figure 21 C, has wherein formed amorphous layer 31 on jut 11b.

Then, grow the step of n-type GaInN layer 13 and step subsequently so that the GaN that is similar to the first embodiment light-emitting diode to be provided.

According to the second embodiment, can obtain the advantage similar to the first embodiment.

The third embodiment of the present invention is described now.

In the 3rd embodiment, as shown in Figure 22 A and 22B, 32 epitaxial growth of GaN layer are similar to the first embodiment on the Sapphire Substrate that the patterning indentation occurs.

Then, as shown in Figure 22 C, utilize the RIE method that GaN layer 32 is eat-back, only stay very thin GaN layer 32 in the bottom of the notch part 11a of Sapphire Substrate 11.

, as Figure 22 D as shown in, on the whole surface of Sapphire Substrate 11 it carried out Implantation thereafter, decrystallized to the superficial layer of Sapphire Substrate 11 jut 11b thus, to form amorphous layer 31.Simultaneously, also carry out decrystallized to GaN layer 32.The atom, energy and the dosage that are used for Implantation chosen will be enough to make GaN layer 32 decrystallized.For example, the atom that is used for Implantation comprises inert atom, such as He, Ne, Ar, Kr, Xe etc., and Si, H, N, Ga etc.For example, if with the atom of Si as Implantation, the energy range that is used for so Implantation is 10～30 kiloelectron-volts (KeV), and its dosage is 1 * 10 ¹⁸/ cm ²Perhaps.

Then, to as shown in 22G, be similar to the first embodiment as Figure 22 E, growing GaN layer 12 on Sapphire Substrate 11; Here, as mentioned above, Amorphous SiC layer 32 has been formed on the bottom that has formed amorphous layer 31 and notch part 11a on jut 11b.Attention: during the growth temperature that is heated to

GaN layer

12,32 crystallization of Amorphous SiC layer.

Then, the step of the n-type of growing GaInN layer and step subsequently are similar to the first embodiment so that the GaN light-emitting diode to be provided.

According to the 3rd embodiment, can obtain the advantage similar to the first embodiment.

The fourth embodiment of the present invention is described.

In the 4th embodiment, such as using the methods such as vacuum deposition method, sputtering method, chemical vapor deposition (CVD), form SiN film 33 as amorphous layer, as shown in Figure 23 A on the whole surface of smooth Sapphire Substrate 11.For example, the thickness of this SiN film 33 1nm or more than.

Then, as shown in Figure 23 B, such as using RIE method, powder injection process, sand-blast etc., the Sapphire Substrate 11 that has been formed with SiN film 33 on it is patterned indentation, to form notch part 11a and jut 11b, as in the first embodiment.

Then, as shown in Figure 23 C, growing GaN layer 34 under the low temperature of about 550 ℃ for example.For example, the thickness of GaN layer 34 is 200nm or less than 200nm.GaN layer 34 is grown in respectively the bottom of each notch part 11a of Sapphire Substrate 11, and is grown on SiN film 33, and wherein this SiN film 33 is formed on each jut 11b.

Then, to as shown in 23F, be similar to the first embodiment as Figure 23 D, growing GaN layer 12 on Sapphire Substrate 11; GaN layer 34 has been formed on the bottom that wherein, has formed SiN film 33 and notch part 11a on the jut 11b of Sapphire Substrate.During the growth temperature that is heated to

GaN layer

12,34 crystallization of GaN layer.So GaN layer 12 of having grown on the GaN of crystallization layer 34; On the other hand, during being heated to growth temperature, the GaN layer 34 on SiN film 33 has evaporated.

Then, the step of the n-type of growing GaInN layer 13 and step subsequently are similar to the first embodiment so that the GaN light-emitting diode to be provided.

According to the 4th embodiment, can obtain the advantage similar to the first embodiment.

The fifth embodiment of the present invention is described.

In the 5th embodiment, as shown in Figure 24 A, such as by methods such as vacuum deposition method, sputtering method, chemical vapor depositions (CVD), form successively SiN film 35, SiO on the whole surface of smooth Sapphire Substrate 11 ₂Film 36 and SiN film 37.For example,

SiN film

35,37 thickness be 1nm or more than, SiO ₂The thickness of film 36 be 10nm or more than.

Then, as shown in Figure 24 B, such as using RIE method, powder injection process, sand-blast etc., SiN film 35, SiO have been formed with ₂The Sapphire Substrate 11 of film 36 and SiN film 37 is patterned indentation, to form notch part 11a and jut 11b, is similar to the first embodiment.

As shown in Figure 24 C, utilize wet etching, for example, use the etchant of hydrofluoric acid base, only to SiO ₂Film 36 carries out etching, and after etching, its side along continuous straight runs is slightly stepped back.

Then, as shown in Figure 24 D, be similar to the first embodiment, growing GaN layer 12.As mentioned above, because SiO ₂The sidewall of film 36 is stepped back in the horizontal direction, so stoped at SiO ₂ Deposition GaN layer 12 on the sidewall of film 36.

Then, as shown in Figure 24 E, utilize wet etching, for example, have hydrofluoric acidic etchant, with SiO ₂Film 36 all removes, and SiN film 37 and GaN layer 34 that result will be grown above it also are removed (peeling off).

Then, as shown in Figure 24 F and 24G, be similar to the first embodiment cross growth GaN layer 12.

As the first embodiment, the step of the n-type of growing GaInN layer 13 and step subsequently are to provide the GaN light-emitting diode.

According to the 5th embodiment, can obtain the advantage similar to the first embodiment.

Then, the sixth embodiment of the present invention is described.

In the 6th embodiment, to as shown in 25D, growing GaN layer 12 on the Sapphire Substrate 11 that is patterned indentation is similar to the first embodiment as Figure 25 A.

As shown in Figure 25 E, utilize the methods such as RIE, GaN layer 12 is patterned, and removes selectively the part that the upper threading dislocation of jut 11b is concentrated, and then allows the surface of jut 11b to expose there.

As shown in Figure 25 F and 25G, from the remaining GaN layer 12 cross growth GaN layer 37 of notch part 11a.

Thereafter, the step of the n-type of growing GaInN layer 13 and step subsequently are similar to the first embodiment so that the GaN light-emitting diode to be provided.

According to the 6th embodiment, can obtain the advantage similar to the first embodiment.

Then, the seventh embodiment of the present invention is described.

In the 7th embodiment, as shown in Figure 26 A, growing GaN layer 38 on smooth Sapphire Substrate 11.

As shown in Figure 26 B, with GaN layer 38 patterning indentation, to form notch part 38a and jut 38b, be similar to notch part 11a and the jut 11b of the Sapphire Substrate 11 in the first embodiment.

Then, as the first embodiment, be patterned growing GaN layer 12 on the GaN layer 38 of indentation.

Then, the step of the n-type of growing in the same manner as in the first embodiment GaInN layer 13 and step subsequently are to provide the GaN light-emitting diode.

According to the 7th embodiment, can obtain the advantage similar to the first embodiment.

Then, the eighth embodiment of the present invention is described.

In the 8th embodiment, repeat the first embodiment, until form p lateral electrode 21, its step subsequently is different.In order to form p lateral electrode 21, preferably use certain technology that prevents electrode material (such as Ag etc.) diffusion, and insert the layer that contains palladium (Pd).As selection, in order to prevent failure, for example, in p lateral electrode 21, for example due to stress, Au or Sn from be formed on above-mentioned layer layer (weld layer, the projection etc.) diffusion that contains Au or Sn or because failure appears in heating, can use in essence barrier metal layer without crystal boundary and amorphous, the nitride of each of high melting point metal layer such as Ti, W or their alloy or these metals (such as TiN, WN, TiWN etc.) by form high melting point metal layer on electrode.The technology that insertion contains the Pd layer is well-known, for example insertion that contains the Pd layer in the metal plating field, and in the Al of silica-based electronic device wiring technique, the barrier metal material is well-known.

More specifically, as shown in Figure 27 A, after forming p lateral electrode 21, for example, form by promoting (lift) method the Ni film 41 that covers on p lateral electrode 21.Then, although not shown in the drawings, for example, form a Pd film to cover on Ni film 41.Then form metal nitride films, such as TiN, WN, TiWN etc., it covers on the Pd film, and if necessary, then formation covers the alloy film of Ti film, W film, Mo film or their formations on nitride film.Replace to form Ni film 41, can form the Pd film and cover p lateral electrode 21, then form the TiN, the WN that cover on the Pd film, TiWN film etc., if necessary, then form the alloy film that the Ti film that covers on film, W film, Mo film or their consist of.

Then, as shown in Figure 27 B, utilize photoetching process, the resist pattern 42 that forms given pattern covers Ni film 41 and the upper layers that comprises the Pd film.

Then, as shown in Figure 27 C, for example, resist pattern 42 is carried out etching as mask by the RIE method, to form platform part 22, wherein the shape in the cross section of platform part is trapezoidal.For example, the angle that forms between table top part 22 and Sapphire Substrate 11 first type surfaces is set to about 35 degree.If necessary, on the inclined plane of table top part 22, form λ/4 thin dielectric films, wherein λ is emission wavelength.

Then, as shown in Figure 27 D, on N-shaped GaInN layer 13, form n lateral electrode 23.

Then, as shown in Figure 27 E, on the whole surface of substrate, form SiO ₂Film 43, this film is as passivating film.In the mill, in the occasion of the adhesive force of consideration and the Sub, durability, corrosion resistance, can use SiN film or SiON film to replace SiO ₂Film 43.

As shown in Figure 27 F, in order to reduce its thickness, to SiO ₂Film 43 eat-backs, afterwards at the SiO of the sloping portion of platform part 22 ₂On film 43, form the Al film 44 as reflectance coating.This Al film 44 is used for and will reflexes to Sapphire Substrate 11 1 sides from the light that active layer 16 produces, and then improves light extraction efficiency.Form like this Al film 44, it is at one end contacted with n lateral electrode 23.This is because do not form the gap between Al film 44 and n lateral electrode 23, in order to strengthen the light reflection.Then, again form SiO ₂Film 43, its thickness is enough to form passivating film.

As shown in Figure 27 G, utilize etching, with Ni film 41 and the SiO above n lateral electrode 23 ₂ Film 43 parts are removed, and with formation opening 45,46, and then make Ni film 41 and n lateral electrode 23 in these part place's exposures.

Then, as shown in Figure 27 H, form pad electrode 47 on the Ni film 41 at opening 45 places, form pad electrode 48 on the n of opening part 46 lateral electrode 23.

As shown in Figure 27 I, projection mask material 49 is formed on the whole surface of substrate, by the part of etching pad electrode 48 tops, projection mask material 49 is removed to form opening 50 afterwards, at opening 50 place's exposed pad electrodes 48.

Then, as shown in Figure 27 J, utilize projection mask material 49, on pad electrode 48, form Au projection 51, subsequently projection mask material 49 is removed.Thereafter, then form projection mask material (not shown) on the whole surface of substrate, by etching, the projection mask material 49 that will be positioned at pad electrode 47 tops removes to form opening, at this opening part exposed pad electrode 47.Form Au projection 52 on pad electrode 47.

If necessary, the Sapphire Substrate 11 that is formed with light emitting diode construction in the mode that proposes is above cut or ground from its back side, to reduce the thickness of substrate, then to Sapphire Substrate 11 line, form bar.Then, bar is delineated into chip.

Attention: be an example to the electrode stack stack structure that 27J illustrates as Figure 27 A.Especially, each electrode layer a plurality of stacking in, need to obtain highly reflective by improving the p lateral electrode 21 and the adhesive force between other metal level, stress durability and the resistance to rupture that are formed by Ag electrode etc., and make that contact resistance is low, the quality that keeps Ag electrode etc. etc., consider simultaneously the stress of appearance and the diffusion between adjacent metal are suppressed, this stress is to raise with device temperature due to the difference of the thermal coefficient of expansion between each metal level to occur.Therefore, if necessary, can utilize the Al wiring technique of silicon electronic device recited above.

The ninth embodiment of the present invention is described.

In the 9th embodiment, the manufacture method of LED backlight device has been described, wherein, except GaN blue LED and GaN green LED that the method according to the first embodiment obtains, for this purpose, also use the AlGaInP red light emitting diodes that provides separately.

Method according to first embodiment of the invention, form GaN blue LED structure on Sapphire Substrate 11, the projection (not shown) is respectively formed on p lateral electrode 21 and n lateral electrode 23, then carries out the GaN blue LED that chip cutting obtains flip chip.Similarly, obtain the GaN green LED of flip chip.On the other hand, for the AlGaInP red light emitting diodes, the AlGaInP red light emitting diodes generally uses in the mode of chip, it is by forming an AlGaInP semiconductor layer and then providing a diode structure to obtain on N-shaped GaAs substrate, form the p lateral electrode on this diode structure, and form the n lateral electrode at the back side of N-shaped GaAs substrate.

These AlGaInP red light emitting diodes chips, GaN green LED and GaN blue LED are arranged on respectively on the pedestal that is made of AlN etc., then be arranged on substrate in the mode that pedestal is overturn downwards, Al substrate for example, this state is as shown in Figure 28 A.In Figure 28 A, mark 61 expression substrates.Similarly, 62 expression pedestals, the 63rd, AlGaInP red light emitting diodes chip, the 64th, GaN green LED chip, the 65th, GaN blue led chips.These AlGaInP red light emitting diodes chips 63, GaN green LED chip 64 and GaN blue led chips 65 have respectively for example 350 square chip sizes of μ m.These AlGaInP red light emitting diodes chips 63 are installed like this, to such an extent as to the n lateral electrode is on pedestal 62, GaN green LED chip 64 and GaN blue led chips 65 are installed respectively by this way, and namely p lateral electrode and n lateral electrode are arranged on pedestal 62 through projection.The extraction electrode (not shown) that the pedestal 62 that AlGaInP red light emitting diodes chip 63 is installed has a given pattern is used for n lateral electrode above it.The n lateral electrode of AlGaInP red light emitting diodes chip 63 is arranged on the specified portions of extraction electrode.In order to connect, the p lateral electrode of AlGaInP red light emitting diodes chip 63 is connected with line 67 respectively with given pad electrode 66 on being connected substrate 21.Similarly, the line (not shown) is connected with another pad electrode on being arranged on substrate 61 with the extraction electrode that is positioned at an end respectively, to guarantee the connection between them.The sub-installing rack 62 that GaN green LED chip 64 is installed has respectively the extraction electrode corresponding with the p lateral electrode and the extraction electrode corresponding with the n lateral electrode (all not illustrating), and this extraction electrode all forms with the pattern of expectation.The p lateral electrode of GaN green LED chip 64 and n lateral electrode respectively by projection be arranged on the extraction electrode of p lateral electrode and n lateral electrode extraction electrode to certain portions.The extraction electrode corresponding with the p lateral electrode of GaN green LED chip 64 is connected with a line (not shown) respectively with an end of pad electrode on being connected substrate 61, and the extraction electrode corresponding with the n lateral electrode is connected with a line (not shown) respectively with an end of pad electrode on being connected substrate 61.GaN blue led chips 65 is identical therewith.

Attention: can not use pedestal 62, in this case, AlGaInP red light emitting diodes chip 63, GaN green LED chip 64, GaN blue led chips 65 are directly installed on respectively on the arbitrary printed circuit board (PCB) with good emitting performance, have therefore reduced generally the cost of LED backlight device.

In practice, these AlGaInP red light emitting diodes chips 63, GaN green LED chip 64, GaN blue led chips 65 provide in the mode of device unit (unit cell), and the unit of requirement is arranged on substrate 61 with given pattern.An example of this mode is as shown in Figure 29 A.Then, as shown in Figure 28 B, utilize transparent resin 68 with the device unit encapsulation, and then the unit is covered.Then with transparent resin 68 sclerosis.By sclerosis, transparent resin 68 solidifies, thus resin generation minimal shrink (Figure 28 C).Utilize this method, obtain LED backlight device, wherein, AlGaInP red light emitting diodes chip 63, GaN green LED chip 64, GaN blue led chips 65 provide in the mode of device unit, specifically as shown in Figure 29 B, these unit are arranged in array on substrate 61.In this case, transparent resin 68 contacts with the back side of the Sapphire Substrate of GaN green LED chip 64 and GaN blue led chips 65, like this, the back side of the diversity ratio Sapphire Substrate 11 of its refractive index directly with situation that air contacts under little.Finally, cause transmitting by Sapphire Substrate 11 the more impossible backside reflection in Sapphire Substrate 11 of light that leaks into the outside, therefore improved light extraction efficiency.

Such LED backlight device is suitable for being applied as for example back lighting device of liquid crystal display screen.

Then, the tenth embodiment of the present invention is described.

In the tenth embodiment, the device unit of requirement on substrate 61 with the 9th embodiment in identical given arranged in patterns, these device units comprise AlGaInP red light emitting diodes chip 63, GaN green LED chip 64, GaN blue led chips 65.Then, as shown in figure 30, be fit to the transparent resin 69 of AlGaInP red light emitting diodes chip 63 (that is, the light for the diode chip for backlight unit emission wavelength has higher transparency) with 63 encapsulation of AlGaInP light-emitting diode chip for backlight unit, so that AlGaInP red light emitting diodes chip 63 is covered.Similarly, the 70 pairs of GaN light-emitting diode chip for backlight unit 64 of transparent resin that are fit to GaN green LED chip 64 encapsulate, to cover GaN green LED chip 64.The 71 pairs of GaN blue led chips 65 of transparent resin that are fit to GaN blue led chips 65 encapsulate, to cover GaN blue led chips 65.Then with transparent resin 69～71 sclerosis.By sclerosis, transparent resin 69～71 solidifies, and the result of solidifying is that minimal shrink occurs.Utilize this method, can obtain LED backlight device, it has a plurality of unit, and each unit is made of AlGaInP red light emitting diodes chip 63, GaN green LED chip 64, GaN blue led chips 65, and these unit are arranged in array on substrate 61.In this case, transparent resin 70,71 contacts with the back side of the Sapphire Substrate 11 of GaN green LED chip 64 and GaN blue led chips 65, like this, the back side of the diversity ratio Sapphire Substrate 11 of its refractive index directly with situation that air contacts under little.Finally, cause transmitting by Sapphire Substrate 11 fact that leaks into the more impossible backside reflection in Sapphire Substrate 11 of outside light, therefore improved light extraction efficiency.

Then, the 11st embodiment of the present invention is described.

In the 11 embodiment, according to the method for first embodiment of the invention, form the GaN light emitting diode construction on Sapphire Substrate 11, and the projection (not shown) is respectively formed on p lateral electrode 21 and n lateral electrode 23.Then, Sapphire Substrate 11 is delineated into the square part that has to sizing.Like this, as shown in figure 31, can access the integrated light-emitting diode with banded radiating portion.In this case, the n lateral electrode 23 of formation is around banded table top part 22.Shown in figure 32, integrated GaN light-emitting diode is arranged on the pedestal 69 that is made of AlN etc.Pedestal 69 has with the extraction electrode corresponding with the p lateral electrode of given pattern formation and the extraction electrode (all not shown) corresponding with the n lateral electrode, and

solder projection

70,71 is formed on extraction electrode.Integrated GaN light-emitting diode is installed so that p lateral electrode 21 is placed on scolder 70, n lateral electrode 23 is placed on scolder 71, and then melting

solder

70,71 connects.

Then, the 12nd embodiment of the present invention is described.

In the 12 embodiment, the manufacturing of light source cell unit (cell unit) has been described, except the GaN blue LED that obtains, GaN green LED, also used the AlGaInP red light emitting diodes of independent manufacturing in the step of the first embodiment.

As shown in Figure 33 A, the unit 81 of requirement on printed circuit board (PCB) 82 with given arranged in patterns, each unit comprises AlGaInP red light emitting diodes chip 63, GaN green LED chip 64, GaN blue led chips 65, the quantity of every kind of diode is 1 at least, and these diodes are with given arranged in patterns.In this example, individual unit 81 comprises an AlGaInP red light emitting diodes chip 63, a GaN green LED chip 64 and a GaN blue led chips 65, and they are positioned at vertex of a triangle.Figure 33 B has shown the unit 81 that amplifies.In unit 81, between AlGaInP red light emitting diodes chip 63, GaN green LED chip 64, GaN blue led chips 65 is for example 4mm apart from a, but is not limited to this distance.The distance b of unit 81 is for example 30mm, but is not limited to this.For printed circuit board (PCB) 82, can use FR4 (fire retardant type 4) substrate, metal core substrate etc., but not limit, also can use the printed circuit board substrate of other type with radiation (radiation) performance.Be similar to the 9th embodiment, transparent resin 68 is sealed to cover each unit 81.As selection, be similar to the tenth embodiment, transparent resin 69 is sealed to cover AlGaInP red light emitting diodes chip 63, transparent resin 70 is sealed to cover GaN green LED chip 64, transparent resin 71 sealings are covered GaN blue led chips 65.Utilize this mode, obtain light source cell unit, wherein unit 81 is arranged on printed circuit board (PCB) 82, and each unit 81 is made of AlGaInP red light emitting diodes chip 63, GaN green LED chip 64, GaN blue led chips 65.

The object lesson that unit 81 is arranged on printed circuit board (PCB) 82 is as shown in Figure 34 A and 34B.Example shown in Figure 34 A is 4 * 3 bidimensional unit 81 arrays, and the example shown in Figure 34 B is 6 * 2 bidimensional unit 81 arrays.

Figure 35 has shown the example of other type arrays of unit 81.In this example, unit 81 comprises an AlGaInP red light emitting diodes chip 63, two GaN green LED chips 64 and a GaN blue led chips 65, and they for example are arranged on foursquare summit.Two GaN green LED chips 64 are arranged in square cornerwise two ends, and AlGaInP red light emitting diodes chip 63 and GaN blue led chips 65 are arranged in square another cornerwise two ends.

When single or multiple when such light supply apparatus is set, LED backlight device is applicable is the back lighting device of liquid crystal display screen for example.

Hereinbefore, understand in detail embodiments of the invention, only be limited to these embodiment but present invention should not be construed as.The multiple variation of carrying out according to the technology of the present invention principle is all possible.

For example, the bearing of trend of numerical value, material, structure, shape, substrate, parent material, technique and the notch part 11a that illustrates in the first to the 12 embodiment of the present invention is only example.If necessary, can use the numerical value different from previous description, material, structure, shape, substrate, parent material, technique etc.

And in the first to the 12 embodiment of the present invention, for example, the conduction type of p-type GaN semiconductor layer and N-shaped GaN semiconductor layer can be exchanged.In addition, for example, the substrate of SiC substrate, Si substrate and other type also can replace Sapphire Substrate 11.

The bearing of trend of notch part 11a can not be GaN layer 12＜1-100〉direction, but GaN layer 12＜11-20〉direction.

If necessary, can be with two or more combinations in the first to the 12 embodiment.

It should be appreciated by those skilled in the art: in claim or the scope that requires of equal value, according to design needs and other factors, multiple improvement, combination, sub-portfolio and change can occur.

The theme that the present invention comprises is relevant at the Japanese patent application JP2006-105647 of Japan Office submission in Japanese patent application JP2005-142462 and on April 6th, 2006 that Japan Office is submitted to on May 16th, 2005, and its content is incorporated in herein as a reference.

Claims

1. a method of making light-emitting diode, comprise the steps:

Be provided at the substrate that has at least one notch part on a first type surface, by forming on the cross section the bottom surface of the described notch part leg-of-mutton state as the base, growth regulation mononitride base III-V compound semiconductor layer is buried described notch part thus;

On described substrate from the described first nitride based III-V compound semiconductor layer of nitride based III-V compound semiconductor layer cross growth second; And

The tetrazotization thing base III-V compound semiconductor layer of growing and having the 3rd nitride based III-V compound semiconductor layer, the active layer of the first conduction type and have the second conduction type successively on the described second nitride based III-V compound semiconductor layer

On the part except described notch part of described substrate, form successively the first amorphous layer, the second amorphous layer and the 3rd amorphous layer, and described the second amorphous layer with respect to described the first amorphous layer and described the 3rd amorphous layer by the selectivity etching.

2. according to claim 1 method, wherein, during growth the described first nitride based III-V compound semiconductor layer, along with the perpendicular direction of a described first type surface on, from and described notch part bottom surface between the interface dislocation occurs, this dislocation arrives with the leg-of-mutton inclined-plane as the base, the bottom surface of described notch part, and this dislocation is along crooked with the direction of a described major surfaces in parallel thus.

3. according to claim 1 method, wherein, when growing respectively the described first nitride based III-V compound semiconductor layer and the described second nitride based III-V compound semiconductor layer, be in the bottom surface of described notch part and form the first concave point with first width in described substrate, form the second concave point with second width in the part except described notch part of described substrate, described the second width is larger than described the first width.

4. according to claim 1 method, wherein, described notch part is the trapezoidal of reversing on the cross section.

5. according to claim 1 method, wherein, described first type surface has described notch part and the jut of alternative arrangement.

6. according to claim 1 method, wherein, described notch part extends along a direction.

7. according to claim 1 method, wherein, described at least one notch part is quantitatively a plurality of, and described a plurality of notch part extends along cross one another the first and second directions.

8. according to claim 5 method, wherein said jut is hexagon in the plane, and a plurality of this jut is arranged in bidimensional honeycomb form, and the described notch part that forms is around each jut.

9. according to claim 1 method, wherein said substrate is such: nitride based III-V compound semiconductor layer growth is on the material substrate different from nitride based III-V compound semiconductor layer, and described notch part is formed on described nitride based III-V family semiconductor layer.

10. according to claim 1 method, wherein, described substrate has the amorphous layer at the part place except described notch part of described substrate.

11. method according to claim 10 wherein, is carried out Implantation and described superficial layer is carried out the described amorphous layer of decrystallized formation by the superficial layer to described substrate.

12. method according to claim 10, wherein said amorphous layer is made of the dielectric film that is formed on described substrate.

13. method according to claim 1, wherein, after the nitride based III-V compound semiconductor layer of cross growth described second, part part on the described second nitride based III-V compound semiconductor layer notch part is removed, horizontal growth the described the 3rd nitride based III-V compound semiconductor layer on the described second nitride based III-V compound semiconductor layer that stays on described notch part, and grow successively on the described the 3rd nitride based III-V compound semiconductor layer described active layer and described tetrazotization thing base III-V compound semiconductor layer.

14. method according to claim 1, wherein, after the nitride based III-V compound semiconductor layer of cross growth described second, part part on the described second nitride based III-V compound semiconductor layer notch part is removed, the horizontal nitride based III-V compound semiconductor of growth regulation five layer on the described second nitride based III-V compound semiconductor layer that stays on described notch part, and the described the 3rd nitride based III-V compound semiconductor layer of growing successively on the described the 5th nitride based III-V compound semiconductor layer, described active layer and described tetrazotization thing base III-V compound semiconductor layer.

15. the method for a manufacturing integration light-emitting diode, it comprises the following steps:

Growth regulation mononitride base III-V compound semiconductor layer at least one notch part on a first type surface of substrate, the described first nitride based III-V compound semiconductor layer is formed on the cross section the bottom surface of the described notch part leg-of-mutton state as the base, thereby bury notch part;

Growing successively on the described second nitride based III-V compound semiconductor layer has the 3rd nitride based III-V compound semiconductor layer, active layer and the tetrazotization thing base III-V compound semiconductor layer of the first conduction type,

16. a light-emitting diode, it comprises:

The substrate that has at least one notch part on a first type surface;

Do not form the 6th nitride based III-V compound semiconductor layer in gap at described Grown and in described notch part; And

The 3rd nitride based III-V compound semiconductor layer, the active layer with first conduction type that forms on the described the 6th nitride based III-V compound semiconductor layer and the tetrazotization thing base III-V compound semiconductor layer with second conduction type

Wherein in the described the 6th nitride based III-V compound semiconductor layer, along with the perpendicular direction of a described first type surface on, from and described notch part bottom surface between the interface dislocation occurs, this dislocation arrives with the leg-of-mutton inclined-plane as the base, notch part bottom surface, and along crooked with the direction of a described major surfaces in parallel

17. a light-emitting diode, it comprises:

The substrate that has at least one notch part on a first type surface;

Wherein the first concave point with first width is formed on the bottom at described notch part in described substrate, forms the second concave point with second width in the part except described notch part of described substrate, and described the second width is larger than described the first width,

18. an integrated light-emitting diode that is integrated with a plurality of light-emitting diodes, at least one light-emitting diode comprises:

The substrate that has at least one notch part on a first type surface;

19. the method for a growing nitride base III-V compound semiconductor layer, it comprises the following steps:

Substrate is provided, this substrate has at least one notch part on a first type surface, by forming on the cross section the bottom surface of the described notch part leg-of-mutton state as the base, growth regulation mononitride base III-V compound semiconductor layer, and bury described notch part; And

On described substrate from the described first nitride based III-V compound semiconductor layer of nitride based III-V compound semiconductor layer cross growth second,

20. light source cell unit, it comprises printed circuit board (PCB) and a plurality of unit that are formed on described printed circuit board (PCB), each unit comprises at least one red light emitting diodes, at least one green LED and at least one blue LED, and at least one in wherein said red light emitting diodes, described green LED and described blue LED comprises:

The substrate that has at least one notch part on a first type surface;

21. a LED backlight device, it comprises:

Be arranged in a plurality of red light emitting diodes of pattern, a plurality of green LED and a plurality of blue LED, wherein, at least one in described red light emitting diodes, described green LED and described blue LED comprises:

The substrate that has at least one notch part on a first type surface;

Do not form the 6th nitride based III-V compound semiconductor layer in gap at described Grown and in described notch part;

The 3rd nitride based III-V compound semiconductor layer, the active layer with first conduction type that forms on the described the 6th nitride based III-V compound semiconductor layer and the tetrazotization thing base III-V compound semiconductor layer with second conduction type; And

In the described the 6th nitride based III-V compound semiconductor layer, along with the perpendicular direction of a described first type surface on, from and described notch part bottom surface between the interface dislocation occurs, this dislocation arrives with the leg-of-mutton inclined-plane as the base, notch part bottom surface, and along crooked with the direction of a described major surfaces in parallel

22. a light emitting diode indicator, it comprises:

The substrate that has at least one notch part on a first type surface;

23. the electronic device with at least one light-emitting diode, at least one light-emitting diode comprises:

The substrate that has at least one notch part on a first type surface;