CN101222206A - Method and device for correcting time constant of chip built-in resistor and capacitor - Google Patents

Abstract

A method for correcting an on-chip RC time constant of an integrated circuit tuner. The integrated circuit tuner comprises a receiving circuit for receiving radio frequency signals; a quadrature mixer coupled to the output of the receiving circuit; a polyphase filter; a relaxation oscillator; and a digital correction module. The image signal filtering function of the polyphase filter and the oscillation period of the relaxation oscillator are controlled by an RC time constant built in a chip. The calibration method comprises generating a clock proportional to the RC time constant built in the chip; the clock inputs a counter in the digital correction module; counting the period of the clock in a preset time section to generate a count value; and updating the RC time constant in the chip according to the counting value by using a continuous approximation correction method.

Description

Method and device for calibrating time constants of resistors and capacitors built into a chip

technical field

The present invention provides a chip built-in RC time constant correction method and device, especially an integrated circuit tuning method with an RC time constant precision self-calibration method to improve the image signal (image) rejection (rejection) function of a polyphase filter chip.

Background technique

Usually integrated circuit tuner chips use a polyphase filter to process the mixed signal of the in-phase/quadrature signal (I/Q signals) and the radio frequency signal from the quadrature mixer to form an image signal to filter the mixer, and output the desired signal. The quality of its image signal filtering function depends on the precise control of the RC time constant. Generally speaking, the resistance error of integrated circuit manufacturing resistors is about +/-20%, and the capacitance error of capacitors is about +/-10%, so it is not easy to accurately control the RC time constant. Therefore, the polyphase filter particularly needs an accurate RC time constant correction method to improve its image signal filtering function.

In a prior art US Patent No. 5,245,646, a reference clock is used to count a pulse determined by the RC time constant. However, since the frequency of the reference clock used is limited, and the counting speed of the counter is also limited, its overall performance is not particularly superior. In a word, providing a flexible and accurate RC time constant correction method and device is the fundamental way to improve the image signal filtering function of the integrated circuit tuner chip.

Contents of the invention

The invention provides an integrated circuit tuner using a chip built-in RC time constant correction method. The integrated circuit tuner includes a receiving circuit for receiving radio frequency signals; a quadrature mixer coupled to the output end of the receiving circuit; a polyphase filter; a relaxation oscillator; and a digital correction module.

The polyphase filter includes a first input end and a second input end, the first input end is coupled to an output end of the quadrature mixer, the digital correction module includes a 2-input AND gate, one of which A first input end is coupled to an output end of the relaxation oscillator; a counter, an input end thereof is coupled to an output end of the 2-input AND gate; a finite state machine includes an input end coupled to the 2-input AND gate. An output terminal of the counter, a first output terminal coupled to an input terminal of the relaxation oscillator and a second input terminal of the polyphase filter, and a second output terminal coupled to the 2-input AND gate a second input terminal.

The present invention also provides a method for calibrating the built-in RC time constant of the polyphase filter of the integrated circuit tuner. The image signal filtering function of the polyphase filter is controlled by a built-in RC time constant of the chip. The method comprises generating a clock by a relaxation oscillator, the period of the clock is proportional to the on-chip RC time constant; the clock is input to a counter in the digital correction module, and a finite state machine in the digital correction module sends an enabling signal to Setting a predetermined time period, counting the period of the clock to generate a count value; comparing the count value with an expected value in the finite state machine to generate a comparison result; and updating the digital correction module according to the comparison result On-chip RC time constant (rc_code) to polyphase filter and relaxation oscillator.

Description of drawings

FIG. 1 is a schematic circuit diagram of an integrated circuit tuner according to the present invention.

FIG. 2 is a flowchart of a binary search approximation correction method in a preferred embodiment of the present invention.

FIG. 3 is a schematic diagram of the internal circuit of the relaxation oscillator shown in FIG. 1 .

Description of main component symbols

100 integrated circuit tuner 105 receiving circuit

110 Cross Mixer 120 Polyphase Filter

130 Digital Correction Module 140 Relaxation Oscillator

1502 input AND gate 160 counter

170 finite state machine 310 first comparator

320 2nd comparator 330 1st 2-input NAND gate

340 second 2-input NAND gate rc_code correction code

I In-phase signal Q Quadrature signal

CLK clock clock n n correction code bits

NP Period Count Value EN Enable Signal

C1 The first capacitor area C2 The second capacitor area

SW1 first switch SW2 second switch

Vref Bandgap V1, V2 voltage source

  Reference Voltage

N1, N2, node VN1, VN2, node voltage

N3, N4, VN4, VN5

N5

400 Process 200-300 Steps

Detailed ways

As mentioned above, the prior art of US Patent No. 5,245,646 discloses the use of a reference clock to count a pulse determined by the RC time constant. The technology of the present invention is to generate a clock determined by the RC time constant, and to count the cycle of the clock in a predetermined time period to generate a cycle count value, and then use the cycle count value and an expected value to execute the RC time Constant correction, the longer the predetermined time period is, the more accurate the corrected RC time constant is. Since there is no limit to the predetermined time period, the RC time constant can achieve any required accuracy, so the integration can be significantly improved The image signal filtering function of the circuit tuner chip.

Please refer to FIG. 1 . FIG. 1 shows a schematic circuit diagram of an integrated circuit tuner 100 with an on-chip RC time constant correction function according to the present invention. The integrated circuit tuner 100 includes a receiving circuit 105 for receiving a radio frequency signal; a quadrature mixer 110 coupled to the output of the receiving circuit 105; and a polyphase filter rccr_combiner 120 coupled to the quadrature mixer The output of 110 is used to process the mixing signal of the in-phase/orthogonal signal (I/Q signals) and the radio frequency signal from the quadrature mixer 110, to form an image signal filtering mixer, and output the desired signal . The polyphase filter rccr_combiner 120 includes multiple resistors and multiple capacitors. In order to avoid output image distortion, the polyphase filter rccr_combiner 120 also receives a correction code rc_code (on-chip RC time constant) to adjust its multiple resistors and multiple capacitors. The circuit operation of the capacitor is used to perform the correcting function of filtering out false image signals. Since the operation principle of the polyphase filter rccr_combiner 120 is a known technology, it will not be repeated here.

The IC tuner 100 also includes a relaxation oscillator 140 and a digital correction module 130 . The digital correction module 130 includes a 2-input AND gate 150 , a counter 160 , and a finite state machine 170 for updating and outputting the correction code rc_code to the polyphase filter rccr_combiner 120 and the relaxation oscillator 140 . The relaxation oscillator 140 updates its oscillation frequency according to the received calibration code rc_code, and outputs the clock CLK with the updated frequency to the digital calibration module 130. The calibration code rc_code can be continuously changed to correct the operation of related components. The 2-input AND gate 150 has a first input terminal, a second input terminal, and an output terminal, the first input terminal is used to receive the clock CLK output by the relaxation oscillator 140, and the second input terminal is used to receive the finite state machine The enable signal EN output by 170 is coupled to the counter 160 at its output terminal.

The period of the clock CLK output by the relaxation oscillator 140 is proportional to the on-chip RC time constant correction code rc_code. The counter 160 is controlled by the enable signal EN output by the finite state machine 170 to start and stop counting in a predetermined time period, and the counter 160 counts the period of the relaxation oscillator 140 output clock CLK in the predetermined time period to generate a period For the count value NP, the finite state machine 170 uses the binary search approximation correction method to update the correction code rc_code according to the period count value NP output by the counter 160, and provides the updated correction code rc_code to the relaxation oscillator 140 and the polyphase filter rccr_combiner 120.

Please refer to FIG. 2 , which shows a flowchart of a continuous approximation search correction method 400 according to a preferred embodiment of the present invention. First, all the bit values of the correction code rc_code are set to "0", and the finite state machine 170 of the digital correction module 130 outputs an enable signal EN to control the counter 160 to count the number of times of the relaxation oscillator 140 output clock CLK in a predetermined time period. period to generate a period count value NP. Afterwards, the finite state machine 170 compares the period count value NP with an expected value. If the period count value NP is greater than the expected value, it means that the oscillation frequency of the relaxation oscillator 140 is too high. At this time, one bit of the correction code rc_code will be is updated to increase the RC time constant. On the contrary, if the period count value NP is smaller than the expected value, it means that the oscillation frequency of the relaxation oscillator 140 is too low, and at this time, one bit of the correction code rc_code will be updated to reduce the RC time constant. The above-mentioned comparing and updating procedures are continuously executed, and each bit of the correction code rc_code is updated sequentially from the most significant bit to the least significant bit.

The continuous approach search correction method 400 includes the following steps:

Step 200: start;

Step 210: Set the initial value of all the bit values of the correction code rc_code to "0", assuming that the correction code rc_code is an n-bit binary code, and its bit index value range is set from 1 to n, and n represents the most effective The index value of the bit, 1 represents the index value of the least significant bit, set a variable i, and set the initial value of the variable i to n;

Step 220: the finite state machine 170 sends an enabling signal EN to start counting to start the counting state of the counter 160, and after a predetermined time period, the finite state machine 170 sends an enabling signal EN to stop counting to stop the counting state of the counter 160 ;

Step 230: The finite state machine 170 compares the period count value NP generated by the counter 160 with an expected value, and if the period count value NP is greater than the expected value, execute step 240, otherwise execute step 250;

Step 240: The finite state machine 170 sets the effective bit value of the index value i in the correction code rc_code to "1" to increase the value of the correction code rc_code to reduce the oscillation frequency of the relaxation oscillator 140, and execute step 260;

Step 250: The finite state machine 170 sets the effective bit value of the index value i in the correction code rc_code to "0" to reduce the value of the correction code rc_code to increase the oscillation frequency of the relaxation oscillator 140, and execute step 260;

Step 260: the finite state machine 170 judges whether the value of the variable i is greater than 1, if the value of the variable i is greater than 1, execute step 270, otherwise execute step 280;

Step 270: Set the effective bit value of the index value i-1 in the correction code rc_code to "1";

Step 280: decrement the value of variable i by 1;

Step 290: If the value of the variable i is not equal to 0, it means that the correction code rc_code has not been corrected yet, jump back to step 220, otherwise execute step 300;

Step 300: end.

In the above-mentioned continuous approximation search correction method 400, in step 210, the initial values of all the bit values of the correction code rc_code are set to "0", which can be changed to set the most significant bit of the correction code rc_code to "1", and At least one bit other than the most significant bit is set to "0", that is, the initial value of the correction code rc_code is set to an intermediate value, and then the continuous approximation search procedure is started. In general, under the condition that the correction result of the correction code rc_code is not affected, equal changes similar to the continuous approximation method are within the scope of the present invention.

Please refer to FIG. 3 . FIG. 3 is a schematic diagram showing an internal circuit of the relaxation oscillator 140 of FIG. 1 . The relaxation oscillator 140 includes a first capacitance area C1, including a set of on-chip capacitors and resistors controlled by the calibration code rc_code; a second capacitor area C2, including another on-chip capacitor and resistors controlled by the calibration code rc_code set; a first comparator 310; a second comparator 320; a first 2-input NAND gate 330; and a second 2-input NAND gate 340.

Both the first capacitor area C1 and the second capacitor area C2 include multiple capacitors and multiple resistors, which are used to simulate the circuit functions of the multiple capacitors and multiple resistors included in the polyphase filter rccr_combiner 120, so that the relaxation oscillator 140 It can effectively reproduce the effect of the current correction code rc_code acting on the polyphase filter rccr_combiner 120.

The first capacitive region C1 is coupled between the node N1 and the ground, and has an input terminal for receiving the calibration code rc_code. The node N1 is coupled to a voltage source V1, the negative input terminal of the first comparator 310, and a first switch SW1, which has a control input terminal coupled to the node N4, that is to say, the first switch SW1 is controlled by the node voltage of the node N4 Controlled by VN4, when the node voltage VN4 is at a high level, the first switch is in a closed state, that is, the first capacitor region C1 is set to a discharge state; when the node voltage VN4 is at a low level, the first switch is in an open state, That is, the first capacitor region C1 is set to be in a charging state. At this time, the first capacitor region C1 uses the correction code rc_code to control the circuit operation of the on-chip capacitor resistor group to control the RC charging constant of the charging state.

The second capacitive region C2 is coupled between the node N2 and the ground, and has an input terminal for receiving the correction code rc_code. The node N2 is coupled to a voltage source V2, the negative input terminal of the second comparator 320, and a second switch SW2 , has a control input terminal coupled to the node N5, that is to say, the second switch SW2 is controlled by the node voltage VN5 of the node N5, when the node voltage VN5 is at a high level, the second switch is in a closed state, that is, the second Capacitance area C2 is set to discharge state. When node voltage VN5 is at low level, the second switch is in open state, that is, the second capacitance area C2 is set to charge state. At this time, the second capacitance area C2 uses the correction code rc_code controls the circuit operation of its on-chip capacitor-resistor set to control the RC charge constant of the state of charge.

The positive input ends of the first comparator 310 and the second comparator 320 both receive a bandgap (bandgap) reference voltage Vref, the output end of the first comparator 310 is coupled to the first input end of the first 2-input NAND gate 330, The output terminal of the second comparator 320 is coupled to the first input terminal of the second 2-input NAND gate 340, and the second input terminal of the first 2-input NAND gate 330 is coupled to the output terminal of the second 2-input NAND gate 340 At the node N5, the second input terminal of the second 2-input NAND gate 340 and the output terminal of the first 2-input NAND gate 330 are coupled to the node N4, and the output clock CLK of the relaxation oscillator 140 is output to the node N4.

The first 2-input NAND gate 330 and the second 2-input NAND gate 340 are connected to form an RS latch (RS-Latch). The first input terminal of the second 2-input NAND gate 340 is the Set input terminal, and the first The first input terminal of the 2-input NAND gate 330 is the Reset input terminal. When both the Set input terminal and the Reset input terminal receive a high-level signal, the RS-Latch is in a latch state, that is, it is held The storage state of the output state, pay special attention to the latch state (storage state) of the RS latch connected by two 2-input NAND gates is different from the RS latch connected by two NOR gates, when When the Set input terminal receives a high-level signal and the Reset input terminal receives a low-level signal, the output node voltage VN4 of the first 2-input NAND gate 330 is high level, and the output node voltage of the second 2-input NAND gate 340 is VN5 is low level, when the Set input end receives a low level signal and the Reset input end receives a high level signal, the output node voltage VN4 of the first 2-input NAND gate 330 is low level, and the second 2-input NAND The output node voltage VN5 of the NOT gate 340 is high level.

Assuming that the Set input terminal receives a high-level signal and the Reset input terminal receives a low-level signal, as described above, the node voltage VN4 is at a high level and the node voltage VN5 is at a low level, that is, the output clock CLK of the relaxation oscillator 140 is at High level state, so the first switch is set to the closed state and the second switch is set to the open state, that is, the first capacitance area C1 is set to the discharge state, and the second capacitance area C2 is set to the Charging state, because the negative input terminal (node N1) of the first comparator 310 is short-circuited to ground at this time, that is, the negative input terminal voltage of the first comparator 310 is less than the positive input terminal voltage (bandgap reference voltage Vref), so The signal at the output terminal (Reset input terminal) of the first comparator 310 is converted from a low level to a high level. At this time, both the Set input terminal and the Reset input terminal receive a high level signal, so the RS latch is in a latched state , its output state remains unchanged, that is, the output clock CLK of the relaxation oscillator 140 remains in a high-level state. (Set input terminal) signal is converted from high level to low level. At this time, the Set input terminal receives a low level signal and the Reset input terminal receives a high level signal, so the output node voltage of the first 2-input NAND gate 330 VN4 transitions to a low level, and the output node voltage VN5 of the second 2-input NAND gate 340 transitions to a high level, that is, the output clock CLK of the relaxation oscillator 140 transitions to a low level state.

Thereafter, the first switch is set to an open state and the second switch is set to a closed state, that is, the first capacitive region C1 is set to a charging state, and the second capacitive region C2 is set to a discharging state, At this time, because the negative input terminal (node N2) of the second comparator 320 is short-circuited to ground, that is, the negative input terminal voltage of the second comparator 320 is smaller than the positive input terminal voltage (bandgap reference voltage Vref), so the second comparator The signal at the output terminal (Set input terminal) of the device 320 is converted from a low level to a high level. At this time, both the Set input terminal and the Reset input terminal receive a high level signal, so the RS latch is in a latched state, and its output The state remains unchanged, that is, the output clock CLK of the relaxation oscillator 140 remains in a low-level state. When the node voltage VN1 is charged from zero potential to be greater than the bandgap reference voltage Vref, the output terminal (Reset input terminal) signal from high level to low level, at this time, the Set input terminal receives a high level signal and the Reset input terminal receives a low level signal, so the output node voltage VN4 of the first 2-input NAND gate 330 is converted to High level, and the output node voltage VN5 of the second 2-input NAND gate 340 is switched to low level, that is, the output clock CLK of the relaxation oscillator 140 is switched to a high level state.

As mentioned above, the charge state and discharge state of the first capacitance area C1 and the second capacitance area C2 are constantly changing alternately to generate the output oscillation clock CLK of the relaxation oscillator 140, and because the first capacitance area C1 and the second capacitance area The time constant of the region C2 in the charging state is proportional to the on-chip RC time constant correction code rc_code, so the oscillation period of the relaxation oscillator 140 output clock CLK is also proportional to the on-chip RC time constant correction code rc_code.

From the above, it can be seen that the technology of the present invention breaks through the limitations of the prior art on RC time constant correction. The technology of the present invention uses a relaxation oscillator to generate a clock determined by the RC time constant, and is used to count the clock within a predetermined time period to generate a cycle count value, and then compare the cycle count value with an expected value to perform RC time constant correction. The longer the predetermined time period is, the more effective digits the correction code rc_code has, and the corrected RC time constant It is also more accurate. In general, there are two main sources of calibration error, one is the delay error caused by the comparator in the relaxation oscillator, and the other is the synchronization count error when starting and stopping counting. The structure of the present invention is advanced in that the two errors can be reduced below the allowable error by reducing the oscillation frequency of the relaxation oscillator and extending the predetermined time period. That is to say, a longer calibration time can improve calibration accuracy. Therefore, the correction of the RC time constant can achieve any required accuracy, so the image signal filtering function of the integrated circuit tuner chip can be significantly improved.

By using appropriate types of resistors and capacitors, the variation of the RC time constant with temperature and voltage changes can be reduced to negligible conditions, that is, the variation of the RC time constant is mainly affected by semiconductor manufacturing. Therefore, it is only necessary to perform an RC time constant calibration procedure once when starting up, and there is no need for further calibration thereafter. Therefore, the longer calibration time will not have any impact on the circuit operation after the power-on calibration procedure is completed. The high-precision RC time constant correction method and device provided by the present invention can ensure that the image signal filtering function is only limited by the filtering resolution of the polyphase filter, not by the precision of the correction procedure. Compared with the typical voltage comparator structure, the structure of the present invention can save chip area and reduce circuit complexity.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (13)

1. the integrated circuit tuner of the multiphase filter of a tool chip built-in RC time constant calibration function comprises:

One orthogonal mixer;

One multiphase filter comprises a first input end and one second input, and this first input end is coupled to an output of this orthogonal mixer;

One relaxation oscillator; And

One figure adjustment module comprises an output and be coupled to second input of this multiphase filter and an input of this relaxation oscillator, and an input is coupled to an output of this relaxation oscillator.

2. integrated circuit tuner as claimed in claim 1, wherein this figure adjustment module comprises:

One 2 inputs and door comprise the input that a first input end is coupled to this figure adjustment module;

One counter comprises the output that an input is coupled to this 2 input and door; And

One finite state machine comprises the output that an input is coupled to this counter, and one first output is coupled to the output of this figure adjustment module, and one second output is coupled to one second input of this 2 input and door.

3. integrated circuit tuner as claimed in claim 2, wherein this relaxation oscillator comprises:

One first capacitive region is coupled between a first node and the ground connection, comprises the input that an input is coupled to this relaxation oscillator, and this first node is coupled to one first voltage source;

One first switch is coupled between this first node and the ground connection;

One first comparator comprises a first input end and is coupled to this first node, and one second input is coupled to one the 3rd node, and the 3rd node is coupled to a reference voltage;

One the 1 input nand gate, comprise the output that a first input end is coupled to this first comparator, one second input is coupled to one the 5th node, and one output be coupled to one the 4th node, the 4th node is coupled to a control input end of this first switch and the output of this relaxation oscillator;

One second capacitive region is coupled between a Section Point and the ground connection, comprises the input that an input is coupled to this relaxation oscillator, and this Section Point is coupled to one second voltage source;

One second switch is coupled between this Section Point and the ground connection;

One second comparator comprises a first input end and is coupled to this Section Point, and one second input is coupled to one the 3rd node; And

One the 22 input nand gate, comprise the output that a first input end is coupled to this second comparator, one second input is coupled to one the 4th node, and an output is coupled to one the 5th node, and the 5th node is coupled to a control input end of this second switch.

4. integrated circuit tuner as claimed in claim 1, wherein this relaxation oscillator comprises:

One first capacitive region is coupled between a first node and the ground connection, comprises the input that an input is coupled to this relaxation oscillator, and this first node is coupled to one first voltage source;

One first switch is coupled between this first node and the ground connection;

One first comparator comprises a first input end and is coupled to this first node, and one second input is coupled to one the 3rd node, and the 3rd node is coupled to a reference voltage;

One the 1 input nand gate, comprise the output that a first input end is coupled to this first comparator, one second input is coupled to one the 5th node, and one output be coupled to one the 4th node, the 4th node is coupled to a control input end of this first switch and the output of this relaxation oscillator;

One second capacitive region is coupled between a Section Point and the ground connection, comprises the input that an input is coupled to this relaxation oscillator, and this Section Point is coupled to one second voltage source;

One second switch is coupled between this Section Point and the ground connection;

One second comparator comprises a first input end and is coupled to this Section Point, and one second input is coupled to one the 3rd node; And

One the 22 input nand gate, comprise the output that a first input end is coupled to this second comparator, one second input is coupled to one the 4th node, and an output is coupled to one the 5th node, and the 5th node is coupled to a control input end of this second switch.

5. integrated circuit tuner as claimed in claim 4, wherein this first capacitive region and this second capacitive region all comprise a plurality of electric capacity and a plurality of resistance, in order to simulate a plurality of electric capacity that this multiphase filter comprises and the circuit function of a plurality of resistance.

6. integrated circuit tuner as claimed in claim 5, wherein this figure adjustment module comprises:

One 2 inputs and door comprise the input that a first input end is coupled to this figure adjustment module;

One counter comprises the output that an input is coupled to this 2 input and door; And

One finite state machine comprises the output that an input is coupled to this counter, and one first output is coupled to the output of this figure adjustment module, and one second output is coupled to one second input of this 2 input and door.

7. chip built-in RC time constant bearing calibration that is used for the multiphase filter of integrated circuit tuner, the image signal filtering function of this multiphase filter is controlled by a chip built-in RC time constant, and this method comprises the following step:

(a) produce a clock, the cycle of this clock is proportional to this chip built-in RC time constant;

(b) in a scheduled time section, the cycle of counting this clock is to produce a count value;

(c) this count value and a desired value are compared to produce a comparative result; And

(d) upgrade this chip built-in RC time constant according to this comparative result.

8. bearing calibration as claimed in claim 7 also comprises:

This chip built-in RC time constant is set at an initial value.

9. bearing calibration as claimed in claim 8, wherein this chip built-in RC time constant comprises a plurality of positions, and the one highest significant position is set at " 1 ".

10. bearing calibration as claimed in claim 8, wherein upgrading this chip built-in RC time constant is to set the position data of this chip built-in RC time constant according to this comparative result.

11. bearing calibration as claimed in claim 8, wherein after this chip built-in RC time constant is finished initial value and is set, from the highest significant position to the least significant bit according to step (a) and (b), (c), and repeating and new settings more (d).

12. bearing calibration as claimed in claim 7 also comprises:

The voltage and a preset reference voltage of comparison one first capacitive region, voltage and this preset reference voltage of comparison one second capacitive region are in order to control the cycle of this clock.

13. bearing calibration as claimed in claim 12 also comprises:

Adjust effective number of a plurality of chip built-in electric capacity in this first capacitive region and this second capacitive region according to this chip built-in RC time constant.

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