CN101211782B - Method for etching conductive composite layer - Google Patents
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- CN101211782B CN101211782B CN2006101480124A CN200610148012A CN101211782B CN 101211782 B CN101211782 B CN 101211782B CN 2006101480124 A CN2006101480124 A CN 2006101480124A CN 200610148012 A CN200610148012 A CN 200610148012A CN 101211782 B CN101211782 B CN 101211782B
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Abstract
A method for etching a conductive composite layer comprises the following steps that: an oxygen ambient silica layer, the conductive composite layer and a nano-pattern photoresist layer are formed on a silicon substrate in order and the silicon substrate with the oxygen ambient silica, the conductive composite layer and the nano-pattern photoresist layer is put in an etching reaction chamber; the etching pressure in the reaction chamber is increased from 6 millitorr - 10 millitorr to 10 millitorr - 30 millitorr and the conductive composite layer is etched till the oxygen ambient silica is exposed with the nano-pattern photoresist layer as mask. After the steps, the semiconductor device formed at last has leveled profile, the verticality of the side wall of the groove or contact hole is good, and the time for making the semiconductor device is shortened so as to further enhance the yield of the chip.
Description
Technical field
The present invention relates to the manufacture method of semiconductor device, particularly make in the semiconductor device process method of etching conductive composite layer.
Background technology
For the electrode and interconnection line of integrated circuit, the conductive composite layer of 2 μ m thickness is enough, but, for the silicon base spiral inductance, in order to improve quality factor, press for the series resistance that reduces the metal spiral coil, therefore adopt thickness more favourable greater than the metal level (hereinafter to be referred as thick metal) of 2 μ m; In the special for another example power device and circuit, also usually use thick metal and reduce resistance and improve heat radiation.Though wet etching can the thick metal of etching, because the isotropism of its etch rate can't guarantee lines precision and sidewall pattern.Therefore, it is imperative to develop the high accuracy dry etching technology of thick metal.
The high accuracy dry etching technology of thick metal is a difficult point in the submicron integrated circuit technology always.In order to guarantee the lines precision of sub-micron, need to adopt dry etching technology, generally use high-resolution photoresist layer as etch mask; But, because reacting gas BCl commonly used
3And Cl
2The composite material of etching aluminium, titanium and titanium nitride compares usually all less than 2: 1 the selection of conductive composite layer and high-resolution photoresist layer; In order to guarantee exposure resolution ratio, use photoresist layer thickness to be no more than 3 μ m usually, considered to measure and process allowance quarter, be difficult to the aluminium of etch thicknesses more than 2 μ m.
The patent No. is the method that 98124176 Chinese patent discloses dry etching conductive composite layer in Wiring technique.Shown in Figure 1A, finish on the silicon substrate 100 of ground floor aluminium wiring with chemical vapour deposition technique silicon oxide layer 102, be used for isolation between device as interlayer dielectric layer; Sputter thickness is the conductive composite layer 104 of 5 μ m on silicon oxide layer 102, and described conductive composite layer 104 is the composite material of aluminium, titanium and titanium nitride; Then on conductive composite layer 104, form anti-reflecting layer 106 with chemical vapour deposition technique; Form photoresist layer 108 with spin-coating method on anti-reflecting layer 106, photoresist layer 108 thickness of spin coating are 1.8 μ m.
Shown in Figure 1B, photoresist layer 108 is carried out exposure-processed, the semiconductor device graph on the light shield is transferred on the photoresist layer 108, through behind the developing process, on photoresist layer 108, form photoresistance figure 107.
Shown in Fig. 1 C, the silicon substrate 100 that will have silicon oxide layer 102, conductive composite layer 104, anti-reflecting layer 106 and photoresist layer 108 is put into reative cell; In reative cell, feed BCl
3And Cl
2Mist is etched to along photoresistance figure 107 antagonistic reflex layers 106 and conductive composite layer 104 and exposes silicon oxide layer 102, BCl
3And Cl
2Gaseous mixture is known from experience silicon oxide layer 102 generation over etchings, and wherein the etching pressure of reative cell is 6～10 millitorrs (1 holder=133.33 Pascals), gas BCl
3Flow be 40～90sccm, Cl
2Flow be 120～190sccm, the bottom radio frequency is 100～200W in the reative cell, the selection ratio that obtains gas etching conductive composite layer 104 and silicon oxide layer 102 thus is 8, the selection ratio of etching conductive composite layer 104 and photoresist layer 108 is 1～2.5, etch rate is 0.5 μ m/min, and the required time of etching is 15min; Remove photoresist layer 106 with ashing method at last.
Fig. 2 is the design sketch with the intact conductive composite layer of prior art etching.As shown in Figure 2, when being 25,000 times, multiplication factor observes conductive composite layer 104 effects of Figure 1A to Fig. 1 C etching with scanning electron microscopy.Owing in reative cell, feed BCl
3And Cl
2Mist, gas BCl
3Flow be 40～90sccm, Cl
2Flow be 120～190sccm, and etching pressure is very little, be 6～10 millitorrs (1 holder=133.33 Pascals), the bottom radio frequency is 100～200W in the electricity slurry reative cell in the reative cell, the selection ratio that obtains gas etching conductive composite layer 104 and silicon oxide layer 102 thus is 8, the selection ratio of etching conductive composite layer 104 and photoresist layer 108 is 1～2.5, cause the final semiconductor device section out-of-flatness that forms, the verticality of side wall of groove or contact hole well not enough (irising out shown in the part) as ellipse among the figure.
The prior art etching conductive composite layer, because reative cell etching pressure is little, be 6～10 millitorrs, electricity slurry concentration in the reative cell is low, the selection that makes etching gas etching conductive composite layer and silicon oxide layer is than little, the selection of etching conductive composite layer and photoresist layer causes the final semiconductor device section out-of-flatness that forms than also little, and the verticality of side wall of groove or contact hole is bad; Simultaneously because reative cell etching pressure is little, make that etch rate is also corresponding to diminish, the time that causes making semiconductor device is long, and then makes the chip productive rate low.
Summary of the invention
The problem that the present invention solves provides a kind of method of etching conductive composite layer, prevents that reative cell etching pressure is too little, and causes processing procedure slow.
For addressing the above problem, the invention provides a kind of method of etching conductive composite layer, comprise the following steps: on silicon substrate, to form successively silicon oxide layer, conductive composite layer and patterning photoresist layer; To have silicon oxide layer, conductive composite layer and patterning photoresist layer silicon substrate and put into etching reaction chamber; The etching pressure of reative cell is increased to 10～30 millitorrs from 6～10 millitorrs; With the patterning photoresist layer is mask, and etching conductive composite layer is to exposing silicon oxide layer.
That etching adopts is BCl
3And Cl
2Mist, described BCl
3Flow be 40～90sccm, Cl
2Flow be 120～190sccm.
BCl
3And Cl
2The speed of mist etching conductive composite layer is 0.8～1.2 μ m/min, and the selection ratio of etching conductive composite layer and silicon oxide layer is 10～15, and the selection ratio of etching conductive composite layer and photoresist layer is 3～5.
Described conductive composite layer is aluminium, titanium and titanium nitride composite material.
The thickness of described conductive composite layer is 2～5 μ m.
Compared with prior art, the present invention has the following advantages: the present invention increases to 10～30 millitorrs with the etching pressure of reative cell from 6～10 millitorrs, electricity slurry concentration in the reative cell also can increase thereupon, the selection that makes etching gas etching conductive composite layer and silicon oxide layer is than corresponding increase, the selection of etching conductive composite layer and photoresist layer is than also corresponding increase, realize that the final semiconductor device section that forms is smooth, the verticality of side wall of groove or contact hole is good; Because etching pressure increases, and also the phase strain is big to make etch rate, realize that the time of making semiconductor device shortens, and then the chip productive rate is improved simultaneously.
Description of drawings
Figure 1A to Fig. 1 C is a prior art dry etching conductive composite layer schematic diagram;
Fig. 2 is with the design sketch of prior art with the intact conductive composite layer of scanning electron microscopy etching;
Fig. 3 is the flow chart of dry etching conductive composite layer of the present invention;
Fig. 4 A to Fig. 4 C is the schematic diagram of dry etching conductive composite layer of the present invention;
Fig. 5 is with the design sketch of the inventive method with the intact conductive composite layer of sem observation etching;
Fig. 6 A to Fig. 6 E is the schematic diagram of the present invention's dry etching conductive composite layer in Wiring technique.
Embodiment
The present invention increases to 10～30 millitorrs with the etching pressure of reative cell from 6～10 millitorrs, electricity slurry concentration in the reative cell also can increase thereupon, the selection that makes etching gas etching conductive composite layer and silicon oxide layer is than corresponding increase, the selection of etching conductive composite layer and photoresist layer is than also corresponding increase, realize that the final semiconductor device section that forms is smooth, the verticality of side wall of groove or contact hole is good; Because etching pressure increases, and also the phase strain is big to make etch rate, realize that the time of making semiconductor device shortens, and then the chip productive rate is improved simultaneously.For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Fig. 3 is the flow chart of the present invention's dry etching conductive composite layer in Wiring technique.As shown in Figure 3, execution in step S201 forms silicon oxide layer, conductive composite layer and patterning photoresist layer successively on silicon substrate; Execution in step S202 will have the silicon substrate of silicon oxide layer, conductive composite layer and patterning photoresist layer and put into etching reaction chamber; Execution in step S203 increases to 10～30 millitorrs with the etching pressure of reative cell from 6～10 millitorrs; Execution in step S204 is a mask with the patterning photoresist layer, and etching conductive composite layer is to exposing silicon oxide layer.
Fig. 4 A to Fig. 4 C is the schematic diagram of dry etching conductive composite layer of the present invention.Shown in Fig. 4 A, forming thickness with chemical vapour deposition technique on silicon substrate 200 is the silicon oxide layer 202 of 5000 dusts～7000 dusts, is used for isolation between device as interlayer dielectric layer; Be 5000W～7000W with sputtering method at power on silicon oxide layer 202, when temperature was 250 ℃～300 ℃, forming thickness was the conductive composite layer 204 of 2 μ m～6 μ m; Form the anti-reflecting layer 206 that thickness is 0.02 μ m～0.04 μ m with the plasma reinforced chemical vapour deposition mode on conductive composite layer 204, the material of described anti-reflecting layer 206 is a silicon nitride, is used to protect conductive composite layer 204 in the post-exposure process; On anti-reflecting layer 206, form the photoresist layer 208 that thickness is 2.4 μ m～4.8 μ m with spin-coating method.
In the present embodiment, the concrete thickness of silicon oxide layer 202 is 5000 dusts, 5500 dusts, 6000 dusts, 6500 dusts or 7000 dusts, preferred 6000 dusts.
In the present embodiment, sputtering power is specially 5000W, 5500W, 6000W, 6500W or 7000W, preferred sputtering power 6500W; Sputter temperature is specially 250 ℃, 260 ℃, 270 ℃, 280 ℃, 290 ℃ or 300 ℃, and preferred sputter temperature is 270 ℃.
The material of conductive composite layer 204 is the composite material of aluminium, titanium and titanium nitride; Conductive composite layer 204 thickness are specially 2 μ m, 2.5 μ m, 3 μ m, 3.5 μ m, 4 μ m, 4.5 μ m, 5 μ m, 5.5 μ m or 6 μ m; The thickness of anti-reflecting layer 206 is specially 0.02 μ m, 0.03 μ m or 0.04 μ m; The thickness of photoresist layer 208 is specially 2.4 μ m, 2.6 μ m, 2.8 μ m, 3.0 μ m, 3.2 μ m, 3.4 μ m, 3.6 μ m, 3.8 μ m, 4.0 μ m, 4.2 μ m, 4.4 μ m, 4.6 μ m or 4.8 μ m.
Shown in Fig. 4 B, photoresist layer 208 is carried out exposure-processed, the semiconductor device graph on the light shield is transferred on the photoresist layer 208, through behind the developing process, on photoresist layer 208, form photoresistance figure 207.
Shown in Fig. 4 C, the silicon substrate 200 that will have silicon oxide layer 202, conductive composite layer 204, anti-reflecting layer 206 and photoresist layer 208 is put into reative cell, is mask with photoresist layer 208, feeds BCl in reative cell
3And Cl
2Mist, the etching pressure of reative cell is increased to 10～30 millitorrs (1 holder=133.33 Pascals) from 6～10 millitorrs, the bottom radio frequency is 100～200W in the reative cell, is etched to along 207 pairs of conductive composite layers 204 of photoresistance figure and exposes silicon oxide layer 202, simultaneously etching gas BCl
3And Cl
2Can be to silicon oxide layer 202 over etchings; Because etching pressure increases, the electricity slurry concentration in the reative cell is increased, make etching gas BCl
3And Cl
2The selection of etching conductive composite layer 204 and silicon oxide layer 202 is than corresponding increase, and the selection of etching conductive composite layer 204 and photoresist layer 208 realizes that than also corresponding increase the final semiconductor device section that forms is smooth, and the conductive composite layer verticality of side wall is good; Because etching pressure increases, and also the phase strain is big to make etch rate, realize that the time of making semiconductor device shortens, and then the chip productive rate is improved simultaneously; Remove photoresist layer 208 with the wet etching method at last.
In the present embodiment, reative cell etching pressure concrete example is as 10 millitorrs, 15 millitorrs, 20 millitorrs, 25 millitorrs or 30 millitorrs.Gas BCl
3Flow be 40～90sccm, concrete flow is 40sccm, 50sccm, 60sccm, 70sccm, 80sccm or 90sccm for example; Cl
2Flow be 120～190sccm, concrete flow is 120sccm, 130sccm, 140sccm, 150sccm, 160sccm, 170sccm, 180sccm or 190sccm for example.BCl
3And Cl
2The selection ratio of mist etching conductive composite layer 204 and silicon oxide layer 202 is 10～15, is specially 10,11,12,13,14 or 15; The selection ratio of etching conductive composite layer 204 and photoresist layer 208 is 3～5, is specially 3,4 or 5.Etch rate is 0.8～1.2 μ m/min, and concrete etch rate is 0.8 μ m/min, 0.9 μ m/min, 1.0 μ m/min, 1.1 μ m/min or 1.2 μ m/min.
In the present embodiment, wet etching photoresist layer 208 required solution are organic solvent, and etch period is 50min～70min, is specially 50min, 60min or 70min, preferred 60min.
Fig. 5 is the design sketch with the intact conductive composite layer of the inventive method etching.As shown in Figure 5, be 15,000 times of conductive composite layer 204 effects of observing Fig. 4 A to Fig. 4 C etching down with scanning electron microscopy in multiplication factor, owing in reative cell, feed BCl
3And Cl
2Mist, gas BCl
3Flow be 40～90sccm, Cl
2Flow be 120～190sccm, the etching pressure of reative cell increases to 10～30 millitorrs from 6～10 millitorrs, the bottom radio frequency is 100～200W in the electricity slurry reative cell in the reative cell, the selection ratio that obtains gas etching conductive composite layer 204 and silicon oxide layer 202 thus is 10～15, the selection ratio of etching conductive composite layer 204 and photoresist layer 208 is 3～5, realize that the final semiconductor device section that forms is smooth, groove or contact hole verticality of side wall good (ellipse is irised out shown in the part among the figure).
Fig. 6 A to Fig. 6 E is the schematic diagram of the present invention's dry etching conductive composite layer in Wiring technique.As shown in Figure 6A, physical vaporous deposition formation thickness is first conductive composite layer 302 of 4 μ m～6 μ m on the silicon substrate 300 that comprises memory device, and wherein the material of first conductive composite layer 302 is aluminium copper, titanium nitride and titanium; Forming thickness with chemical vapour deposition technique on first conductive composite layer 302 is the silicon oxide layer 304 of 5000 dusts～7000 dusts, is used for isolation between device as interlayer dielectric layer; On silicon oxide layer 304, form first photoresist layer 306, first photoresist layer 306 is exposed, the via hole image on the light shield is transferred on first photoresist layer 306,, on first photoresist layer 306, form opening figure 307 through developing process.
In the present embodiment, the thickness of first conductive composite layer 302 is specially 4 μ m, 5 μ m or 6 μ m, the preferred 5 μ m of present embodiment.
The thickness of silicon oxide layer 304 is specially 5000 dusts, 5500 dusts, 6000 dusts, 6500 dusts or 7000 dusts, preferred 6000 dusts of present embodiment.
Shown in Fig. 6 B, be mask with first photoresist layer 306, along opening figure 307, dry etching silicon oxide layer 304 forms the through hole 308 that connects silicon oxide layer 304 to exposing first conductive composite layer 302 in silicon oxide layer 304; On silicon oxide layer 304, form metal level 310, and with metal level 310 filling vias 308, wherein the material of metal level 310 is tungsten, aluminium, titanium nitride or titanium with chemical vapour deposition technique.
Shown in Fig. 6 C, to exposing silicon oxide layer 304, form metal plug 309 with chemical mechanical polishing method grinding metal layer 310; Is 5000W～7000W with sputtering method at power, when temperature is 250 ℃～300 ℃, forms second conductive composite layer 312 on silicon oxide layer 304, and second conductive composite layer 312 covers metal plug 309; Forming thickness with the plasma reinforced chemical vapour deposition mode on second conductive composite layer 312 is the anti-reflecting layer 314 of 0.02 μ m～0.04 μ m, is used to protect second conductive composite layer 312 in the post-exposure process; On anti-reflecting layer 314, form second photoresist layer 316 that thickness is 2.4 μ m～4.8 μ m with spin-coating method.
In the present embodiment, sputtering power is specially 5000W, 5500W, 6000W, 6500W or 7000W, preferred sputtering power 6500W; Sputter temperature is specially 250 ℃, 260 ℃, 270 ℃, 280 ℃, 290 ℃ or 300 ℃, and preferred sputter temperature is 270 ℃.
In the present embodiment, the material of second conductive composite layer 312 is the composite material of aluminium, titanium and titanium nitride; The thickness of second conductive composite layer 312 is 2 μ m～6 μ m, and concrete thickness is 2 μ m, 2.5 μ m, 3 μ m, 3.5 μ m, 4 μ m, 4.5 μ m, 5 μ m, 5.5 μ m or 6 μ m for example.The thickness of anti-reflecting layer 314 is specially 0.02 μ m, 0.03 μ m or 0.04 μ m; The thickness of second photoresist layer 316 is specially 2.4 μ m, 2.6 μ m, 2.8 μ m, 3.0 μ m, 3.2 μ m, 3.4 μ m, 3.6 μ m, 3.8 μ m, 4.0 μ m, 4.2 μ m, 4.4 μ m, 4.6 μ m or 4.8 μ m.
Shown in Fig. 6 D, second photoresist layer 316 is carried out exposure-processed, the land pattern on the light shield is transferred on the photoresist layer 318, through behind the developing process, on second photoresist layer 316, form photoresistance figure 317.
Shown in Fig. 6 E, the silicon substrate 300 that will have each rete is put into reative cell, is mask with second photoresist layer 316, feeds BCl in reative cell
3And Cl
2Mist, the etching pressure of reative cell is increased to 10～30 millitorrs (1 holder=133.33 Pascals) from 6～10 millitorrs, the bottom radio frequency is 100～200W in the reative cell, be etched to along photoresistance figure 317 antagonistic reflex layers 314 and second conductive composite layer 312 and expose silicon oxide layer 304, simultaneously etching gas BCl
3And Cl
2Can be to silicon oxide layer 304 over etchings; Because etching pressure increases, the electricity slurry concentration in the reative cell is increased, make etching gas BCl
3And Cl
2The selection of etching second conductive composite layer 312 and anti-reflecting layer 314 is than corresponding increase, the selection of etching second conductive composite layer 312 and second photoresist layer 316 is than also corresponding increase, realize that the final semiconductor device section that forms is smooth, groove or contact hole verticality of side wall are good; Because etching pressure increases, and also the phase strain is big to make etch rate, realize that the time of making metal pad shortens, and then the chip productive rate is improved simultaneously; Remove second photoresist layer 316 with the wet etching method at last.
In the present embodiment, reative cell etching pressure concrete example is as 10 millitorrs, 15 millitorrs, 20 millitorrs, 25 millitorrs or 30 millitorrs.Gas BCl
3Flow be 40～90sccm, concrete flow is 40sccm, 50sccm, 60sccm, 70sccm, 80sccm or 90sccm for example; Cl
2Flow be 120～190sccm, concrete flow is 120sccm, 130sccm, 140sccm, 150sccm, 160sccm, 170sccm, 180sccm or 190sccm for example.BCl
3And Cl
2The selection ratio of mist etching second conductive composite layer 312 and silicon oxide layer 314 is 10～13, is specially 10,11,12 or 13; The selection ratio of etching second conductive composite layer 312 and photoresist layer 316 is 3～5, is specially 3,4 or 5.Etch rate is 0.8～1.2 μ m/min, and concrete etch rate is 0.8 μ m/min, 0.9 μ m/min, 1.0 μ m/min, 1.1 μ m/min or 1.2 μ m/min.
In the present embodiment, wet etching second photoresist layer 316 required solution are organic solvent, and etch period is 50min～70min, is specially 50min, 60min or 70min, preferred 60min.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (6)
1. the method for an etching conductive composite layer is characterized in that, comprises the following steps:
On silicon substrate, form silicon oxide layer, conductive composite layer and patterning photoresist layer successively;
The silicon substrate that will have silicon oxide layer, conductive composite layer and patterning photoresist layer is put into etching reaction chamber;
The etching pressure of reative cell is set to 10～30 millitorrs, and feeds mixing etching gas BCl
3And Cl
2
With the patterning photoresist layer is mask, and etching conductive composite layer is to exposing silicon oxide layer;
Described conductive composite layer is aluminium, titanium and titanium nitride composite material.
2. the method for etching conductive composite layer according to claim 1 is characterized in that: described BCl
3Flow be 40～90sccm, Cl
2Flow be 120～190sccm.
3. the method for etching conductive composite layer according to claim 2 is characterized in that: BCl
3And Cl
2The speed of mist etching conductive composite layer is 0.8～1.2 μ m/min.
4. the method for etching conductive composite layer according to claim 3, it is characterized in that: the selection ratio of etching conductive composite layer and silicon oxide layer is 10～15.
5. the method for etching conductive composite layer according to claim 3, it is characterized in that: the selection ratio of etching conductive composite layer and photoresist layer is 3～5.
6. the method for etching conductive composite layer according to claim 1, it is characterized in that: the thickness of described conductive composite layer is 2～5 μ m.
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|---|---|---|---|
| CN2006101480124A CN101211782B (en) | 2006-12-28 | 2006-12-28 | Method for etching conductive composite layer |
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| CN102142368B (en) * | 2010-02-01 | 2013-03-13 | 北大方正集团有限公司 | Method for planarization of wafer surface |
| US12245414B2 (en) | 2021-03-18 | 2025-03-04 | Changxin Memory Technologies, Inc. | Method of etching a memory stack by etching a blind hole |
| CN113066761B (en) * | 2021-03-18 | 2022-12-27 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1221809A (en) * | 1997-11-14 | 1999-07-07 | 西门子公司 | Method of etching aluminum-based layer |
| US5968711A (en) * | 1998-04-28 | 1999-10-19 | Vanguard International Semiconductor Corporation | Method of dry etching A1Cu using SiN hard mask |
| US6040248A (en) * | 1998-06-24 | 2000-03-21 | Taiwan Semiconductor Manufacturing Company | Chemistry for etching organic low-k materials |
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2006
- 2006-12-28 CN CN2006101480124A patent/CN101211782B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1221809A (en) * | 1997-11-14 | 1999-07-07 | 西门子公司 | Method of etching aluminum-based layer |
| US5968711A (en) * | 1998-04-28 | 1999-10-19 | Vanguard International Semiconductor Corporation | Method of dry etching A1Cu using SiN hard mask |
| US6040248A (en) * | 1998-06-24 | 2000-03-21 | Taiwan Semiconductor Manufacturing Company | Chemistry for etching organic low-k materials |
Non-Patent Citations (2)
| Title |
|---|
| US 2003/0003756 A1,全文. |
| US 2005/0003673 A1,全文. |
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