CN101206494A

CN101206494A - Voltage generator circuit

Info

Publication number: CN101206494A
Application number: CNA2006101478270A
Authority: CN
Inventors: 袁文师
Original assignee: Shanghai Beiling Co Ltd
Current assignee: Shanghai Beiling Co Ltd
Priority date: 2006-12-22
Filing date: 2006-12-22
Publication date: 2008-06-25
Anticipated expiration: 2026-12-22
Also published as: CN101206494B

Abstract

The invention discloses a voltage generator circuit, wherein, basically stable voltage which is lower than zero voltage is generated by adoption of a current mirror circuit and utilization of a characteristic that voltage on both ends of a capacitor can not be mutated; when bias voltage is arranged, the current mirror circuit in a voltage generator operates, and stable voltage is generated and inputted to a source electrode of a PMOS tube M1; two clocks which are relatively clk1 and clk2 are not overlapped with each other; the clock clk1 is taken as an input of a NAND gate through a phase inverter and the clock clk2; an output of the NAND gate is taken as control voltage of a grid electrode of the PMOS tube M1; one end of the capacitor is connected with the clock clk2; the other end of the capacitor is connected with a drain electrode of the PMOS tube M1 and taken as a voltage output end. By utilization of the characteristic that the voltage on both ends of the capacitor can not be mutated and changes of clock signals, the voltage which is lower than the zero voltage is generated.

Description

Voltage generator circuit

Technical Field

The present invention relates to a voltage generator circuit, and more particularly, to a circuit applied to a bias circuit or a clock circuit in a System On Chip (SOC).

Background

In a system-on-chip, almost all circuits have voltage generating circuits to generate proper and accurate voltages, which is very important for the whole chip. The existing application generally utilizes a reference voltage source to generate voltage, but the voltage generated by the reference voltage source cannot be lower than zero volt voltage and cannot follow clock change. Therefore, in order to generate a voltage lower than zero volts and capable of following the clock, a voltage generator, such as a multiplying voltage generator, is generally used. The known voltage generator is generally implemented by charging and discharging a switched capacitor, but the circuit is relatively complex and the adjustability is relatively poor.

Disclosure of Invention

The invention aims to provide a voltage generator circuit which can generate a voltage lower than zero volt and can adjust the generated voltage according to the change of a clock.

The voltage generator circuit includes:

a current mirror circuit for generating a stable voltage; and

an output circuit;

the voltage generated by the current mirror circuit is used as the control voltage of the output circuit;

the output circuit comprises a PMOS tube M1, a capacitor, a NAND gate and an inverter;

clock clk₁By an inverter and clock clk₂The output of the NAND gate is connected with the grid of the PMOS transistor M1; one terminal of the capacitor is connected to a clock clk₂The other end of the PMOS tube M1 is connected with the drain electrode of the PMOS tube M1 and is used as a voltage output end;

the voltage generated by the current mirror circuit is connected to the source of the PMOS transistor M1 in the output circuit.

The current mirror circuit comprises a PMOS tube M2, a PMOS tube M3, a PMOS tube M4, a PMOS tube M5, an NMOS tube M6 and an NMOS tube M7;

wherein,

the drain electrode of the PMOS tube M2 is provided with power supply voltage, the source electrode of the PMOS tube M2 is connected with the drain electrode of the PMOS tube M4, the source electrode of the PMOS tube M4 is connected with the source electrode of the NMOS tube M6, and the drain electrode of the NMOS tube M6 is grounded;

the drain electrode of the PMOS tube M3 is provided with power supply voltage, the source electrode of the PMOS tube M3 is connected with the drain electrode of the PMOS tube M5, the source electrode of the PMOS tube M5 is connected with the source electrode of the PMOS tube M7, and the drain electrode of the PMOS tube M7 is grounded;

the grid electrode of the PMOS tube M2 is connected with the grid electrode of the PMOS tube M3, and the grid electrode of the PMOS tube M4 is connected with the grid electrode of the PMOS tube M5; the grid electrodes of the PMOS transistor M2 and the PMOS transistor M4 are connected with the source electrodes thereof; the gate of the NMOS transistor M7 is connected to the drain thereof.

The capacitor is adjustable, and the output voltage can be adjusted by adjusting the capacitor.

According to the present invention, when the gate of the NMOS transistor M6 is supplied with a positive bias voltage, the current mirror circuit starts operating. At the same time, clock clk₁And clk₂The signal is converted and then input to the grid of the PMOS transistor M1, the voltage generated by the current mirror circuit is supplied to the source of the PMOS transistor M1, so that the two control the opening and the closing of the PMOS transistor M1 together, thereby determining the charging and the discharging of the parallel capacitor.

When the current mirror circuit is operated, i.e. when a positive bias voltage is applied to the gate of the NMOS transistor M6, the current mirror circuit on the left side operates to generate a positive voltage to be input to the source of the PMOS transistor M1. According to the working characteristics of the PMOS tube, when the grid voltage of the PMOS tube is lower than the source voltage, the PMOS tube is conducted, otherwise, the PMOS tube is cut off.

Therefore, when the clock clk is asserted₁And clk₂When one of the voltages is at a low level, the gate of the PMOS transistor M1 is at a high level, the PMOS transistor M1 is turned off, and the voltage across the capacitor is at a low level. When the clock clk is₁And clk₂When the voltage is high, the grid electrode of the PMOS transistor M1 is low, the PMOS transistor M1 is conducted, the source electrode and the drain electrode of the PMOS transistor M1 are equal in voltage, the capacitor is charged, and a voltage difference exists between the two ends of the capacitor. When clk is present₁When the voltage level is changed to low again, the gate of the PMOS transistor M1 is high, the PMOS transistor M1 is turned off, and the clock clk goes off₁And clk₂The voltage difference between the two ends of the capacitor does not change, and the voltage at the other end of the capacitor, namely the voltage at the output end, must change to generate the output voltage.

Due to the clock clk₁And clk₂Is a periodic clock signal, the process cycles to output a voltage at the voltage output terminal that is less than zero voltage. And the output voltage can be adjusted by adjusting the size of the capacitor.

The voltage generator circuit further comprises an NMOS tube M8, wherein the source electrode of the NMOS tube M8 is connected with the drain electrode of the NMOS tube M6, and the drain electrode of the NMOS tube M6 is grounded. When the positive bias voltage is applied to the gates of the NMOS transistor M6 and the NMOS transistor M8, the current mirror circuit starts operating.

The invention can generate voltage which is lower than zero voltage and can change according to clock signals. The circuit has simple structure and good adjustability.

Drawings

Fig. 1 is a circuit diagram of an embodiment of the present invention.

Fig. 2 is a circuit diagram of another embodiment of the present invention.

FIG. 3 is a clock timing diagram of an embodiment of the present invention.

Detailed Description

In an embodiment of the present invention, as shown in fig. 1, the left circuit is a current mirror circuit, and includes a PMOS transistor M2, a PMOS transistor M3, a PMOS transistor M4, a PMOS transistor M5, an NMOS transistor M6, and an NMOS transistor M7. The PMOS transistor M2, the PMOS transistor M4 and the NMOS transistor M7 are connected in a way that the PMOS transistor M2, the PMOS transistor M4 and the NMOS transistor M7 work in a saturation region. The right side is an output circuit which comprises a PMOS pipe M1, a capacitor, a NAND gate and an inverter. When a positive bias voltage Vbias is applied to the grid of the NMOS tube M6, the current mirror circuit starts to work, and the voltage V at the point A is_AIs a V_DD-V_DSATIn which V is_DSATIs the drain-source saturation voltage of the PMOS transistor M3.

As shown in fig. 3, the two clock signals have the same period, the same high and low levels, and the phase of the clock signals is shifted from each other and input to the output circuit. At t₀Time of day, clock clk₂At low level, clk₁Also at low level, i.e. V_DIs low, V_EIs high. Then V_BAt high level, the PMOS transistor M1 is turned off, the capacitor is not charged, and the output voltage V is_CBeing low, i.e. output voltage clk_outThe output is 0.

At t₁Time of day, clock clk₂At a high level, clk₁At a low level, i.e. V_DIs high, V_EIs high. Then V_BAt low level, the PMOS transistor M1 is turned on, and the voltage at point C is equal to the voltage at point A, i.e. V_C＝V_A＝V_DD-V_DSATOutput voltage clk_outThe output is a high voltage.

At t₂Time of day, clock clk₂At low level, clk₁At a low level, i.e. V_DIs low, V_EIs high. Then V_BThe high voltage level turns off the PMOS transistor M1. Since the voltage across the capacitor cannot jump, the voltage at point C decreases, i.e. the output voltage clk_outA negative voltage is output.

At t₃Time of day, clock clk₂At low level, clk₁At a high level, i.e. V_DIs low, V_EIs high. Then V_BAt high level, the PMOS transistor M1 is turned off and the output voltage clk_outA negative voltage is maintained.

At time t₄Clock clk₂At a high level, clk₁At a high level, i.e. V_DIs high, V_EIs low. Then V_BThe voltage level is high, and the PMOS transistor M1 is cut off. Since the voltage across the capacitor cannot jump, the voltage at point C rises, i.e. the output voltage clk_outA positive voltage is output.

At time t₅Clock clk₂At a high level, clk₁At a low level, i.e. V_DIs high, V_EIs high. Then V_BThe voltage level is low, and the PMOS transistor M1 is turned on. Output voltage clk_outA positive voltage is still output.

At time t₆Clock clk₂At low level, clk₁At a low level, i.e. V_DIs low, V_EIs high. Then V_BThe high voltage level turns off the PMOS transistor M1. Since the voltage across the capacitor cannot jump, the voltage at point C decreases, i.e. the output voltage clk_outA negative voltage is output.

At time t₇Clock clk₂At low level, clk₁At a high level, i.e. V_DIs low, V_EIs low. Then V_BThe voltage level is high, and the PMOS transistor M1 is cut off. Output voltage clk_outA positive voltage is still output.

Later, at clock clk₁And clk₂Under the cyclic action of (1), the output voltage clk_outAnd outputting the positive and negative staggered voltage. Its period following the clock clk₁And clk₂And its output voltage can be adjusted by changing the size of the capacitor.

In another embodiment of the present invention, as shown in fig. 2, the current mirror circuit on the left side includes a PMOS transistor M2, a PMOS transistor M3, a PMOS transistor M4, a PMOS transistor M5, an NMOS transistor M6, an NMOS transistor M7, andand an NMOS transistor M8. When positive bias voltages Vbias and Vbias2 are applied to the gates of NMOS transistor M6 and NMOS transistor M8, the current mirror circuit starts operating. Similarly, at clock clk₁And clk₂Under the cyclic action of (1), the output voltage clk_outAnd outputting the positive and negative staggered voltage. Its period following the clock clk₁And clk₂And its output voltage can be adjusted by changing the size of the capacitor.

It should be understood that modifications and substitutions apparent to those skilled in the art are considered to be within the scope of the present invention. For example, clock clk₁The input is not through an inverter but directly into a nand gate.

Claims

1. A voltage generator circuit, comprising:

a current mirror circuit for generating a stable voltage; and

an output circuit;

clock clk₁By an inverter and clock clk₂Together as two inputs to a NAND gate, the output of the NAND gateThe output end of the PMOS tube M1 is connected with the grid electrode of the PMOS tube M1; one terminal of the capacitor is connected to a clock clk₂The other end of the PMOS tube M1 is connected with the drain electrode of the PMOS tube M1 and is used as a voltage output end;

2. The voltage generator circuit of claim 1, wherein:

wherein,

3. The voltage generator circuit of claim 2, wherein the capacitance is adjustable.

4. The voltage generator circuit as claimed in claim 2, further comprising an NMOS transistor M8, wherein the source of the NMOS transistor M8 is connected to the drain of the NMOS transistor M6, and the drain of the NMOS transistor M6 is grounded.