CN103413568B - Reference voltage provides circuit - Google Patents
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- CN103413568B CN103413568B CN201310371208.XA CN201310371208A CN103413568B CN 103413568 B CN103413568 B CN 103413568B CN 201310371208 A CN201310371208 A CN 201310371208A CN 103413568 B CN103413568 B CN 103413568B
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Abstract
A kind of reference voltage provides circuit, including: oscillator, the first electric charge pump, the second electric charge pump, mu balanced circuit, testing circuit, counting circuit and switching circuit, switching circuit is suitable to send the first clock signal that oscillator exports to the first electric charge pump in being read memory；First clock signal is sent to the second electric charge pump in time threshold after read operation, after the time threshold after read operation, the second clock signal that oscillator exports is sent to the second electric charge pump；First electric charge pump is suitable to export the first voltage according to the first clock signal；Described second electric charge pump is suitable to, when after the triggering signal receiving the output of described testing circuit, export the second voltage according to the first clock signal or second clock signal, when, after the control signal receiving the output of described counting circuit, stopping exporting described second voltage；Mu balanced circuit is suitable to according to the first voltage or the second voltage output reference voltage.Reference voltage of the present invention provides circuit to reduce the power consumption of circuit.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a reference voltage providing circuit.
Background
With the development of semiconductor technology, memories (memories) are widely used in various computer systems. The memory is a memory device in a computer system for storing programs and data, and all information in the computer, including input raw data, computer programs, intermediate operation results and final operation results, can be stored in the memory, and the memory stores and reads data according to the position designated by the controller.
In order to realize a read operation of a memory, a stable operating voltage needs to be supplied to the memory. Fig. 1 shows a schematic diagram of a reference voltage supply circuit of the prior art. As shown in fig. 1, the reference voltage supply circuit may include: an oscillator 1 and a charge pump 2. The oscillator 1 is adapted to provide a clock signal CLK to the charge pump 2; the charge pump 2 is adapted to output a reference voltage Vref under control of the clock signal CLK. The reference voltage Vref is output to a memory under the control of a control circuit in the memory as a working voltage at the time of the memory read operation.
In order to ensure that the memory can correctly perform a read operation, a reference voltage providing circuit in the prior art is always in an operating state, that is, the reference voltage providing circuit always stably outputs a reference voltage no matter whether the memory is in a read operation process, so that power consumption of the memory is large when the memory is not subjected to the read operation.
Disclosure of Invention
The invention solves the problem of large power consumption of the memory in the prior art.
To solve the above problems, the present invention provides a reference voltage providing circuit, adapted to provide a reference voltage to a memory, comprising: an oscillator, a first charge pump, a second charge pump, a voltage stabilizing circuit, a detection circuit, a counting circuit and a switching circuit,
the oscillator is suitable for outputting a first clock signal in the process of reading the memory and within a time threshold after the reading operation is finished, otherwise, outputting a second clock signal, wherein the frequency of the first clock signal is greater than that of the second clock signal;
the switching circuit is adapted to send the first clock signal to the first charge pump during a read operation of a memory; the switching circuit is further adapted to send the first clock signal to the second charge pump within a time threshold after the end of the read operation, and send the second clock signal to the second charge pump after the time threshold after the end of the read operation;
the first charge pump is suitable for outputting a first voltage through an output end of the first charge pump under the control of the first clock signal;
the second charge pump is suitable for outputting a second voltage through the output end of the second charge pump under the control of the first clock signal or the second clock signal after receiving the trigger signal output by the detection circuit; the second charge pump is also suitable for stopping outputting the second voltage after receiving the control signal output by the counting circuit, and the voltage value of the second voltage is greater than that of the first voltage;
the input end of the voltage stabilizing circuit is connected with the output end of the first charge pump and the output end of the second charge pump, and the output end of the voltage stabilizing circuit is suitable for outputting the reference voltage;
the detection circuit is connected with the input end of the voltage stabilizing circuit and is suitable for outputting the trigger signal when the voltage value of the input end of the voltage stabilizing circuit is smaller than the voltage threshold value;
the counting circuit is adapted to be triggered by the trigger signal, count the first clock signal or the second clock signal, and generate the control signal when a count value equals a count threshold.
Optionally, the voltage stabilizing circuit includes: a pass transistor and a voltage source circuit,
the voltage source circuit is suitable for outputting starting voltage to the transmission transistor, and the voltage value of the starting voltage is larger than the sum of the threshold voltage of the transmission transistor and the reference voltage;
the first end of the transmission transistor is used as the input end of the voltage stabilizing circuit, and the second end of the transmission transistor is used as the output end of the voltage stabilizing circuit; the control end of the transmission transistor is suitable for inputting the starting voltage.
Optionally, the transmission transistor is an NMOS transistor, a drain of the NMOS transistor is used as the first end, a source of the NMOS transistor is used as the second end, and a gate of the NMOS transistor is used as the control end.
Optionally, the detection circuit includes: the capacitive reactance detection circuit comprises a first capacitive reactance element, a second capacitive reactance element, a detection transistor and a current source;
the first end of the first capacitive reactance element is suitable for being connected with the input end of the voltage stabilizing circuit, and the second end of the first capacitive reactance element is connected with the first end of the second capacitive reactance element and the control end of the detection transistor;
the second end of the second capacitive reactance element is grounded;
the first end of the detection transistor is suitable for being connected with a first power line, and the second end of the detection transistor is suitable for being connected with the first end of the current source and outputting the trigger signal;
the second end of the current source is suitable for being connected with a second power line.
Optionally, the detection transistor is a PMOS transistor, a drain of the PMOS transistor is used as the first end of the detection transistor, a source of the PMOS transistor is used as the second end of the detection transistor, and a gate of the PMOS transistor is used as the control end of the detection transistor.
Optionally, the voltage threshold is greater than the reference voltage.
Optionally, the count threshold is related to a voltage value of the second voltage, a duty ratio of the first clock signal and the second clock signal.
Optionally, the switching circuit includes: a control circuit, a first selection circuit and a second selection circuit,
the first selection circuit is suitable for selecting the first clock signal to be output to the first charge pump under the control of a reading operation control signal;
the control circuit is suitable for outputting a first selection signal within a time threshold value after the end of reading operation on the memory and outputting a second selection signal after the time threshold value after the end of reading operation;
the second selection circuit is adapted to output a first clock signal to the second charge pump under control of the first selection signal and a second clock signal to the second charge pump under control of the second selection signal.
Optionally, the control circuit includes: the circuit comprises an inverter, a delay unit and an AND gate;
the input end of the phase inverter is suitable for receiving a reading operation control signal, and the output end of the phase inverter is connected with the first input end of the AND gate;
the input end of the delay unit is suitable for receiving the reading operation control signal, the output end of the delay unit is connected with the second input end of the AND gate, and the delay time of the delay unit is the time threshold;
and the output end of the AND gate is suitable for outputting the first selection signal or the second selection signal.
Optionally, the time threshold is in a range of 4 to 8 cycles of the first clock signal.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the reference voltage supply circuit of the technical scheme of the invention generates stable reference voltage by two charge pumps. In the process of reading the memory, the first charge pump is controlled to output a first voltage through a first clock signal, and after the memory is read, the first charge pump stops working. And outputting a second voltage under the control of the first clock signal by a second charge pump within a time threshold after the reading operation of the memory is finished, and outputting the second voltage under the control of a second clock signal with a smaller frequency after the reading operation of the memory is finished. In addition, the second charge pump stops working after receiving the control signal generated by the counting circuit. Compared with the prior art, the two charge pumps in the reference voltage supply circuit are not always in working states, so that the power consumption of the whole circuit is greatly reduced.
In an alternative, the second charge pump outputs the second voltage based on the first clock signal within a time threshold after a read operation on the memory ends, and outputs the second voltage based on the second clock signal after the time threshold after the read operation ends. The time threshold ranges from 4 to 8 cycles of the first clock signal, and the voltage value of the second voltage output by the second charge pump based on the first clock signal is smaller than the voltage value of the second voltage output by the second charge pump based on the second clock signal, so that the power consumption of the circuit in the time threshold after the end of the reading operation is further reduced, that is, the power consumption of the memory is further reduced.
Drawings
FIG. 1 is a schematic diagram of a prior art reference voltage providing circuit;
FIG. 2 is a schematic diagram of a reference voltage providing circuit according to an embodiment of the present invention;
FIG. 3 is a circuit schematic of the voltage regulator circuit of FIG. 2;
FIG. 4 is a circuit schematic of the circuit of FIG. 2;
FIG. 5 is a circuit schematic of the switching circuit of FIG. 2;
FIG. 6 is a timing diagram of various signals of the switching circuit shown in FIG. 5;
FIG. 7 is a timing diagram of various signals of the reference voltage providing circuit according to the embodiment of the present invention.
Detailed Description
As described in the background art, in the prior art, the charge pump of the reference voltage supply circuit is always in an operating state during a read operation of the memory or during a read operation of the memory, so that the power consumption of the circuit is large.
The invention provides a reference voltage providing circuit, which is characterized in that two charge pumps which separately and independently work and corresponding control parts are arranged, so that the two charge pumps can be closed under the condition of not influencing the normal work of a subsequent circuit, and the power consumption of the circuit is reduced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 shows a schematic diagram of a reference voltage supply circuit according to the present invention. The reference voltage providing circuit is suitable for providing a reference voltage to the memory to realize the reading operation of the memory. Referring to fig. 2, the reference voltage supply circuit includes: the circuit comprises an oscillator 10, a first charge pump 20, a second charge pump 30, a voltage stabilizing circuit 40, a detection circuit 50, a counting circuit 60 and a switching circuit 70. In particular, the amount of the solvent to be used,
the oscillator 10 is adapted to output a first clock signal CLK _ a during a read operation of the memory and within a time threshold after the read operation is completed, and otherwise output a second clock signal CLK _ S, wherein a frequency of the first clock signal CLK _ a is greater than a frequency of the second clock signal CLK _ S.
The switching circuit 70 is adapted to send the first clock signal CLK _ a to the first charge pump 20 during a read operation of the memory; the switching circuit 70 is further adapted to send the first clock signal CLK _ a to the second charge pump 30 within a time threshold after the end of the read operation and to send the second clock signal CLK _ S to the second charge pump 30 after the time threshold after the end of the read operation.
The first charge pump 20 is adapted to output a first voltage through an output of the first charge pump 20 under control of the first clock signal CLK _ a.
The second charge pump 30 is adapted to output a second voltage through the output terminal of the second charge pump 30 under the control of the first clock signal CLK _ a or the second clock signal CLK _ S after receiving the trigger signal EN output by the detection circuit 50; the second charge pump 30 is further adapted to stop outputting the second voltage after receiving the control signal ST output by the counting circuit 60, wherein the voltage value of the second voltage is greater than the voltage value of the first voltage.
An input terminal PWL of the voltage stabilizing circuit 40 is connected to the output terminal of the first charge pump 20 and the output terminal of the second charge pump 30, and an output terminal of the voltage stabilizing circuit 40 is adapted to output the reference voltage VREF.
The detection circuit 50 is connected to the input terminal PWL of the voltage stabilizing circuit 40, and is adapted to output the trigger signal EN when the voltage value of the input terminal PWL of the voltage stabilizing circuit 40 is smaller than the voltage threshold.
Specifically, the voltage threshold is greater than the reference voltage VREF. The voltage threshold may be reasonably set according to actual needs and actual structures of the circuit, for example, a voltage difference between the voltage threshold and the reference voltage VREF may be set to 0.2V, which is merely an example and is not limited in this disclosure.
The counting circuit 60 is adapted to be triggered by the trigger signal EN, to count the first clock signal CLK _ a or the second clock signal CLK _ S, and to generate the control signal ST when the count value equals a count threshold value.
In particular, the count threshold is related to a voltage value of the second voltage and a duty cycle of a second clock signal. For example, when the voltage value of the second voltage output by the second charge pump 30 is larger and the duty ratio of the second clock signal is larger, the count threshold value is also larger; conversely, the count threshold is smaller as the second voltage value output by the second charge pump 30 is smaller and the duty ratio of the second clock signal is also smaller. This is because the larger the duty ratio of the second clock signal is, the longer the charging time of the second charge pump 30 is, and the larger the second voltage value generated by the second charge pump is, the longer the time for the voltage value at the input terminal PWL of the voltage stabilizing circuit to fall to the voltage threshold value is, and the larger the count threshold value is; conversely, the smaller the duty cycle of the second clock signal, the shorter the charging time of the second charge pump 30, and the smaller the second voltage value it generates, the shorter the time for the voltage value at the input PWL of the regulator circuit to drop to the voltage threshold, and therefore the shorter the count threshold.
The first charge pump 20 and the second charge pump 30 of the reference voltage providing circuit of the present invention are not always in the working state, but stop working under the control of the corresponding signal, and compared with the prior art in which the charge pumps are always in the working state, the power consumption of the reference voltage providing circuit of the present invention is effectively reduced.
Referring to fig. 3, the voltage stabilizing circuit includes: pass transistor M1 and voltage source circuit 401.
The voltage source circuit 401 is adapted to output a start-up voltage V0 to the pass transistor M1, the voltage value of the start-up voltage V0 being greater than the sum of the threshold voltage VT of the pass transistor M1 and the reference voltage VREF;
a first end of the pass transistor M1 is used as an input end PWL of the voltage stabilizing circuit and is suitable for receiving the voltage output by the voltage stabilizing circuit, and a second end of the pass transistor M1 is used as an output end of the voltage stabilizing circuit; the control terminal of the pass transistor M1 is adapted to input the start voltage V0.
In a specific example, the pass transistor M1 may be an NMOS transistor, and the drain of the NMOS transistor serves as a first terminal, the source of the NMOS transistor serves as a second terminal, and the gate of the NMOS transistor serves as a control terminal. In order to reduce the voltage value of the starting voltage V0 and reduce the power consumption of the circuit, the pass transistor M1 may be a low threshold NMOS transistor, although the invention is not limited thereto. The voltage source circuit 401 may be implemented by using an existing voltage supply circuit, for example, the voltage source circuit 401 may be a charge pump.
In the reference voltage providing circuit of the present invention, the time threshold ranges from 4 cycles of the first clock signal to 8 cycles of the first clock signal. The magnitude of the time threshold is related to the voltage value of the second voltage output by the second charge pump 30 based on the first clock signal CLK _ a. When the voltage value of the second voltage outputted by the second charge pump 30 under the control of the first clock signal CLK _ a is greater than the voltage value of the first voltage and the pass transistor M1 in the stabilizing circuit 40 is in a saturation state, the switching circuit 70 may output the second clock signal CLK _ S to the second charge pump, so that the second charge pump 30 outputs the second voltage under the control of the second clock signal CLK _ S.
It will be appreciated by those skilled in the art that the time threshold is very short in duration since it ranges from 4 to 8 cycles of the first clock signal. The voltage value of the second voltage output by the second charge pump 30 based on the first clock signal CLK _ a is smaller than the voltage value of the second voltage output by the second charge pump 30 based on the second clock signal CLK _ S. In this way, the power consumption of the second charge pump 30 based on the first clock signal during the time threshold is smaller than the power consumption of the second charge pump 30 based on the second clock signal during the time threshold, so that the power consumption of the reference voltage providing circuit of the present invention is further reduced.
Referring to fig. 4, the detection circuit includes: a first capacitive reactance element C1, a second capacitive reactance element C2, a detection transistor MP1 and a current source I1.
The first end of the first capacitive reactance element C1 is suitable for being connected with the input end PWL of the voltage stabilizing circuit, and the second end is connected with the first end of the second capacitive reactance element C2 and the control end of the detection transistor MP 1;
the second end of the second capacitive reactance element C2 is grounded;
the first terminal of the detection transistor MP1 is adapted to be connected to a first power line VDD, and the second terminal is adapted to be connected to the first terminal of the current source I1 and adapted to output the trigger signal EN;
the second terminal of the current source I1 is adapted to be connected to a second power line, which in this embodiment provides a voltage of 0V.
In a specific example, the detecting transistor MP1 can be a PMOS transistor, the drain of the PMOS transistor serves as the first terminal of the detecting transistor MP1, the source of the PMOS transistor serves as the second terminal of the detecting transistor MP1, and the gate of the PMOS transistor serves as the control terminal of the detecting transistor MP 1.
With continued reference to fig. 4, the detection circuit may further include a first delay unit 501, where the first delay unit 501 is adapted to delay and output the trigger signal EN, and for convenience of description, the delayed signal is labeled as EN _ D. The first delay unit 501 may be implemented by using an existing delay circuit, for example, an even number of inverters, such as the first inverter INV1 and the second inverter INV2, connected in sequence to implement delay or a buffer to implement delay, which is not limited by the present invention.
In a specific example, the first capacitive reactance element C1 and the second capacitive reactance element C2 are both MOS capacitors. Of course, the present invention is not limited to this, and other existing capacitive reactance elements may be used for the first capacitive reactance element C1 and the second capacitive reactance element C2.
Referring to fig. 5, the switching circuit includes: a control circuit 701, a first selection circuit MUX1 and a second selection circuit MUX 2.
The first selection circuit MUX1 is adapted to select the first clock signal CLK a to be output to the first charge pump 20 during a read operation on the memory. Specifically, the first selection circuit MUX1 has a first input terminal adapted to receive the first clock signal CLK _ a, a second input terminal connected to ground, a control terminal adapted to receive the read operation control signal ACT _ EN, and an output terminal connected to the first charge pump 20.
The control circuit 701 is adapted to output a first selection signal st1 within a time threshold after the end of a read operation on the memory, and to output a second selection signal st2 after the time threshold after the end of the read operation. The time threshold may refer to a stage t1 shown in fig. 7, where the stage t1 includes 4 cycles of the first clock signal CLK _ a, and of course, in other examples, the time threshold may be set to other time values as needed, which is not limited in the present invention.
The second selection circuit MUX2 is adapted to output a first clock signal CLK _ a to the second charge pump 30 under the control of the first selection signal st1 and output a second clock signal CLK _ S to the second charge pump 30 under the control of the second selection signal st 2. In particular, the second selection circuit MUX2 has a first input terminal adapted to receive the first clock signal CLK _ a, a second input terminal adapted to receive the second clock signal CLK _ S, a control terminal adapted to receive the first selection signal st1 or the second selection signal st2, and an output terminal connected to the second charge pump 30.
The first selection circuit MUX1 and the second selection circuit MUX2 may be implemented by using an existing selection circuit, which is not limited in the present invention.
With continued reference to fig. 5, the control circuit 701 includes: inverter INV3, delay unit 710, AND gate AND 1. Wherein,
the input end of the inverter INV3 is suitable for receiving a read operation control signal ACT _ EN, AND the output end is connected to the first input end of the AND gate AND 1; an output end of the inverter INV3 is adapted to output an inverted signal ACT _ I of the read operation control signal ACT _ EN.
The input end of the delay unit 710 is adapted to receive the read operation control signal ACT _ EN, the output end of the delay unit 710 is connected to the second input end of the AND gate AND1, AND the delay time of the delay unit 710 is the time threshold, i.e. the delay time of the delay unit 710 ranges from 4 cycles of the first clock signal CLK _ a to 8 cycles of the first clock signal CLK _ a. An output terminal of the delay unit 710 is adapted to output a delay signal ACT _ D of the read operation control signal ACT _ EN.
Similar to the first delay unit 501, the delay unit 710 can also be implemented by using an existing circuit structure, and is not described herein again.
An output terminal of the AND gate AND1 is adapted to output the first selection signal st1 or the second selection signal st 2.
Fig. 6 shows a timing diagram of respective signals of the switching circuit shown in fig. 5. Referring to fig. 6, a signal ACT _ I is an inverted signal of the read operation control signal ACT _ EN; the signal ACT _ D is a delayed signal of the read operation control signal ACT _ EN. The signal ACT _ I AND the signal ACT _ D, which are simultaneously in a high level state, output a first selection signal st1 in a high level through the AND gate AND 1; then, since the signal ACT _ D becomes a low level, the AND gate AND1 outputs the second selection signal st2 of a low level.
Referring to fig. 5, when the read operation control signal ACT _ EN is at a high level, the first selection circuit MUX1 selects the first clock signal CLK _ a to output to the first charge pump 20 under the control of the read operation control signal ACT _ EN at the high level. The first charge pump 20 outputs a first voltage under the control of the first clock signal CLK _ a, as shown in fig. 7, and the first charge pump 20 outputs a first voltage of 2.5V during a period T1. When the read operation control signal ACT _ EN goes low, the first selection circuit MUX1 outputs the 0V voltage at the second input terminal, and the first charge pump 20 stops operating. Of course, the second input terminal of the first selection circuit MUX1 may receive a high level, so that the first selection circuit MUX1 outputs a high level after the read operation control signal ACT _ EN goes low, but the first charge pump 20 still stops operating. Thereby achieving the purpose of reducing power consumption.
With continued reference to fig. 5 AND 6, the read operation control signal ACT _ EN changed to the low level outputs the inverted signal ACT _ I of the high level after passing through the inverter INV3, AND the delay signal ACT _ D is still at the high level for the time threshold under the delay action of the delay unit 710, so that both the inverted signal ACT _ I AND the delay signal ACT _ D are at the high level for the time threshold, AND thus the first selection signal ACT 39st 1 of the high level is output after passing through the AND gate AND 1. The high-level first selection signal st1 causes the second selection circuit MUX2 to output a first clock signal CLK _ a to the second charge pump 30, and the second charge pump 30 outputs a second voltage having a voltage value that can refer to a voltage at a point a shown in fig. 7 under the control of the first clock signal CLK _ a.
With continued reference to fig. 5 to 7, after the time threshold, the control circuit 701 outputs the second selection signal st2 of a low level, thereby causing the second selection circuit MUX2 to output the second clock signal CLK _ S to the second charge pump 30, and the second charge pump 30 outputs a second voltage under the control of the second clock signal CLK _ S, the voltage value of which may refer to the voltage at point C shown in fig. 7.
The working principle of the reference voltage providing circuit according to the present invention will be described in further detail with reference to the accompanying drawings.
It should be noted that, the dynamic state shown in fig. 7 refers to a process of performing a read operation on the memory, the static state refers to a process of not performing a read operation on the memory, and the stage t1 indicates a time threshold after the read operation on the memory is completed, where the time of the time threshold is the duration of the first selection signal st 1. In addition, the count threshold is set to 10, and the start voltage received by the control terminal of the pass transistor M1 in the regulating circuit 40 is set to 3.3V.
In a dynamic process, the oscillator 10 outputs a first clock signal CLK _ a; the switching circuit 70 outputs the first clock signal CLK _ A to the first charge pump 20, and the first charge pump 20 outputs a first voltage to the stabilizing circuit 40 under the control of the first control signal CLK _ A. As shown in fig. 7, the input terminal PWL of the regulating circuit 40 receives a voltage of 2.5V during the period T1. The voltage value of the first voltage is the working voltage required for reading the memory, that is, the reference voltage output by the reference voltage providing circuit of the present invention is 2.5V.
Referring to fig. 3, in a dynamic process, the first terminal of the pass transistor M1 receives a first voltage of 2.5V, the control terminal of the pass transistor M1 receives a start voltage greater than the sum of the threshold voltage VT of the pass transistor M1 and the reference voltage VREF, i.e., 3.3V, so that the pass transistor M1 is in a saturation region, and the second terminal of the pass transistor M1 transmits the first voltage received by the first terminal to the second terminal to be output as the reference voltage VREF.
In the period t1 after the dynamic process is finished, that is, in the time threshold after the reading operation of the memory is finished, the detection circuit 50 detects that the voltage value of the input terminal PWL of the voltage stabilizing circuit 40 is 2.5V, which is smaller than the voltage threshold, and therefore, the detection circuit 50 outputs the trigger signal EN to the second charge pump 30. The second charge pump 30 receives the trigger signal EN; since the oscillator 10 still outputs the first clock signal CLK _ a during the period t 1; the switching unit 70 outputs the first clock signal CLK _ a to the second charge pump 30, so that the second charge pump 30 outputs a second voltage to the input terminal PWL of the stabilizing circuit 40 under the control of the first control signal CLK _ a. As shown in fig. 7, the input terminal PWL of the regulating circuit 40 receives the second voltage at the point a at the end of the t1, and the voltage at the point a is about 3.5V.
At the stage t1, the counting circuit 60 is also cleared and starts counting the first clock signal CLK _ a under the trigger of the trigger signal EN, but since the first clock signal CLK _ a has a short period of only four periods, the count value of the counting circuit 60 is smaller than the count threshold, and therefore, the counting circuit 60 does not output the control signal ST. However, it will be understood by those skilled in the art that during the period t1, the counting circuit 60 may generate the control signal ST to turn off the second charge pump 30 in due time by setting the counting threshold value appropriately, so as to prevent the second charge pump 30 from outputting a high second voltage under the control of the first clock signal CLK _ a, thereby causing excessive power consumption of the circuit.
With reference to fig. 2 to 7, in the static process after the stage t1 after the dynamic process is ended, the oscillator 10 outputs a second clock signal CLK _ S, and the frequency of the second clock signal CLK _ S is smaller than the frequency of the first clock signal CLK _ a. The switching circuit 70 outputs the second clock signal CLK _ S to the second charge pump 30.
When the detection circuit 50 detects that the voltage value of the input terminal PWL of the stabilizing circuit 40 is smaller than the voltage threshold, such as the voltage at point B shown in fig. 7, the detection circuit 50 outputs a trigger signal EN to the counting circuit 60 and the second charge pump 30. The second charge pump 30 receives the trigger signal EN and outputs a second voltage to the input terminal PWL of the voltage stabilizing circuit 40 under the control of the second clock signal CLK _ S.
Referring to fig. 7, the duration of the active pulse (i.e., the high level signal) of the second clock signal CLK _ S is long, and thus, the voltage value of the second voltage output by the second charge pump 30 is greater than the voltage value of the first voltage. In the static process, the input terminal PWL of the regulating circuit 40 may receive the voltage value at the point C in fig. 7, for example, the voltage value at the point C is 5V.
Referring to fig. 2, the counting circuit 60 clears and counts the second clock signal CLK _ S under the control of the trigger signal output from the detection circuit 50, and outputs a control signal ST to the second charge pump 30 when the count value is equal to a count threshold 10. The second charge pump 30 stops operating based on the control signal ST, that is, stops outputting the second voltage to the input terminal PWL of the voltage stabilizing circuit 40. The voltage value at the input terminal PWL of the voltage stabilizing circuit 40 slowly decreases until the detection circuit 50 detects that the voltage value at the input terminal PWL of the voltage stabilizing circuit 40 is smaller than the voltage threshold value, and the trigger signal EN is output again. The second charge pump 30 and the counting circuit 60 start to work again, and the working process is the same as the foregoing process, which is not described again here.
Referring to fig. 3 and 7, in a static process after the t1 phase, the first terminal of the pass transistor M1 receives a voltage value between the voltage threshold and the second voltage as shown by C, the control terminal of the pass transistor M1 receives a start voltage with a voltage value of 3.3V, the pass transistor M1 is in a linear region, and the second terminal of the pass transistor M1 can output a reference voltage with a voltage value of 2.5V by setting reasonable parameters of the pass transistor M1.
In summary, the reference voltage providing circuit of the present invention operates under the control of the first clock signal by the first charge pump when performing a read operation on the memory; within a time threshold value after the reading operation of the memory is finished, the second charge pump works under the control of a first clock signal; and after a time threshold value after the end of the reading operation on the memory, the second charge pump works under the control of a second clock signal. Because the period of the first clock signal CLK _ a is less in the time threshold after the reading operation of the memory is finished, the voltage value of the second voltage output by the second charge pump is greater than the voltage value of the first voltage, but is less than the voltage value of the second voltage output by the second charge pump under the control of the second clock signal CLK _ S, and thus the power consumption of the circuit when the circuit is switched from the dynamic state to the static state is effectively reduced.
Moreover, because the frequency of the second clock signal is less than that of the first clock signal, and the second charge pump stops working after receiving the control signal output by the counting circuit, the power consumption of the second charge pump in the static process after the time threshold is very small, and the power consumption of the reference voltage providing circuit in the static process is greatly reduced. In addition, the reference voltage providing circuit has a simple structure, is easy to realize, and is also beneficial to the integration of the circuit.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A reference voltage providing circuit adapted to provide a reference voltage to a memory, comprising: an oscillator, a first charge pump, a second charge pump, a voltage stabilizing circuit, a detection circuit, a counting circuit and a switching circuit,
the oscillator is suitable for outputting a first clock signal in the process of reading the memory and within a time threshold after the reading operation is finished, otherwise, outputting a second clock signal, wherein the frequency of the first clock signal is greater than that of the second clock signal;
the switching circuit is adapted to send the first clock signal to the first charge pump during a read operation of a memory; the switching circuit is further adapted to send the first clock signal to the second charge pump within a time threshold after the end of the read operation, and send the second clock signal to the second charge pump after the time threshold after the end of the read operation;
the first charge pump is suitable for outputting a first voltage through an output end of the first charge pump under the control of the first clock signal;
the second charge pump is suitable for outputting a second voltage through the output end of the second charge pump under the control of the first clock signal or the second clock signal after receiving the trigger signal output by the detection circuit; the second charge pump is also suitable for stopping outputting the second voltage after receiving the control signal output by the counting circuit, and the voltage value of the second voltage is greater than that of the first voltage;
the input end of the voltage stabilizing circuit is connected with the output end of the first charge pump and the output end of the second charge pump, and the output end of the voltage stabilizing circuit is suitable for outputting the reference voltage;
the detection circuit is connected with the input end of the voltage stabilizing circuit and is suitable for outputting the trigger signal when the voltage value of the input end of the voltage stabilizing circuit is smaller than the voltage threshold value;
the counting circuit is adapted to be triggered by the trigger signal, count the first clock signal or the second clock signal, and generate the control signal when a count value equals a count threshold.
2. The reference voltage providing circuit of claim 1 wherein said voltage regulator circuit comprises: a pass transistor and a voltage source circuit,
the voltage source circuit is suitable for outputting starting voltage to the transmission transistor, and the voltage value of the starting voltage is larger than the sum of the threshold voltage of the transmission transistor and the reference voltage;
the first end of the transmission transistor is used as the input end of the voltage stabilizing circuit, and the second end of the transmission transistor is used as the output end of the voltage stabilizing circuit; the control end of the transmission transistor is suitable for inputting the starting voltage.
3. The reference voltage providing circuit of claim 2 wherein the pass transistor is an NMOS transistor having a drain as a first terminal, a source as a second terminal, and a gate as a control terminal.
4. The reference voltage providing circuit of claim 1 wherein the detection circuit comprises: the capacitive reactance detection circuit comprises a first capacitive reactance element, a second capacitive reactance element, a detection transistor and a current source;
the first end of the first capacitive reactance element is suitable for being connected with the input end of the voltage stabilizing circuit, and the second end of the first capacitive reactance element is connected with the first end of the second capacitive reactance element and the control end of the detection transistor;
the second end of the second capacitive reactance element is grounded;
the first end of the detection transistor is suitable for being connected with a first power line, and the second end of the detection transistor is suitable for being connected with the first end of the current source and outputting the trigger signal;
the second end of the current source is suitable for being connected with a second power line.
5. The reference voltage providing circuit of claim 4 wherein the sense transistor is a PMOS transistor having a drain as the first terminal of the sense transistor, a source as the second terminal of the sense transistor, and a gate as the control terminal of the sense transistor.
6. The reference voltage providing circuit of claim 1 wherein the voltage threshold is greater than the reference voltage.
7. The reference voltage providing circuit of claim 1 wherein the count threshold is related to a voltage value of the second voltage, a duty cycle of the first clock signal and the second clock signal.
8. The reference voltage providing circuit of claim 1 wherein the switching circuit comprises: a control circuit, a first selection circuit and a second selection circuit,
the first selection circuit is suitable for selecting the first clock signal to be output to the first charge pump under the control of a reading operation control signal;
the control circuit is suitable for outputting a first selection signal within a time threshold value after the end of reading operation on the memory and outputting a second selection signal after the time threshold value after the end of reading operation;
the second selection circuit is adapted to output a first clock signal to the second charge pump under control of the first selection signal and a second clock signal to the second charge pump under control of the second selection signal.
9. The reference voltage providing circuit of claim 8 wherein the control circuit comprises: the circuit comprises an inverter, a delay unit and an AND gate;
the input end of the phase inverter is suitable for receiving a reading operation control signal, and the output end of the phase inverter is connected with the first input end of the AND gate;
the input end of the delay unit is suitable for receiving the reading operation control signal, the output end of the delay unit is connected with the second input end of the AND gate, and the delay time of the delay unit is the time threshold;
and the output end of the AND gate is suitable for outputting the first selection signal or the second selection signal.
10. The reference voltage providing circuit of claim 1 wherein the time threshold is in a range of 4 to 8 cycles of the first clock signal.
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| US9419632B1 (en) * | 2016-04-22 | 2016-08-16 | Via Alliance Semiconductor Co., Ltd. | Charge pump for use in phase-locked loop |
| CN114201440B (en) * | 2021-12-14 | 2024-06-07 | 上海微阱电子科技有限公司 | Clock detection method, circuit, serial port communication system, medium and equipment |
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| CN102279609A (en) * | 2010-06-09 | 2011-12-14 | 上海宏力半导体制造有限公司 | Voltage regulator and reference voltage generating circuit thereof |
| CN102360565A (en) * | 2011-08-26 | 2012-02-22 | 北京兆易创新科技有限公司 | Charge pump system and method for generating reading and writing operation word line voltage by aid of same and memory |
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| JP2007129828A (en) * | 2005-11-04 | 2007-05-24 | Sanyo Electric Co Ltd | Charge pump circuit |
| DE102008046324A1 (en) * | 2008-08-29 | 2010-04-01 | Stribel Production Gmbh | power supply |
| US8111107B2 (en) * | 2010-07-07 | 2012-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Charge pump control scheme |
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| CN101136248A (en) * | 2006-10-12 | 2008-03-05 | 中兴通讯股份有限公司 | A control device for a charge pump outputting high voltage |
| CN102279609A (en) * | 2010-06-09 | 2011-12-14 | 上海宏力半导体制造有限公司 | Voltage regulator and reference voltage generating circuit thereof |
| CN102158076A (en) * | 2011-05-06 | 2011-08-17 | 上海宏力半导体制造有限公司 | Output voltage regulator circuit of charge pump |
| CN102360565A (en) * | 2011-08-26 | 2012-02-22 | 北京兆易创新科技有限公司 | Charge pump system and method for generating reading and writing operation word line voltage by aid of same and memory |
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