CN101188095A - Liquid crystal display device and method capable of attenuating afterimage thereof - Google Patents

Abstract

The invention relates to a liquid crystal display device and a method capable of attenuating afterimage thereof, when the liquid crystal display device is shut down, a reset signal is enabled to set a corresponding grid signal of each grid line of the liquid crystal display device; and according to each set grid signal, each data switch of the liquid crystal display device is conducted to execute a quick discharge program of each storage unit of the liquid crystal display device so as to achieve the purpose of quickly attenuating the residual image. A reset circuit is used for setting all grid signals to be high-level signals according to the reset signal, and a charge-discharge module is also used for directly feeding high-level voltage to all grid lines according to the reset signal.

Description

Liquid crystal display device and method for attenuating its afterimage

technical field

The invention relates to a liquid crystal display device and a related method, in particular to a liquid crystal display device and a method for attenuating its afterimage.

Background technique

Liquid crystal display devices have the characteristics of light and thin appearance, low power consumption, and no radiation pollution, so they have been widely used in electronic products such as computer screens, mobile phones, personal digital assistants (PDAs), and flat-screen TVs. A liquid crystal display device usually has a liquid crystal material layer sandwiched between two substrates. By changing the potential difference between the two ends of the liquid crystal material layer, the rotation angle of the liquid crystal molecules in the liquid crystal material layer can be changed, so that the light transmittance of the liquid crystal material layer can be changed. Instead, different images are displayed.

Please refer to FIG. 1 , which is a schematic diagram of a conventional thin film transistor (Thin Film Transistor, TFT) liquid crystal display device. The liquid crystal display device 10 includes a liquid crystal display panel (LCD Panel) 100 , a power supply circuit 150 , a source driving circuit 104 , a gate driving circuit 106 and a voltage generator 108 . As mentioned above, the liquid crystal display panel 100 is basically composed of two substrates, and a liquid crystal material layer (Liquid Crystal Layer) is filled between the two substrates. For example, a plurality of data lines (Data Line) 110, a plurality of gate lines (Gate Line, or scan line, Scan Line) 112 perpendicular to the data line 110, and a plurality of thin film transistors 114 are arranged on a substrate. ; A common electrode (Common Electrode) is provided on the other substrate for receiving the common voltage Vcom provided by the voltage generator 108. For ease of description, only four thin film transistors 114 are shown in FIG. distributed on the liquid crystal display panel 100 in a manner, each data line 110 corresponds to a row of the thin film transistor liquid crystal display device 10, each gate line 112 corresponds to a column of the thin film transistor liquid crystal display device 10, and each thin film transistor 114 is Corresponding to a pixel (Pixel) of the thin film transistor liquid crystal display device 10 . In addition, the characteristics of the circuit formed by the two substrates of the liquid crystal display panel 100 can be regarded as a plurality of equivalent capacitors 116, each equivalent capacitor 116 includes at least one liquid crystal capacitor and at least one storage capacitor, and each equivalent capacitor 116 is become a storage unit.

The power supply circuit 150 includes a plurality of level shifters (Level Shifter) 151, 152 and 153 for converting the vertical start logic signal STV, the first pulse wave logic signal CLK1L and the second pulse wave logic signal CLK2L into vertical The start signal ST, the first pulse signal CLK1 and the second pulse signal CLK2 are supplied to the gate driving circuit 106 , and a low-level gate signal reference voltage Vgl can be sent to the gate driving circuit 106 .

The driving principle of the existing thin film transistor liquid crystal display device 10 is summarized as follows. When the power supply circuit 150 receives the vertical start logic signal STV, the first pulse wave logic signal CLK1L and the second pulse wave logic signal CLK2L, the power supply circuit 150 will send the signal The high/low logic level is converted into a high/low level gate signal reference voltage to generate the corresponding vertical start signal ST, the first pulse signal CLK1 and the second pulse signal CLK2, which are input to the gate drive circuit 106, and then the gate drive circuit 106 and the source drive circuit 104 will generate corresponding gate signals and data signals for different gate lines 112 and data lines 110, thereby controlling the conduction state and equivalent capacitance of the thin film transistor 114 116, and further change the rotation angle of liquid crystal molecules and the corresponding amount of light penetration, so as to display the data to be displayed on the panel. For example, the gate driving circuit 106 can input a gate signal to the gate line 112 to turn on the corresponding thin film transistor 114. At this time, the data signal input from the source driving circuit 104 to the data line 110 can be passed through The corresponding thin film transistor 114 is input to the corresponding equivalent capacitor 116 to control the gray level state of the corresponding pixel.

When the thin film transistor liquid crystal display device 10 is turned off, the charge stored in the equivalent capacitor 116 cannot be quickly discharged, but can only be gradually discharged through the leakage of the thin film transistor 114, so the image will not disappear immediately when the power is turned off, but will remain for a period of time. This is the phenomenon of residual image after shutdown (Residual Image), which may cause uncomfortable visual experience for users.

Contents of the invention

According to an embodiment of the present invention, a liquid crystal display device is disclosed, which is used to quickly attenuate the afterimage phenomenon of the liquid crystal display device when the liquid crystal display device is turned off. The liquid crystal display device includes a source drive circuit, a gate drive circuit, a plurality of data lines arranged in parallel (Data Line), a plurality of gate lines (Gate Line) arranged in parallel, a plurality of storage units, a plurality of data switch, a reset circuit, and a power circuit.

The source driving circuit is used to generate a plurality of data signals corresponding to images to be displayed. The gate driving circuit is used to generate a plurality of gate signals. A plurality of data lines arranged in parallel are coupled to the source driving circuit, and each data line receives a corresponding data signal. A plurality of gate lines arranged in parallel are coupled to the gate driving circuit and are perpendicular to the plurality of data lines, and each gate line receives a corresponding gate signal. Each storage unit includes a first terminal and a second terminal, wherein the first terminal is coupled to the corresponding data switch, and the second terminal is used for receiving the common voltage. Each data switch includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the corresponding storage unit, the second terminal is coupled to the corresponding data line, and the control terminal is coupled to the corresponding the gate line. The reset circuit includes a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal, and a third output terminal, wherein the first input terminal is used to receive a first pulse logic signal, The second input terminal is used to receive the second pulse logic signal, the third input terminal is used to receive the reset signal, and the first output terminal, the second output terminal, and the third output terminal are used to receive the reset signal as a Micro Motion When it is a logic signal, the first output terminal outputs the first pulse wave logic signal, the second output terminal outputs the second pulse wave logic signal, and the third output terminal outputs a low level logic signal, or is used to reset the signal to a low level When the logic signal is at a high level, the first output terminal, the second output terminal, and the third output terminal are all set as high-level logic signals. The power supply circuit includes a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal, wherein the first input terminal is used for To receive the vertical start logic signal, the second input end is coupled to the first output end of the reset circuit, the third input end is coupled to the second output end of the reset circuit, and the fourth input end is coupled to the reset circuit The third output terminal, the first output terminal is coupled to the gate drive circuit for outputting the vertical start signal, and the second output terminal is coupled to the gate drive circuit for outputting according to the first output terminal of the reset circuit The logic signal outputs the first pulse wave signal or the high-level gate signal reference voltage, and the third output terminal is coupled to the gate drive circuit to output the second pulse signal according to the logic signal output from the second output terminal of the reset circuit. wave signal or high-level gate signal reference voltage, the fourth output end is coupled to the gate drive circuit for outputting the gate signal reference voltage according to the logic signal output by the third output end of the reset circuit.

According to an embodiment of the present invention, it further discloses a liquid crystal display device, which is used to quickly attenuate the afterimage phenomenon of the liquid crystal display device when the liquid crystal display device is turned off. The liquid crystal display device includes a source driving circuit, a gate driving circuit, a plurality of data lines arranged in parallel, a plurality of gate lines arranged in parallel, a plurality of storage units, a plurality of data switches, a power supply circuit, and a Charge and discharge module.

The source driving circuit is used to generate a plurality of data signals corresponding to images to be displayed. The gate driving circuit is used to generate a plurality of gate signals, and the gate driving circuit includes an input terminal for receiving a low-level gate signal reference voltage. A plurality of data lines arranged in parallel are coupled to the source driving circuit, and each data line receives a corresponding data signal. A plurality of gate lines arranged in parallel are coupled to the gate driving circuit and are perpendicular to the plurality of data lines, and each gate line receives a corresponding gate signal. Each storage unit includes a first terminal and a second terminal, wherein the first terminal is coupled to the corresponding data switch, and the second terminal is used for receiving the common voltage. Each data switch includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the corresponding storage unit, the second terminal is coupled to the corresponding data line, and the control terminal is coupled to the corresponding gate line. The power supply circuit includes a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal, and a third output terminal, wherein the first input terminal is used to receive a vertical start logic signal, and the second The input end is used to receive the first pulse wave logic signal, the third input end is used to receive the second pulse wave logic signal, the first output end is coupled to the gate drive circuit, and is used to output a vertical start signal, and the second output end The third output terminal is coupled to the gate drive circuit for outputting the first pulse signal, and the third output terminal is coupled to the gate drive circuit for outputting the second pulse signal. The charging and discharging module is coupled to the plurality of gate lines for receiving a high-level gate signal reference voltage and a reset signal, so as to output a high-level gate signal reference voltage when the reset signal is enabled. a plurality of gate lines.

According to the embodiment of the present invention, it further discloses a method for attenuating the image sticking of a liquid crystal display device, which is used to quickly attenuate the image sticking phenomenon of the liquid crystal display device when the liquid crystal display device is turned off. The method includes enabling a reset signal when the liquid crystal display device is turned off, and setting a gate signal of each gate line of a plurality of gate lines of the liquid crystal display device according to the enabled reset signal, and setting a gate signal according to the activated reset signal. The set gate signals turn on each data switch of the plurality of data switches of the liquid crystal display device, and execute each of the plurality of storage units of the liquid crystal display device according to the turned-on data switches. The discharge procedure of the storage unit.

Description of drawings

FIG. 1 is a schematic diagram of a conventional thin film transistor liquid crystal display device.

FIG. 2 is a schematic diagram of a first embodiment of a liquid crystal display device capable of rapidly attenuating afterimages according to the present invention.

FIG. 3 is a timing diagram of signals related to the fast fading afterimage performed by the liquid crystal display device shown in FIG. 2 .

FIG. 4 is a schematic diagram of a second embodiment of a liquid crystal display device capable of rapidly attenuating afterimages according to the present invention.

FIG. 5 is a circuit diagram of an embodiment of the controllable switch shown in FIG. 4 .

FIG. 6 is a circuit diagram of another embodiment of the controllable switch shown in FIG. 4 .

FIG. 7 is a flow chart of a method for rapidly attenuating image sticking of a liquid crystal display device according to the present invention.

Figure number:

10, 20, 40 Liquid crystal display device

100, 200, 400 LCD display panel

104, 204, 404 Source drive circuit

106, 206, 406 gate drive circuit

108, 208, 408 Voltage generator

110, 210, 410 data lines

112, 212, 412 Gate lines

114, 214, 414 thin film transistor

116, 216, 416 equivalent capacitance

150, 250, 450 Power circuit

151-153, 251-254, level shifter

451-453, 495

260 reset circuit

261 The first logical OR gate

262 Second logic OR gate

263 buffer

480 Charge and discharge module

490 Controllable switch

491 Power cord

492 Control signal line

590, 690, 691 Transistors

CLK1 The first pulse signal

CLK1L The first pulse logic signal

CLK2 Second pulse signal

CLK2L Second pulse logic signal

S710-S740 Steps

ST Vertical start signal

STV Vertical start logic signal

Vcom Common voltage

Vgh High level gate signal reference voltage

Vgl Low level gate signal reference voltage

SGn-1, SGn, SGn+1 gate signal

Vss Gate signal reference voltage

XON reset signal

Detailed ways

In order to make the present invention clearer and easier to understand, the liquid crystal display device and the method for attenuating its afterimage according to the present invention will be described in detail below in conjunction with the accompanying drawings, but the provided examples are not intended to limit The scope covered by the present invention, and the step numbers of the method flow are not used to limit the order of execution, any execution flow recombined from the method steps, resulting in a method with equal effect, is covered by the present invention.

Please refer to FIG. 2 . FIG. 2 is a schematic diagram of a first embodiment of a liquid crystal display device capable of rapidly attenuating afterimages according to the present invention. The liquid crystal display device 20 includes a liquid crystal display panel 200 , a power supply circuit 250 , a source driving circuit 204 , a gate driving circuit 206 , a reset circuit 260 and a voltage generator 208 . The source driving circuit 204 is used for generating a plurality of data signals corresponding to images to be displayed, and the gate driving circuit 206 is used for generating a plurality of gate signals.

The liquid crystal display panel 200 includes two substrates, and a liquid crystal material layer is filled between the two substrates. A plurality of data lines 210, a plurality of gate lines 212 perpendicular to the data lines 210, and a plurality of thin film transistors 214 are arranged on one substrate, and a common electrode is arranged on the other substrate for receiving the voltage generated by the voltage generator 208. A common voltage Vcom is provided. The data lines 210 are coupled to the source driving circuit 204 , and each data line 210 receives a corresponding data signal provided by the source driving circuit 204 . The gate lines 212 are coupled to the gate driving circuit 206 , and each gate line 212 receives a corresponding gate signal provided by the gate driving circuit 206 .

For ease of description, FIG. 2 still only shows four thin film transistors 214, but in fact, the intersection of each data line 210 and gate line 212 in the liquid crystal display panel 200 is connected to a thin film transistor 214, that is, the thin film transistors 214 and 214 are connected to each other. The matrix is distributed on the liquid crystal display panel 200, that is to say, each data line 210 corresponds to a row of the thin film transistor liquid crystal display device 20, each gate line 212 corresponds to a column of the thin film transistor liquid crystal display device 20, and each A thin film transistor 214 corresponds to a pixel of the thin film transistor liquid crystal display device 20 . In addition, the characteristics of the circuit formed by the two substrates of the liquid crystal display panel 200 can be regarded as a plurality of equivalent capacitors 216, and each equivalent capacitor 216 includes a liquid crystal capacitor and a storage capacitor connected in parallel, and each equivalent capacitor 216 uses As a storage unit, it has a first terminal and a second terminal, the first terminal is coupled to a corresponding thin film transistor, and the second terminal is used for receiving the common voltage Vcom. Each thin film transistor 214 includes a first terminal, a second terminal and a control terminal, the first terminal is coupled to the corresponding equivalent capacitor 216, the second terminal is coupled to the corresponding data line 210, and the control terminal is coupled to the corresponding A gate line 212 . Each thin film transistor 214 is used as a data switch, which can control the signal connection between the second terminal and the first terminal according to the gate signal received by the control terminal and transmitted by the corresponding gate line 212, that is, control Whether the data signal of the corresponding data line 210 can be transmitted to the corresponding equivalent capacitor 216 .

The reset circuit 260 includes a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal and a third output terminal, wherein the first input terminal is used to receive the first pulse logic signal CLK1L , the second input terminal is used to receive the second pulse logic signal CLK2L, and the third input terminal is used to receive the reset signal XON. When the reset signal XON is a high-level logic signal, the first output terminal of the reset circuit 260 outputs the first pulse wave logic signal CLK1L to the power supply circuit 250, and the second output terminal outputs the second pulse wave logic signal CLK2L to the power supply. The circuit 250 , and the third output terminal outputs a low level logic signal to the power circuit 250 . When the reset signal XON is a low level logic signal, the first output terminal, the second output terminal and the third output terminal of the reset circuit 260 are all set to output a high level logic signal to the power supply circuit 250 .

In a preferred embodiment, the reset circuit 260 includes a buffer (Buffer) 263 , a first logic OR gate 261 and a second logic OR gate 262 . The buffer 263 includes an input terminal and an output terminal, wherein the input terminal is coupled to the third input terminal of the reset circuit 260 for receiving the reset signal XON, and the output terminal is coupled to the third output terminal of the reset circuit 260, It is used to output the inverted signal of the reset signal XON. In the embodiment of FIG. 2, the reset signal XON is a low-level enable signal, so the buffer 263 is an inverting buffer; in another embodiment, if the reset signal XON is a high-level enable signal If the signal is enabled, the buffer 263 is a non-inverting buffer. The first logical OR gate 261 includes a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the first input terminal of the reset circuit 260 for receiving the first pulse wave logic signal CLK1L, the second The two input terminals are coupled to the output terminal of the buffer 263 , and the output terminal is coupled to the first output terminal of the reset circuit 260 . The second logical OR gate 262 includes a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the second input terminal of the reset circuit 260 for receiving the second pulse logic signal CLK2L, the second The two input terminals are coupled to the output terminal of the buffer 263 , and the output terminal is coupled to the second output terminal of the reset circuit 260 .

The power supply circuit 250 includes a plurality of input terminals and a corresponding plurality of output terminals, for converting the low-level logic voltage of each input signal into a low-level gate signal reference voltage Vgl, and converting the low-level logic voltage of each input signal The high-level logic voltage is converted into a high-level gate signal reference voltage Vgh. In a preferred embodiment, the power supply circuit 250 includes a plurality of level shifters 251-254. The level shifter 251 includes an input terminal, an output terminal, a high potential input terminal and a low potential input terminal, wherein the input terminal is used to receive the vertical start logic signal STV, and the output terminal is used to output the vertical start signal ST to the gate driver In the circuit 206 , the high potential input terminal is used for receiving the high level gate signal reference voltage Vgh, and the low potential input terminal is used for receiving the low level gate signal reference voltage Vgl. The level shifter 252 includes an input terminal, an output terminal, a high potential input terminal and a low potential input terminal, wherein the input terminal is coupled to the first output terminal of the reset circuit 260, and the output terminal is coupled to the gate driving circuit 206 , to output the first pulse signal CLK1 or the high-level gate signal reference voltage Vgh, the high-level input terminal is used to receive the high-level gate signal reference voltage Vgh, and the low-level input terminal is used to receive the low-level gate signal Pole signal reference voltage Vgl.

The level shifter 253 includes an input terminal, an output terminal, a high potential input terminal, and a low potential input terminal, wherein the input terminal is coupled to the second output terminal of the reset circuit 260, and the output terminal is coupled to the gate The pole driving circuit 206 is used to output the second pulse signal CLK2 or the high-level gate signal reference voltage Vgh, the high-level input terminal is used to receive the high-level gate signal reference voltage Vgh, and the low-level input terminal is used to receive the low-level gate signal reference voltage Vgh. The level gate signal reference voltage Vgl. The level shifter 254 includes an input terminal, an output terminal, a high potential input terminal, and a low potential input terminal, wherein the input terminal is coupled to the third output terminal of the reset circuit 260, and the output terminal is coupled to the gate The electrode driving circuit 206 is used to output a gate signal reference voltage Vss, the high potential input terminal is used to receive the high level gate signal reference voltage Vgh, and the low potential input terminal is used to receive the low level gate signal reference voltage Vgl.

Please refer to FIG. 3 . FIG. 3 shows a timing diagram of operation-related signals of the liquid crystal display device 20 in FIG. 2 , and the horizontal axis is the time axis. In FIG. 3 , the signals from top to bottom are reset signal XON, first pulse signal CLK1 , second pulse signal CLK2 , gate signal reference voltage Vss, and gate signal SGn. The working principle of the rapidly attenuating afterimage function of the liquid crystal display device 20 is described as follows in conjunction with the related signal timing diagram shown in FIG. 3 . When starting up and working normally, the reset signal XON is a high-level logic signal, so that the buffer 263 outputs a low-level logic signal. input, so that both the first pulse wave logic signal CLK1L and the second pulse wave logic signal CLK2L can be transmitted to the power supply circuit 250 through the reset circuit 260, and the first pulse wave signal CLK1 is generated by the signal level conversion process of the power supply circuit 250 and the second pulse signal CLK2. As for the reset signal XON, the gate signal reference voltage Vss is set to the low level gate signal reference voltage Vgl through the inversion process of the buffer 263 and the signal level conversion process of the level shifter 254 . In addition, the vertical start logic signal STV is converted and processed by the level shifter 251 to generate the vertical start signal ST, so the gate drive circuit 206 can generate the vertical start signal ST according to the vertical start signal ST, the first pulse wave The signal CLK1, the second pulse signal CLK2 and the gate signal refer to the voltage Vss to generate a plurality of gate signals SGn-1, SGn, SGn+1, etc., which are respectively output to the corresponding gate lines 212 to perform normal gate operation. The image to be displayed is output through a polar scanning operation.

When the liquid crystal display device 20 is turned off at the time Toff, the reset signal XON is converted from a high-level logic signal to a low-level logic signal, so that the buffer 263 outputs a high-level logic signal, and the first logic OR gate 261 and the second logic logic Due to the input of the high-level signal, the OR gate 262 switches the outputs of the first logic OR gate 261 and the second logic OR gate 262 to high-level logic signals, that is, the first pulse wave logic signal CLK1L and the second pulse wave logic signal CLK1L. Neither the logic signal CLK2L can be transmitted to the power circuit 250 through the reset circuit 260, so the first pulse signal CLK1 and the second pulse signal CLK2 are switched to a high level signal, and the gate signal reference voltage Vss is also switched to a high level signal. Therefore, the gate signals of all the gate lines 212 are switched to high level signals, so that all the thin film transistors 214 are turned on, so the stored charges of all the equivalent capacitors 216 can be quickly released. Please note that due to shutdown, the voltage of the high-level signal cannot reach the reference voltage Vgh of the high-level gate signal, and will decrease with time, but the remaining power of shutdown is enough to turn on all the thin film transistors 214 to Quickly release all the stored charges of the equivalent capacitor 216 to rapidly decay afterimages.

Please refer to FIG. 4 . FIG. 4 is a schematic diagram of a second embodiment of a liquid crystal display device capable of rapidly attenuating afterimages according to the present invention. The liquid crystal display device 40 includes a liquid crystal display panel 400 , a power supply circuit 450 , a source driving circuit 404 , a gate driving circuit 406 , a charging and discharging module 480 and a voltage generator 408 . The source driving circuit 404 is used for generating a plurality of data signals corresponding to images to be displayed, and the gate driving circuit 406 is used for generating a plurality of gate signals. The liquid crystal display panel 400 is composed of two substrates, one substrate is provided with a plurality of data lines 410, a plurality of gate lines 412 perpendicular to the data lines 410, and a plurality of thin film transistors 414, and a common electrode is provided on the other substrate Used to receive a voltage Vcom provided by the voltage generator 408 .

For ease of illustration, FIG. 4 still only shows four thin film transistors 414, but in fact, in the liquid crystal display panel 400, a thin film transistor 414 is connected to the intersection of each data line 410 and gate line 412 to correspond to a pixel. . In addition, the characteristics of the circuit formed by the two substrates of the liquid crystal display panel 400 can be regarded as a plurality of equivalent capacitors 416, each equivalent capacitor 416 includes a liquid crystal capacitor and a storage capacitor connected in parallel, and each equivalent capacitor 416 uses As a storage unit, it is coupled between the corresponding thin film transistor 414 and the voltage generator 408 .

The power circuit 450 includes a plurality of level shifters 451-453. The level shifter 451 includes an input terminal, an output terminal, a high potential input terminal, and a low potential input terminal, wherein the input terminal is used to receive a vertical start logic signal STV, and the output terminal is used to output a vertical start logic signal STV. The start signal ST is sent to the gate driving circuit 406, the high potential input terminal is used to receive the high level gate signal reference voltage Vgh, and the low potential input terminal is used to receive the low level gate signal reference voltage Vgl. The level shifter 452 includes an input terminal, an output terminal, a high potential input terminal, and a low potential input terminal, wherein the input terminal is used to receive the first pulse wave logic signal CLK1L, and the output terminal is used to output the first pulse wave logic signal CLK1L. The wave signal CLK1 is sent to the gate driving circuit 406 , the high potential input terminal is used to receive the high level gate signal reference voltage Vgh, and the low potential input terminal is used to receive the low level gate signal reference voltage Vgl.

The level shifter 453 includes an input terminal, an output terminal, a high potential input terminal, and a low potential input terminal, wherein the input terminal is used to receive the second pulse wave logic signal CLK2L, and the output terminal is used to output the second pulse wave logic signal CLK2L. The wave signal CLK2 is sent to the gate driving circuit 406, the high potential input terminal is used to receive the high level gate signal reference voltage Vgh, and the low potential input terminal is used to receive the low level gate signal reference voltage Vgl. The power supply circuit 450 may further include an input terminal for receiving the low-level gate signal reference voltage Vgl, and transmitting the low-level gate signal reference voltage Vgl to the gate driving circuit 406 through an output terminal. In another embodiment, the low-level gate signal reference voltage Vgl can be directly fed to the gate driving circuit 406 without going through the power supply circuit 450 .

The charging and discharging module 480 includes an inverse level shifter 495 , a plurality of controllable switches 490 , a power line 491 and a control signal line 492 . The inverse level shifter 495 includes an input terminal, an output terminal, a high potential input terminal, and a low potential input terminal, wherein the input terminal is used to receive a reset signal XON, and the output terminal is coupled to the control signal line 492 , the high potential input end is used to receive the high level gate signal reference voltage Vgh, and the low potential input end is used to receive the low level gate signal reference voltage Vgl. The inversion level shifter 495 inverts the reset signal XON and converts the high/low level logic voltage into a high/low level gate signal reference voltage for outputting a control signal for transmission via the control signal line 492 to these controllable switches 490 as described. Please note that in the embodiment shown in FIG. 4, the reset signal XON is a signal enabled at a low level. In another embodiment, if the reset signal XON is a signal enabled at a high level, the inversion Level shifter 495 should be replaced with a non-inverting level shifter. Each controllable switch 490 includes an output end, an input end, and a control end, wherein the output end is coupled to the corresponding gate line 412, and the input end is coupled to the power line 491 for receiving a high level The reference voltage of the gate signal is Vgh, and the control terminal is coupled to the control signal line 492 .

Please refer to FIG. 5 , which is a circuit diagram of an embodiment of the controllable switch 490 shown in FIG. 4 . The controllable switch 490 includes a transistor 590, and the transistor 590 includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the corresponding gate line 412, the second terminal is coupled to the power line 491, and the control terminal is coupled to Connected to the control signal line 492 . The transistor 590 can be a thin film transistor (Thin Film Transistor), a metal oxide semiconductor field effect transistor (MOSFET) or a bipolar junction transistor (Bipolar Junction Transistor).

Please refer to FIG. 6 , which is a circuit diagram of another embodiment of the controllable switch 490 shown in FIG. 4 . The controllable switch 490 includes a first transistor 690 and a second transistor 691 . The first transistor 690 includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the corresponding gate line 412, and the second terminal is coupled to the power supply line 491. The first transistor 690 can be a thin film transistor, bipolar transistor, or metal-oxide-semiconductor field-effect transistor. The second transistor 691 includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the control terminal of the first transistor 690, and the control terminal is coupled to the second terminal of the second transistor 691 and the control signal line 492 , the second transistor 691 may be a thin film transistor, a bipolar transistor or a metal oxide semiconductor field effect transistor. If both the first transistor 690 and the second transistor 691 are metal-oxide-semiconductor field-effect transistors, when the second transistor 691 turns on the first transistor 690 according to the control signal fed in from the control signal line 492, the first The voltage bootstrap effect of the gate capacitance of the transistor 690 makes the second transistor 691 enter the cut-off state, so the gate-source driving voltage that the first transistor 690 is turned on can be maintained to maintain high discharge efficiency.

The working principle of the rapidly attenuating afterimage function of the liquid crystal display device 40 is described as follows. When starting up and working normally, the reset signal XON is a high-level logic signal, so that the inverse phase shifter 495 outputs a low-level gate signal reference voltage Vgl, and the control terminals of the switches 490 can be controlled. Because receiving the low-level gate signal reference voltage Vgl and isolating the signal connection between the power line 491 and the gate lines 412, the high-level gate signal reference voltage Vgh of the power line 491 cannot be fed to all The aforementioned gate lines 412, in other words, the aforementioned gate lines 412 only receive the gate signals SGn-1, SGn, SGn+1, etc. outputted by the gate drive circuit 406 to perform normal scanning operation to output the image to be displayed.

At the moment when the liquid crystal display device 40 is turned off, the reset signal XON is converted from a high-level logic signal to a low-level logic signal, so that the inverse phase shifter 495 outputs a high-level gate signal reference voltage Vgh, so The control terminals of these controllable switches 490 mentioned above receive the reference voltage Vgh of the high-level gate signal and turn on the power supply line 491 to connect with the signals of these gate lines 412, so the high-level position of the power supply line 491 The gate signal reference voltage Vgh is fed to these gate lines 412 . In other words, the gate signals of all the gate lines 412 are switched to the high-level gate signal reference voltage Vgh, thus turning on all the thin film transistors 414 to quickly release the stored charges of all the equivalent capacitors 416 Quickly fades afterimages.

Please refer to FIG. 7 . FIG. 7 is a flowchart of a method for quickly attenuating afterimages of a liquid crystal display device according to the present invention. This method flow consists of the following steps:

Step S710: enabling a reset signal when the liquid crystal display device is turned off;

Step S720: according to the enabled reset signal, setting a gate signal of each gate line of the plurality of gate lines of the liquid crystal display device;

Step S730: turn on each data switch of the plurality of data switches of the liquid crystal display device according to the set gate signals; and

Step S740: Execute a discharge process for each storage unit of the plurality of storage units of the liquid crystal display device according to the data switches that are turned on.

In the process of the method for quickly attenuating the afterimage of the liquid crystal display device, in step S710, when the liquid crystal display device is turned off, enabling the reset signal is to switch the reset signal to a low level when the liquid crystal display device is turned off. bit logic signal. In step S720, according to the enabled reset signal, setting the gate signal of each of the gate lines of the liquid crystal display device includes, according to the enabled reset signal, setting the liquid crystal display The gate signal of each of the gate lines of the device is set to a high level signal. In addition, step S720 may further include isolating the signal connection relationship between the gate lines and at least one input pulse signal.

As for the method of setting the gate signal according to the enabled reset signal in step S720, it may include using a charging and discharging module coupled to the gate lines to set a high voltage according to the enabled reset signal. The level gate signal reference voltage is directly fed to each of the gate lines of the liquid crystal display device, or it may also include a reset circuit coupled to a gate drive circuit, according to the The enabled reset signal sets the gate signal coupled to each gate line of the gate driving circuit to a high level gate signal reference voltage. Turning on each of the data switches of the liquid crystal display device according to the set gate signals in step S730 includes turning on the liquid crystal display according to the set gate signals Each thin film transistor of the plurality of thin film transistors of the device. In step S740, according to the data switches that are turned on, performing a discharge procedure for each storage unit of the storage units of the liquid crystal display device includes, according to the data switches that are turned on, Executing a discharge procedure for liquid crystal capacitors and storage capacitors of each of the storage cells coupled to the data switches.

From the above, it can be known that according to the liquid crystal display device and method capable of quickly attenuating afterimages of the present invention, when a liquid crystal display device is turned off, a reset signal can be enabled to set a gate line of each gate line of the liquid crystal display device. Corresponding to the gate signal, each data switch of the liquid crystal display device is turned on according to each gate signal that is set, and is used to execute the fast discharge procedure of each storage unit of the liquid crystal display device, so as to achieve the purpose of quickly attenuating afterimage .

Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Modification, therefore, the scope of protection of the present invention should be defined by the scope of the claims.

Claims (20)

1. a liquid crystal indicator is characterized in that, described liquid crystal indicator comprises:

The one source pole driving circuit is used for producing the plurality of data signal corresponding to image to be shown;

One gate driver circuit is used for producing a plurality of signals;

The data line that a plurality of be arranged in parallel is coupled to described source electrode drive circuit, and each data line receives a corresponding data-signal of described plurality of data signal;

The gate line that a plurality of be arranged in parallel is coupled to described gate driver circuit, and is orthogonal with described a plurality of data lines, and each gate line receives a corresponding signal of described a plurality of signals;

A plurality of storage elements, each storage element comprises:

One first end is coupled to a corresponding data line of described a plurality of data lines; And

One second end is used voltage altogether in order to receive;

The plurality of data switch, each data switch comprises:

One first end is coupled to a corresponding storage element of described a plurality of storage elements;

One second end is coupled to a corresponding data line of described a plurality of data lines; And

One control end is coupled to a corresponding gate line of described a plurality of gate lines;

One reset circuit, comprise a first input end, one second input end, the 3rd input end, one first output terminal, one second output terminal, and one the 3rd output terminal, wherein said first input end is in order to receive one first pulse wave logical signal, described second input end is in order to receive one second pulse wave logical signal, described the 3rd input end is in order to receive a reset signal, described first output terminal, described second output terminal, and described the 3rd output terminal is when being used to described reset signal and being one first logical signal, described first output terminal is exported the described first pulse wave logical signal, described second output terminal is exported the described second pulse wave logical signal, described the 3rd output terminal is exported a low level logical signal, or when described reset signal is one second logical signal, described first output terminal, described second output terminal, and described the 3rd output terminal all is reset and exports described high levle logical signal; And

One power circuit, comprise a first input end, one second input end, one the 3rd input end, one four-input terminal, one first output terminal, one second output terminal, one the 3rd output terminal, and one the 4th output terminal, wherein said first input end vertically opens the beginning logical signal in order to receive one, described second input end is coupled to described first output terminal of described reset circuit, described the 3rd input end is coupled to described second output terminal of described reset circuit, described four-input terminal is coupled to described the 3rd output terminal of described reset circuit, described first output terminal is coupled to described gate driver circuit, vertically open the beginning signal in order to export one, described second output terminal is coupled to described gate driver circuit, export one first pulse wave signal or a high levle signal reference voltage in order to the logical signal of exporting according to first output terminal of described reset circuit, described the 3rd output terminal is coupled to described gate driver circuit, export one second pulse wave signal or described high levle signal reference voltage in order to the logical signal of exporting according to second output terminal of described reset circuit, described the 4th output terminal is coupled to described gate driver circuit, exports a signal reference voltage in order to the logical signal of exporting according to the 3rd output terminal of described reset circuit.

2. liquid crystal indicator as claimed in claim 1 is characterized in that, described reset circuit comprises:

One impact damper, comprise an input end and an output terminal, wherein said input end is coupled to described the 3rd input end of described reset circuit, and in order to receive described reset signal, described output terminal is coupled to described the 3rd output terminal of described reset circuit;

One first logic sum gate, comprise a first input end, one second input end, reach an output terminal, wherein said first input end is coupled to the described first input end of described reset circuit, in order to receive the described first pulse wave logical signal, described second input end is coupled to the described output terminal of described impact damper, and described output terminal is coupled to described first output terminal of described reset circuit; And

One second logic sum gate, comprise a first input end, one second input end, reach an output terminal, wherein said first input end is coupled to described second input end of described reset circuit, in order to receive the described second pulse wave logical signal, described second input end is coupled to the described output terminal of described impact damper, and described output terminal is coupled to described second output terminal of described reset circuit.

3. liquid crystal indicator as claimed in claim 2 is characterized in that, described data switch is a thin film transistor (TFT), and described impact damper is an inverter buffer or a non-inverting buffer.

4. liquid crystal indicator as claimed in claim 1 is characterized in that described storage element comprises a liquid crystal capacitance.

5. liquid crystal indicator as claimed in claim 1 is characterized in that described liquid crystal indicator comprises a voltage generator in addition, is coupled to described a plurality of storage element, in order to described common voltage to be provided.

6. liquid crystal indicator as claimed in claim 1 is characterized in that, described power circuit comprises:

One first level shifter, comprise an input end, an output terminal, a noble potential input end, reach an electronegative potential input end, wherein said input end is coupled to the described first input end of described power circuit, described output terminal is coupled to described first output terminal of described power circuit, described noble potential input end is in order to receive described high levle signal reference voltage, and described electronegative potential input end is in order to receive a low level signal reference voltage;

One second level shifter, comprise an input end, an output terminal, a noble potential input end, reach an electronegative potential input end, wherein said input end is coupled to described second input end of described power circuit, described output terminal is coupled to described second output terminal of described power circuit, described noble potential input end is in order to receive described high levle signal reference voltage, and described electronegative potential input end is in order to receive described low level signal reference voltage;

One the 3rd level shifter, comprise an input end, an output terminal, a noble potential input end, reach an electronegative potential input end, wherein said input end is coupled to described the 3rd input end of described power circuit, described output terminal is coupled to described the 3rd output terminal of described power circuit, described noble potential input end is in order to receive described high levle signal reference voltage, and described electronegative potential input end is in order to receive described low level signal reference voltage; And

One the 4th level shifter, comprise an input end, an output terminal, a noble potential input end, reach an electronegative potential input end, wherein said input end is coupled to the described four-input terminal of described power circuit, described output terminal is coupled to described the 4th output terminal of described power circuit, described noble potential input end is in order to receive described high levle signal reference voltage, and described electronegative potential input end is in order to receive described low level signal reference voltage.

7. a liquid crystal indicator is characterized in that, described liquid crystal indicator comprises:

The one source pole driving circuit is used for producing the plurality of data signal corresponding to image to be shown;

One gate driver circuit is used for producing a plurality of signals, and described gate driver circuit comprises an input end, is used for receiving a low level signal reference voltage;

The data line that a plurality of be arranged in parallel is coupled to described source electrode drive circuit, and each data line receives a corresponding data-signal of described plurality of data signal;

The gate line that a plurality of be arranged in parallel is coupled to described gate driver circuit, and is orthogonal with described a plurality of data lines, and each gate line receives a corresponding signal of described a plurality of signals;

A plurality of storage elements, each storage element comprises:

One first end is coupled to a corresponding data line of described a plurality of data lines; And

One second end is used voltage altogether in order to receive;

The plurality of data switch, each data switch comprises:

One first end is coupled to a corresponding storage element of described a plurality of storage elements;

One second end is coupled to a corresponding data line of described a plurality of data lines; And

One control end is coupled to a corresponding gate line of described a plurality of gate lines;

One power circuit, comprise a first input end, one second input end, one the 3rd input end, one first output terminal, one second output terminal, and one the 3rd output terminal, wherein said first input end vertically opens the beginning logical signal in order to receive one, described second input end is in order to receive one first pulse wave logical signal, described the 3rd input end is in order to receive one second pulse wave logical signal, described first output terminal is coupled to described gate driver circuit, vertically open the beginning signal in order to export one, described second output terminal is coupled to described gate driver circuit, in order to export one first pulse wave signal, described the 3rd output terminal is coupled to described gate driver circuit, in order to export one second pulse wave signal; And

One charge-discharge modules, be coupled to described a plurality of gate lines, be used for receiving a high levle signal reference voltage and receive a reset signal,, export described high levle signal reference voltage to described a plurality of gate lines with when described reset signal is enabled.

8. liquid crystal indicator as claimed in claim 7 is characterized in that, described charge-discharge modules comprises:

One level shifter, comprise an input end, an output terminal, a noble potential input end, reach an electronegative potential input end, wherein said input end is in order to receive a reset signal, described output terminal is in order to export a control signal, described noble potential input end is in order to receive described high levle signal reference voltage, and described electronegative potential input end is in order to receive described low level signal reference voltage; And

A plurality of controllable switch, each controllable switch comprises:

One first end is coupled to a corresponding gate line of described a plurality of gate lines;

One second end is in order to receive described high levle signal reference voltage; And

One control end, be coupled to the described output terminal of described level shifter, in order to receive described control signal, described controllable switch is controlled the signal binding between described first end and described second end in order to according to the described control signal that described control end received.

9. liquid crystal indicator as claimed in claim 8 is characterized in that, described level shifter is an antiphase shifter or a noninverting level shifter.

10. liquid crystal indicator as claimed in claim 8 is characterized in that described controllable switch comprises a transistor, and described transistor comprises:

One first end is coupled to a corresponding gate line of described a plurality of gate lines;

One second end is in order to receive described high levle signal reference voltage; And

One control end, be coupled to the described output terminal of described level shifter, in order to receive described control signal, described transistor is controlled the signal binding between described first end and described second end in order to according to the described control signal that described control end received.

11. liquid crystal indicator as claimed in claim 10 is characterized in that, described transistor is a thin film transistor (TFT), a metal oxide semiconductcor field effect transistor or a two-carrier transistor.

12. liquid crystal indicator as claimed in claim 8 is characterized in that, described controllable switch comprises:

One the first transistor, described the first transistor comprises:

One first end is coupled to a corresponding gate line of described a plurality of gate lines;

One second end is in order to receive described high levle signal reference voltage; And

One control end; And

One transistor seconds, described transistor seconds comprises:

One first end is coupled to the described control end of described the first transistor;

One second end; And

One control end, be coupled to described second end of described transistor seconds and the described output terminal of described level shifter, in order to receive described control signal, described controllable switch is in order to the described control signal that described control end received according to described transistor seconds, and described first end and the signal between described second end of controlling described the first transistor link.

13. liquid crystal indicator as claimed in claim 7 is characterized in that, described data switch is a thin film transistor (TFT).

14. liquid crystal indicator as claimed in claim 7 is characterized in that, described storage element comprises a liquid crystal capacitance.

15. liquid crystal indicator as claimed in claim 7 is characterized in that, described liquid crystal indicator comprises a voltage generator in addition, is coupled to described a plurality of storage element, in order to described common voltage to be provided.

16. liquid crystal indicator as claimed in claim 7 is characterized in that, described power circuit comprises:

One first level shifter, comprise an input end, an output terminal, a noble potential input end, reach an electronegative potential input end, wherein said input end is coupled to the described first input end of described power circuit, described output terminal is coupled to described first output terminal of described power circuit, described noble potential input end is in order to receive described high levle signal reference voltage, and described electronegative potential input end is in order to receive described low level signal reference voltage;

One second level shifter, comprise an input end, an output terminal, a noble potential input end, reach an electronegative potential input end, wherein said input end is coupled to described second input end of described power circuit, described output terminal is coupled to described second output terminal of described power circuit, described noble potential input end is in order to receive described high levle signal reference voltage, and described electronegative potential input end is in order to receive described low level signal reference voltage; And

One the 3rd level shifter, comprise an input end, an output terminal, a noble potential input end, reach an electronegative potential input end, wherein said input end is coupled to described the 3rd input end of described power circuit, described output terminal is coupled to described the 3rd output terminal of described power circuit, described noble potential input end is in order to receive described high levle signal reference voltage, and described electronegative potential input end is in order to receive described low level signal reference voltage.

17. the method for the ghost of the liquid crystal indicator of can decaying, described method comprises:

When described liquid crystal indicator shuts down, activation one reset signal;

According to the described reset signal that is enabled, the signal of each bar gate line of a plurality of gate lines of described liquid crystal indicator is set;

Each data switch according to the plurality of data switch of the described liquid crystal indicator of described these signal conductings that is set up; And

According to described these data switches that are switched on, carry out the discharge procedures of each storage element of a plurality of storage elements of described liquid crystal indicator.

18. method as claimed in claim 17, wherein when described liquid crystal indicator shuts down, the described reset signal of activation comprises when described liquid crystal indicator shuts down, and described reset signal is switched to a low level logical signal or a high levle logical signal.

19. method as claimed in claim 17, wherein according to the described reset signal that is enabled, the described signal of each bar gate line of described these gate lines of described liquid crystal indicator is set, comprise according to the described reset signal that is enabled, the described signal of each bar gate line of described these gate lines of described liquid crystal indicator is set to a high levle signal reference voltage.

20. method as claimed in claim 17, wherein according to the described reset signal that is enabled, the described signal of each bar gate line of described these gate lines of described liquid crystal indicator is set, comprise and utilize a charge-discharge modules that is coupled to described these gate lines, according to the described reset signal that is enabled, a high levle signal reference voltage is fed to described these gate lines of described liquid crystal indicator.

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