CN101179066B - Chip embedded type packaging structure - Google Patents
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- CN101179066B CN101179066B CN200610143530A CN200610143530A CN101179066B CN 101179066 B CN101179066 B CN 101179066B CN 200610143530 A CN200610143530 A CN 200610143530A CN 200610143530 A CN200610143530 A CN 200610143530A CN 101179066 B CN101179066 B CN 101179066B
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
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- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01—ELECTRIC ELEMENTS
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Abstract
一种芯片嵌埋式封装结构，主要包括一具凸起部的承载板；形成于该承载板凸起部上的半导体芯片；形成于该承载板及该半导体芯片上的绝缘层；以及形成于该绝缘层上的线路层，且该线路层可通过多个导电结构以电性连接至半导体芯片的电极垫，以提供该半导体芯片向外作电性延伸。能通过调整承载板凸起部、绝缘层、承载板厚度以达到控制封装结构在制造方法中因温度变化所产生的翘曲现象。
A chip embedded packaging structure mainly includes a carrier plate with a protruding portion; a semiconductor chip formed on the protruding portion of the carrier plate; an insulating layer formed on the carrier plate and the semiconductor chip; and a circuit layer formed on the insulating layer, and the circuit layer can be electrically connected to the electrode pad of the semiconductor chip through a plurality of conductive structures to provide the semiconductor chip with electrical extension outward. The warping phenomenon of the packaging structure caused by temperature changes during the manufacturing method can be controlled by adjusting the protruding portion of the carrier plate, the insulating layer, and the thickness of the carrier plate.
Description
Technical field
The present invention relates to a kind of chip embedding bury type packaging structure, particularly a kind of embedded with semi-conductor chip also makes it directly outwards make the encapsulating structure that electrically extends.
Background technology
Evolution along with semiconductor packaging, semiconductor device (Semiconductor device) has been developed different packing forms, conventional semiconductor device mainly is first device one semiconductor subassembly of integrated circuit for example on a base plate for packaging (package substrate) or lead frame, again semiconductor subassembly is electrically connected on this base plate for packaging or the lead frame, then encapsulates with colloid.Ball grid array (Ball grid array wherein, BGA) be a kind of advanced person's semiconductor packaging, its characteristics are to adopt a base plate for packaging to settle semiconductor subassembly, and utilize automatic contraposition (Self-alignment) technology to put most the tin balls (Solder ball) that become grid array to arrange to plant in this base plate for packaging back side, make and can hold the needs of more I/O links (I/O connection) on the semiconductor subassembly bearing part of same units area with the semiconductor chip that meets Highgrade integration (Integration), with by these a little tin balls with whole encapsulation unit weldering knot and be electrically connected to external device (ED).
But the conventional semiconductor package structure be with semiconductor subassembly one by one stick in substrate top surface, carry out routing and engage (wire bonding) or chip bonding (Flip chip) encapsulation, plant with the tin ball to electrically connect in the back side of substrate again, so, though can reach the purpose of high pin number, but because the area of semiconductor subassembly and volume restrictions make substrate surface wiring difficulty increase, and because those semiconductor subassemblies all are distributed in substrate surface, thereby be unfavorable for dwindling and the raising of performance of emitted semiconductor assembly package structure size.
In addition, general manufacturing method of semiconductor module, at first be to produce the chip bearing member that is applicable to this semiconductor subassembly by the chip bearing member manufacturing engineer, as substrate or lead frame, afterwards, again those chip bearing members are transferred to the semiconductor packages engineer and put crystalline substance, mold pressing and plant manufacture method such as ball, last, can finish the semiconductor subassembly of the required electric function of client.Relate to different manufacture methods (promptly including chip bearing member manufacturing operation and semiconductor packages operation) therebetween, therefore not only step is loaded down with trivial details and be difficult for integration of interface in actual manufacture process, moreover, when if client desires to change the function design, it is complicated especially with concordant bedding that it involves change, also do not meet requirement change elasticity and economic benefit.
Also have, flourish along with electronic industry, electronic product also marches toward multi-functional, high performance R﹠D direction gradually.For satisfying the package requirements of semiconductor package part high integration (Integration) and microminiaturized (Miniaturization), the heat that semiconductor chip is produced when running will obviously increase, effectively disperse as the untimely heat that semiconductor chip is produced, will seriously shorten the performance and the life-span of semiconductor chip.
For this reason, there is industry to propose semiconductor subassembly is imbedded the practice of substrate then.As shown in Figure 1, imbed the generalized section of the encapsulating structure of substrate for the conventional semiconductor assembly.As shown in the figure, this encapsulating structure comprises a heating panel 12, and is formed with an opening 120 in this heating panel 12; Semiconductor chip 13, it connects and places on this heating panel 12 and be accommodated in this heating panel opening 120, and has a plurality of electronic padses 130 on this semiconductor chip; Insulating barrier 14 is formed on this heating panel 12 and this semiconductor chip 13; And line layer 15, be formed on this insulating barrier 14, and this line layer 15 can be electrically connected to the electronic pads 130 of this semiconductor chip 13 by being formed at conductive blind hole 150 in this insulating barrier 14.
Though the encapsulating structure of this chip buried base plate can solve the defective of above-mentioned prior art, yet, because heating panel 12, the thermal coefficient of expansion of insulating barrier 14 (Coefficient of ThermalExpansion, CTE) difference is big, during the variations in temperature of this kind board structure in manufacture process (as substrate baking (Baking), during environment such as subsequent thermal circulation (Thermal Cycle) operation, produce different thermal stress (Thermal Stress) on each building block respectively), easily cause structure generation warpage (Warpage) phenomenon, may cause when serious and produce delamination between structure sheaf, even be expressed to semiconductor chip, cause chip rupture.The suffered thermal stress (Thermal Stress) of substrate can effectively be improved the substrate warp phenomenon when but increase heating panel thickness changed with equilibrium temperature, the volume and the thickness of encapsulating structure finished product can be obviously increased but set up heating panel thickness, and the increase of manufacture method cost can be caused.
In addition, the semiconductor chip great majority of being imbedded in the above-mentioned encapsulating structure do not form multi-functional module architectures as yet for single form and measure-alike, do not meet electronic product development trend now.In addition, if in this encapsulating structure, imbed the different semiconductor subassembly of various ways, size to reach multi-functional module architectures, because the size difference of those assemblies of being imbedded, make the electric connection surface of those assemblies not be in same plane, cause being embedded with the surface of insulating layer out-of-flatness on the base plate for packaging surface of those original papers, even influence the workmanship that on this insulating barrier, carries out follow-up fine rule road.
Therefore, how a kind of chip embedding bury type packaging structure is proposed, structure generation warpage, encapsulating structure thickness, weight and cost increase in the existing semiconductor package manufacture process to overcome, make surface irregularity, circuit manufacture method ability can't promote, integration of interface is difficult for, can't efficiently radiates heat etc. problem real in to become the technical problem that present this area demands urgently capturing.
Summary of the invention
In view of the defective of above-mentioned prior art, main purpose of the present invention is to provide a kind of chip embedding bury type packaging structure, to avoid causing the structure warping phenomenon in the hot manufacture process of semiconductor device.
Another object of the present invention is to provide a kind of chip embedding bury type packaging structure, to reduce semiconductor device thickness, weight and manufacturing cost.
A further object of the present invention is to provide a kind of chip embedding bury type packaging structure, keeping the planarization and the consistency of the semiconductor subassembly active surface that is embedded into wherein, and then promotes follow-up fine rule road and makes overweight manufacturing capacity.
Of the present invention again again a purpose be to provide a kind of chip embedding bury type packaging structure, thereby can integrate a plurality of semiconductor chips, promote the electrical functionality of electronic installation.
Of the present invention again again a purpose promptly be to provide a kind of chip embedding bury type packaging structure, with the heat that produces in effective dispersion semiconductor chip operation.
For achieving the above object, the present invention discloses a kind of chip embedding bury type packaging structure, and it comprises: the loading plate of at least one lug boss of a tool; At least one first semiconductor chip, it connects on the lug boss that places this loading plate, and has a plurality of electronic padses on this semiconductor chip; One insulating barrier, it is formed on this loading plate and this first semiconductor chip; An and line layer, it is formed on this insulating barrier, and this line layer is able to be electrically connected to the electronic pads of this first semiconductor chip by being formed at conductive structure in this insulating barrier, wherein, this encapsulating structure also can comprise at least one second semiconductor chip, it connects and places the zone beyond the lug boss on this loading plate, and have a plurality of electronic padses on this second semiconductor chip, and this line layer can be electrically connected to the electronic pads of this second semiconductor chip by being formed at conductive structure in this insulating barrier.The thickness of this second semiconductor chip can be different with this first semiconductor chip, and thickness that can be by adjusting lug boss is so that the electric connection surface of this first and second chip is maintained at same level.In addition, because of adapting to actual electrically design requirement, also can on this line layer, be formed with the circuit layer reinforced structure.
This loading plate and lug boss material formed thereon can be identical or different, and this loading plate and lug boss also can be integrated structure, and the material of this loading plate and lug boss can one of them be made by metal, pottery and high heat sink material.
Than prior art, chip embedding bury type packaging structure of the present invention, mainly semiconductor chip is connect on the lug boss that places loading plate, and can be by this loading plate lug boss to adjust insulating layer material between lug boss, to increase the thickness of layer insulating material and loading plate, so that the system control warping phenomenon that encapsulating structure is taken place when making variations in temperature in the process, the increase of encapsulating structure produces in the time of can avoiding increasing in the prior art heating panel thickness simultaneously and improve variations in temperature in the manufacture process the caused encapsulating structure thickness of warpage situation, weight and manufacturing cost.
In addition, the present invention can according to actual design need adjust lug boss thickness so that the semiconductor chip of different-thickness size connect place this loading plate after, the electric connection surface of described semiconductor chip maintains same plane, with planarization and the consistency of keeping the surface of insulating layer on the loading plate of taking in semiconductor chip, and then promote the follow-up reliability that circuit is made that on insulating barrier, forms.In addition, among the present invention, can take in this loading plate a plurality of functions inequality (or identical, also or part identical), the semiconductor chip of size difference (or part is different), and then can form the modularization encapsulating structure that is integrated with the multicore sheet, to meet the multi-functional demand of electronic product now.
In addition, on the insulating barrier and line layer of chip embedding bury type packaging structure of the present invention, also can carry out circuit and increase layer manufacturing, to form the multilayer wiring structure on high density and fine rule road on the loading plate that is embedded with semiconductor chip at this, simultaneously can plant a plurality of conductive components at the line construction outer surface, directly be electrically connected to external device (ED) for the semiconductor chip that is embedded in loading plate, therefore, but the present invention is the manufacturing and the encapsulation process of integrating semiconductor chip and chip bearing member also, the big demand elasticity of client is provided and simplifies semicon industry manufacture method and interface coordination problem.
Moreover, the loading plate of chip embedding bury type packaging structure of the present invention and lug boss are that one of them is made by the metal material of height heat radiation, ceramic material, high heat sink material, thereby it is extremely extraneous will directly to connect the heat loss fast and effectively that produces when semiconductor chip placed on it operates as heat dissipation path by this loading plate, prolongs the life-span of semiconductor chip and the reliability of encapsulating structure.
Description of drawings
Fig. 1 is the encapsulating structure of existing integrating semiconductor chip;
Fig. 2 A is the generalized section of chip embedding bury type packaging structure first preferred embodiment of the present invention;
Fig. 2 B is that the encapsulating structure generalized section that circuit increases layer manufacturing is carried out in chip embedding bury type packaging structure first preferred embodiment of the present invention; And
Fig. 3 is the generalized section of chip embedding bury type packaging structure second preferred embodiment of the present invention.
Description of reference numerals
1,2 encapsulating structures
12 heating panels
120 openings
13 semiconductor chips
130 electronic padses
14 insulating barriers
15 line layers
150 conductive structures
20 loading plates
201,202,20a, 20b lug boss
21a, 21b, 21c semiconductor chip
210a, 210b, 210c electronic pads
211a, 211b, 211c circuit face
212a, 212b, 212c inverter circuit face
23 insulating barriers
222 conductive structures
24 line layers
25 circuit layer reinforced structures
240 insulating barriers
242 line layers
The 242a conductive blind hole
244 electric connection pads
25 welding resisting layers
26 conductive components
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by the disclosed content of this specification.The present invention also can be implemented or used by other different specific embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications and change under the spirit of the present invention not deviating from.
Chip embedding bury type packaging structure principal character of the present invention is to have on its loading plate at least one for connecing the lug boss of putting semiconductor chip, be reduced graph and explanation, be that example is elaborated only among the figure of present embodiment, but be not restriction the present invention of usefulness to have two lug bosses on the loading plate.
See also Fig. 2 A, be the generalized section of the preferred embodiment that describes chip embedding bury type packaging structure of the present invention in detail.As shown in the figure, this encapsulating structure 2 comprises: a loading plate 20 is formed with lug boss 201,202 on this loading plate 20; Semiconductor chip 21a, 21b connect respectively on the lug boss 201,202 that places this loading plate 20; One insulating barrier 22 is formed on this loading plate 20 and those semiconductor chips 21a, the 21b; And one line layer 23 be formed on this insulating barrier 22, and make this line layer 23 be electrically connected to this semiconductor chip 21a, 21b.
In addition, this encapsulating structure 2 also can include at least one semiconductor chip 21c, and it connects and places the zone beyond the lug boss 201,202 on this loading plate 20, and this line layer 23 can be electrically connected to this semiconductor chip 21c again.
The material of this loading plate 20 can be identical or different with the material of this lug boss 201,202, can one of them is made by metal, pottery and high heat sink material.Above-mentioned this semiconductor chip 21a, 21b connect and place on this lug boss 201,202, and this semiconductor chip 21c directly connects and places on this loading plate 20.
In addition, this loading plate 20 also can be for example integrated structure of metal, pottery or high heat sink material with lug boss 201,202.
This semiconductor chip 21a, 21b are formed with active surface 211a, the 211b of the most electronic pads 210a of a tool, 210b, and non-active surface 212a, the 212b relative with this active surface, and this semiconductor chip 21a, 21b connect by an adhesion layer (scheme do not show) with its non-active surface 212a, 212b and place on this lug boss 201,202; Semiconductor chip 21c, directly connect and place on this loading plate 20, this semiconductor chip 21c is formed with the active surface 211c of a plurality of electronic pads 210c of a tool and the non-active surface 212c relative with this active surface, and this semiconductor chip 21c directly connects by an adhesion layer (figure does not show) with its non-active surface 212c and places on this loading plate 20. and above-mentioned those semiconductor chips 21a, 21b, 21c can be combination in any active or the passive type chip. and the thickness of other those semiconductor chips 21a, 21b, 21c can difference; And lug boss 201,202 height that are formed on this loading plate can add variation in response to the different-thickness of those semiconductor chips 21a, 21b, 21c, so that those semiconductor chips 21a, active surface 211a, the 211b of 21b, 21c, 211c are maintained on same plane, make thereby be beneficial to the fine rule road of on this chip, carrying out follow-up electrical extension.
This insulating barrier 22, it is formed on this loading plate 20 and those semiconductor chips 21a, 21b, the 21c, and makes in this insulating barrier 22 complete filling gap between adjacent protrusion portion.This insulating barrier 22 is organic film dielectric material or liquid organic resin material for example; Above-mentioned material can be selected from ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), LCP (Liquid Crystal Polymer), PI (Poly-imide), PPE (Poly (phenyleneether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aramid fiber sensitization or non-sensitization organic resins such as (Aramide), but or also material such as blending epoxy and glass fibre constitute.
This line layer 23 is formed on this insulating barrier 22, and can be electrically conducted to those semiconductor chips 21a by a plurality of conductive structures 222 (for example being conductive blind hole or conductive projection etc.) that are formed in this insulating barrier 22,21b, electronic pads 210a on the 21c, 210b, 210c, and can electrically connect semiconductor chip 21a by line layer 23,21b or 21c, on the part outer surface of this line layer 23, be formed with a plurality of electric connection pads 234 in addition, and on this line layer 23, be coated with a welding resisting layer 25, this welding resisting layer 25 has a plurality of openings to expose this electric connection pad 234, be equipped with a plurality of conductive component 26 in order to provide to plant, and those semiconductor chips and then can form the semiconductor chip package that is integrated with multi-chip moduleization.The generation type of this line layer 23 is this area manufacturing techniques available, gives unnecessary details so no longer write articles at this.
Than prior art, chip embedding bury type packaging structure of the present invention, mainly semiconductor chip is connect on the lug boss that places this loading plate, thereby can be by lug boss that this loading plate had to adjust the thickness of insulating barrier between lug boss, so that in the manufacture process during variations in temperature, the thermal stress that the balance encapsulating structure is suffered, thus encapsulating structure generation of warping phenomenon during variations in temperature in manufacture process can be avoided.And can provide by this lug boss to connect the preferable support effect of putting on it of chip, thereby can avoid the encapsulating structure warpage and cause the chip rhegma.
In addition, the present invention connects semiconductor chip and places on the lug boss, thereby can avoid the thickness of comprehensive increase loading plate of the prior art, and then can reduce the weight of this encapsulating structure finished product, and the present invention can according to actual design need adjust lug boss thickness so that the semiconductor chip of different-thickness connect place this loading plate after, the electric connection surface of described semiconductor chip maintains same plane, with planarization and the consistency that the surface of insulating layer on the loading plate of taking in semiconductor chip is provided, carry out the circuit manufacturing with conveniently follow-up, and then promote the follow-up reliability that circuit is made that on insulating barrier, forms.
Follow-up in encapsulating structure of the present invention, also can increase floor manufacturing in this insulating barrier 22 and line layer 23 enterprising line roads according to actual needs, connect with the circuit that constitutes required electrical design.
See also Fig. 2 B, for increasing the generalized section that floor is made formed encapsulating structure at insulating barrier 22 shown in Fig. 2 A and line layer 23 enterprising line roads.Structure shown in its structure and Fig. 2 A is roughly the same, but also is formed with a circuit layer reinforced structure 24 on this insulating barrier 22 and line layer 23.
This circuit layer reinforced structure 24 includes insulating barrier 240, is stacked and placed on the line layer 242 on this insulating barrier 240 and passes this insulating barrier 240 is electrically connected to insulating barrier below line layer 23 for this line layer 242 conductive blind hole 242a.
Other is formed with a plurality of electric connection pads 244 on the line layer of the outer surface of this circuit layer reinforced structure 24, and on this outermost layer circuit layer, be coated with a welding resisting layer 25, this welding resisting layer 25 has a plurality of openings to expose outside this electric connection pad 244, be equipped with a plurality of conductive component 26 in order to provide to plant, for example be tin ball (Solder ball), conductive pole or welding column, thereby for this semiconductor chip 21a that is accommodated in this loading plate 20,21b, 21c is able to by electronic pads 210a, 210b, 210c, line layer 23, this circuit layer reinforced structure 24 and this conductive component 26 and be electrically conducted to external electronic. in addition, should note, this circuit layer reinforced structure is non-to exceed with the illustrated number of plies, and can increase the number of plies in response to actual demand.
See also Fig. 3, be the generalized section of another preferred embodiment of describing chip embedding bury type packaging structure of the present invention in detail, different with last embodiment to be in this lug boss be to be integrally formed on the loading plate.As shown in the figure, be formed with lug boss 20a, 20b with electroforming or etched mode on this loading plate 20, put semiconductor chip 21a, 21b and connect respectively on this lug boss 20a, the 20b, those semiconductor chips 21a, active surface 211a, the 211b of 21b, 21c, 211c are maintained on same plane, make thereby be beneficial to the fine rule road of on this chip, carrying out follow-up electrical extension.
Therefore, chip embedding bury type packaging structure of the present invention, mainly be that semiconductor chip is positioned on the lug boss of loading plate, and can be by lug boss that this loading plate had to adjust the insulating layer material between lug boss, increase the thickness of layer insulating material and loading plate, so that the suffered thermal stress of chip-packaging structure during variations in temperature in the balance manufacture process, thereby the generation of encapsulating structure warping phenomenon in the time of can avoiding variations in temperature in the manufacture process can avoid increasing in the prior art the caused encapsulating structure thickness of warpage situation that heating panel thickness encapsulating structure when improving variations in temperature in the manufacture process produces simultaneously, the increase of weight and manufacturing cost.In addition, the present invention can according to actual design need adjust lug boss thickness so that the semiconductor chip of different-thickness connect place this loading plate after, the electric connection surface of described semiconductor chip maintains same plane, with the planarization and the consistency of the surface of insulating layer on the loading plate surface that keeps taking in semiconductor chip, and then promote the follow-up reliability that on insulating barrier, forms the circuit manufacture method.In addition, among the present invention, can take in this loading plate most functions inequality (or identical, also or part identical) semiconductor chip so that can form the semiconductor chip package that is integrated with multi-chip moduleization, to meet the multi-functional demand of electronic product now.
In addition, on the insulating barrier and line layer of chip embedding bury type packaging structure of the present invention, also can carry out circuit and increase layer manufacturing, to form the multilayer wiring structure on high density and fine rule road on the loading plate that is embedded with semiconductor chip at this, simultaneously can plant a plurality of conductive components at the line construction outer surface, directly be electrically connected to external device (ED) for the semiconductor chip that is embedded in loading plate, therefore, but the present invention is the manufacturing and the encapsulation process of the bearing part of integrating semiconductor chip also, the big demand elasticity of client is provided and simplifies semicon industry manufacturing and interface coordination problem.
In addition, the loading plate of chip embedding bury type packaging structure of the present invention is metal material, ceramic material or the high heat sink material manufacturing by the height heat radiation, thereby the heat that produces can will directly connect semiconductor chip placed on it work as heat dissipation path by this loading plate the time dissipates to the external world fast and effectively, prolongs the life-span of semiconductor chip and the reliability of encapsulating structure.
The foregoing description only is illustrative principle of the present invention and technique effect thereof, but not is used to limit the present invention.Any those skilled in the art all can make amendment to the foregoing description under spirit of the present invention and category.So the scope of the present invention, claims are listed as the aforementioned.
Claims (14)
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| CN200610143530A CN101179066B (en) | 2006-11-10 | 2006-11-10 | Chip embedded type packaging structure |
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| CN200610143530A CN101179066B (en) | 2006-11-10 | 2006-11-10 | Chip embedded type packaging structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US11399438B2 (en) | 2019-01-07 | 2022-07-26 | Delta Electronics (Shanghai) Co., Ltd. | Power module, chip-embedded package module and manufacturing method of chip-embedded package module |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI449271B (en) * | 2011-11-16 | 2014-08-11 | Dawning Leading Technology Inc | Electrical device with connection interface, circuit board thereof, and method for manufacturing the same |
| KR20150045815A (en) * | 2013-10-21 | 2015-04-29 | 페어차일드코리아반도체 주식회사 | Power module package |
| CN107068579A (en) * | 2013-10-22 | 2017-08-18 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
| US10685904B2 (en) * | 2014-11-21 | 2020-06-16 | Delta Electronics, Inc. | Packaging device and manufacturing method thereof |
| CN105701532B (en) * | 2014-11-25 | 2018-09-11 | 茂邦电子有限公司 | The wafer package part and its molding sheet shape package board and forming method of chip card |
| JP6418126B2 (en) | 2015-10-09 | 2018-11-07 | 三菱電機株式会社 | Semiconductor device |
| CN106571343A (en) * | 2016-11-18 | 2017-04-19 | 三星半导体(中国)研究开发有限公司 | Wafer level fan-out type packaging member integrated with passive element and manufacturing method thereof |
| CN113053852B (en) * | 2019-12-26 | 2024-03-29 | 钰桥半导体股份有限公司 | Semiconductor components |
| CN115763449A (en) * | 2022-11-21 | 2023-03-07 | 中山芯承半导体有限公司 | A packaging structure with small chips of different thicknesses and its manufacturing method |
| CN117766478A (en) * | 2023-12-28 | 2024-03-26 | 昆山国显光电有限公司 | Chip packaging structure and packaging chip |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1395461A (en) * | 2002-07-17 | 2003-02-05 | 威盛电子股份有限公司 | Integrated module board with embedded IC chip and passive element and its production method |
| CN1677665A (en) * | 2004-03-29 | 2005-10-05 | 三洋电机株式会社 | Circuit device and manufacturing method thereof |
-
2006
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1395461A (en) * | 2002-07-17 | 2003-02-05 | 威盛电子股份有限公司 | Integrated module board with embedded IC chip and passive element and its production method |
| CN1677665A (en) * | 2004-03-29 | 2005-10-05 | 三洋电机株式会社 | Circuit device and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11399438B2 (en) | 2019-01-07 | 2022-07-26 | Delta Electronics (Shanghai) Co., Ltd. | Power module, chip-embedded package module and manufacturing method of chip-embedded package module |
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