CN101136588B - Voltage conversion circuit and display device having the voltage conversion circuit - Google Patents

Abstract

A booster circuit of a two-step booster structure is manufactured by NMOS single channel processes and has two basic booster circuits to raise a gate voltage of a charge transfer transistor. The gate voltage of the transistor is first raised at one basic booster circuit, and this raised voltage is further raised at the other basic booster circuit.

Description

Voltage conversion circuit and display device having the voltage conversion circuit

technical field

The present invention relates to a voltage conversion circuit for converting an input voltage and outputting it, and a display device having the voltage conversion circuit, in particular to a driving circuit for a display device of a portable device.

Background technique

The pixel portion has a switching element, and a TFT (Thin Film Transistor) type liquid crystal display device is widely used as a display device such as a computer. In addition, TFT type display devices are also used as display devices of portable terminal devices such as mobile phones. Display devices used in portable terminal devices are required to be smaller in size and have power saving performance than conventional liquid crystal display devices.

As a problem accompanying miniaturization, the problem of a reduction in space for mounting a drive circuit of a display device can be cited. The appearance of a general display device is preferably such that the peripheral part is narrower than the display area (narrow edge). However, the peripheral portion of the display area is an area for mounting a driving circuit. Therefore, due to the narrow edge, the driving circuit is more miniaturized, and the mounting area is limited to a very narrow one. In addition, the development of a display device with a higher resolution is accompanied by an increase in the number of outputs from a driving circuit, and the pitch of connection terminals becomes narrower, which leads to a problem that connection reliability decreases.

Therefore, to realize the driving circuit on a smaller area, and to further eliminate the problem of connection, in the same manufacturing process as the switching element in the pixel part, the driving circuit is also manufactured on the same substrate with the switching element, which is the so-called driving circuit. Circuit-integrated display devices are being developed and put into practical use.

On the other hand, a display device of a portable terminal device is required to have low power consumption. In addition, it is also required to be driven by a portable power source such as a battery. However, various voltages are required to drive the display device, and when using a low voltage such as a battery as a single-voltage power source, it is necessary to form a voltage for driving the display device from the power supply voltage through a booster circuit or the like.

A booster circuit used for this purpose is disclosed, for example, in US Patent Application Laid-Open 2005/0206441 (JP-A-2005-304285).

The boost circuit has a first transistor, a second transistor, a first capacitive element, a second capacitive element, a diode, and a conversion device. The capacitive element is connected to the gate electrode of the first transistor and the electrode on one side of the second transistor, the input side of the conversion device is connected to the other side electrode of the first transistor through the first capacitive element, and is connected to the gate electrode of the second transistor , the diode is forwardly connected between the other electrode of the first transistor and the other electrode of the second transistor.

However, the booster circuit described in US Laid-Open Patent No. 2005/0206441 is based on the premise of forming a CMOS process, and does not disclose a booster circuit formed by using an NMOS single channel (chanel). Furthermore, the influence on the threshold Vth shift has not been sufficiently considered.

That is to say, the circuit described in US Laid-Open Patent No. 2005/0206441 is formed on the premise of using a CMOS process, because transistors with N and P bipolarity are required, and the manufacturing cost becomes very high.

In addition, in the circuit described in US Laid-Open Patent No. 2005/0206441, when the threshold value Vth is increased due to manufacturing variation, a sufficiently large gate voltage cannot be supplied to the charge transfer switch, and the characteristics of the power supply circuit deteriorate due to the on-resistance of the switch.

Contents of the invention

It is an object of the present invention to provide a voltage conversion circuit with good characteristics and a display device using the voltage conversion circuit while suppressing the influence of threshold value variation.

A pixel electrode, a switching element for supplying an image signal to the pixel electrode, a driving circuit for supplying an image signal to the switching element, a driving circuit for outputting a scanning signal, and a voltage conversion circuit (for example, a booster circuit) are provided on the same substrate, and these are passed through an NMOS Single channel method is formed.

Specifically, the drain and gate of the first transistor are connected to the voltage input terminal, the source of the first transistor is connected to the first node, the drain of the second transistor is connected to the voltage input terminal, and the The gate is connected to the second node, the source of the second transistor is connected to the first node, the drain of the third transistor is connected to the voltage input terminal, the gate of the third transistor is connected to the first node, and the third The source of the transistor is connected to the second node, the drain of the fourth transistor is connected to the second node, the gate of the fourth transistor is connected to the third node, the source of the fourth transistor is connected to the fourth node, and The drain of the fifth transistor is connected to the second node, the gate of the fifth transistor is connected to the voltage output terminal, the source of the fifth transistor is connected to the fourth node, and the drain of the sixth transistor is connected to the second node , connect the gate of the sixth transistor to the fourth node, connect the source of the sixth transistor to the voltage output terminal, connect the drain and gate of the seventh transistor to the second node, connect the source of the seventh transistor Connect to the third node, connect the drain of the eighth transistor to the second node, connect the gate of the eighth transistor to the fourth node, connect the source of the eighth transistor to the third node, connect the first capacitive element Connect between the first control signal input terminal and the first node, connect the second capacitive element between the second control signal input terminal and the fourth node, connect the third capacitive element between the third control signal input terminal and the first node Between the three nodes, the fourth capacitive element is connected between the fourth control input signal terminal and the second node, and the fifth capacitor is at least connected between the voltage output terminal and the ground or between the voltage input terminal and the ground. one. Regarding the voltage conversion circuit, in order to boost the gate voltage of the charge transfer switch, two booster circuits using capacitive elements for the charge transfer switch are provided, and one booster circuit is used in advance to boost the gate voltage of the charge transfer switch. After the voltage, another boost circuit is used to further boost the voltage.

The present invention also provides a display device using the voltage conversion circuit, specifically as follows, a display device with the voltage conversion circuit includes:

A display panel having a plurality of pixel electrodes arranged in a matrix;

a switching element for providing an image signal to the pixel electrode;

an image signal line, providing an image signal to the switching element;

A scanning signal line, providing a scanning signal for controlling the switching element;

a first drive circuit that outputs the image signal and is formed on the display panel in the same process as the switching element;

a second driving circuit, outputting the scanning signal;

The voltage conversion circuit is formed in the display panel in the same process as the switching element.

The present invention provides a display device having the voltage conversion circuit, wherein the voltage generated by the voltage conversion circuit is used as the driving voltage of the display device.

The present invention also provides a voltage conversion circuit, which converts the input voltage and outputs it.

characterized in that it includes first to eighth transistors and first to fifth capacitive elements,

connecting the drain and the gate of the first transistor to the voltage input terminal, connecting the source of the first transistor to the first node,

connecting the drain of the second transistor to the voltage input terminal, connecting the gate of the second transistor to the second node, connecting the source of the second transistor to the first node,

connecting the drain of the third transistor to the voltage input terminal, connecting the gate of the third transistor to the first node, and connecting the source of the third transistor to the second node,

connecting the first capacitive element between the first control signal input terminal and the first node,

A plurality of circuit blocks are connected in series between the above-mentioned third transistor source and the voltage output terminal, the circuit block

Connect the drain of the above-mentioned fourth transistor to the above-mentioned second node, connect the gate of the above-mentioned fourth transistor to the third node, connect the source of the above-mentioned fourth transistor to the fourth node, connect the drain of the above-mentioned fifth transistor to Connect the pole to the second node, connect the gate of the fifth transistor to the output of the circuit block, connect the source of the fifth transistor to the fourth node, connect the drain of the sixth transistor to the The second node connects the gate of the sixth transistor to the fourth node, connects the source of the sixth transistor to the output of the circuit block, and connects the drain and gate of the seventh transistor to the first node. Two nodes, the source of the seventh transistor is connected to the third node, the drain of the eighth transistor is connected to the second node, the gate of the eighth transistor is connected to the fourth node, and the The source of the eighth transistor is connected to the third node, the second capacitive element is connected between the second control signal input terminal and the fourth node, and the third capacitive element is connected between the third control signal input terminal and the fourth node. Between the above-mentioned third node, the above-mentioned fourth capacitive element is connected between the fourth control signal input terminal and the above-mentioned second node, the gate of the above-mentioned seventh transistor is used as the input of the circuit block, and the gate of the above-mentioned fifth transistor is gate as the output of this circuit block,

connecting said fifth capacitive element to at least one of between said voltage output terminal and ground or between said voltage input terminal and ground,

The first to fourth control signal input terminals are input with first to fourth control signals having different rising edge timings,

The input terminal of the first circuit block among the plurality of circuit blocks is connected to the source of the third transistor,

an output terminal of a first circuit block among the plurality of circuit blocks is connected to an input terminal of a second circuit block among the plurality of circuit blocks,

an output terminal of a second circuit block among the plurality of circuit blocks is connected to an input terminal of a third circuit block among the plurality of circuit blocks,

An output terminal of an nth circuit block among the plurality of circuit blocks is connected to an input terminal of an n+1th circuit block among the plurality of circuit blocks.

The present invention also provides a display device with the voltage conversion circuit, comprising:

A display panel having a plurality of pixel electrodes arranged in a matrix;

a switching element for providing an image signal to the pixel electrode;

an image signal line, providing an image signal to the switching element;

A scanning signal line, providing a scanning signal for controlling the switching element;

a first drive circuit that outputs the image signal and is formed on the display panel in the same process as the switching element;

a second driving circuit, outputting the scanning signal;

The above-mentioned voltage conversion circuit is formed in the above-mentioned display panel in the same manner as the above-mentioned switching element.

The present invention also provides a display device with the voltage conversion circuit, characterized in that the voltage generated by the voltage conversion circuit is used as the driving voltage of the display device.

The present invention provides a display device, which includes:

A display panel having a plurality of pixel electrodes arranged in a matrix;

a first driving circuit, providing image signals to the plurality of pixels;

a second drive circuit that supplies a scan signal for selecting a pixel to be supplied with the image signal to the pixel;

a power supply circuit that boosts a power supply voltage and applies it to the above-mentioned first drive circuit and the above-mentioned second drive circuit;

The power supply circuit includes first and second charge transfer circuits for boosting voltage, and an extraction capacitor circuit connected between the first charge transfer circuit and the second charge transfer circuit;

The power supply circuit charges the power supply voltage to the extraction capacitor circuit through the first charge transfer circuit, and then raises the potential of the connecting portion of the first charge transfer circuit, the second charge transfer circuit, and the extraction capacitor circuit with a clock signal. , output through the above-mentioned second charge transfer circuit.

The above power supply circuit also includes,

a first booster circuit for boosting the gate voltage of the first charge transfer circuit;

a second voltage boosting circuit that boosts the gate voltage of the second charge transfer circuit;

A third booster circuit is connected between the first charge transfer circuit and the second charge transfer circuit, and boosts a gate voltage of the second booster circuit to boost an initial voltage of the second booster circuit.

In the present invention, since the circuit is formed by the NMOS single-channel method, the cost can be reduced compared to the case of using the CMOS process.

In addition, in the present invention, since the drop in the gate voltage of the charge transfer switch due to threshold deviation can be compensated, it is possible to realize good power supply circuit characteristics without being affected by manufacturing offset.

Description of drawings

FIG. 1 shows a schematic block diagram of a display device according to an embodiment of the present invention;

What Fig. 2 represented is the schematic waveform diagram of the driving signal used for the display device of the embodiment of the present invention;

What Fig. 3 represented is the step-up circuit diagram for the high-voltage VGH related to the first embodiment of the present invention;

What Fig. 4 shows is the schematic diagram of the waveforms of each part of the booster circuit for the high voltage VGH related to the first embodiment of the present invention;

What Fig. 5 represented is the step-up circuit diagram for the low voltage VGL related to the first embodiment of the present invention;

What Fig. 6 represented is the schematic diagram of the waveforms of various parts of the booster circuit for the low voltage VGL related to the first embodiment of the present invention;

What Fig. 7 represented is the schematic block diagram of the liquid crystal display panel of the embodiment of the present invention;

What Fig. 8 shows is the step-up circuit diagram for the high-voltage VGH related to the second embodiment of the present invention;

What Fig. 9 has shown is the step-up circuit diagram for the low voltage VGL related to the second embodiment of the present invention;

What Fig. 10 represented is the schematic diagram of the clock waveform of the boost circuit relevant to the second embodiment of the present invention;

What Fig. 11 shows is the step-up circuit diagram for the high-voltage VGH related to the third embodiment of the present invention;

What Fig. 12 has shown is the step-up circuit diagram for the low voltage VGL related to the third embodiment of the present invention;

What Fig. 13 represented is the schematic diagram of the waveforms of various parts of the boost circuit related to the third embodiment of the present invention;

FIG. 14 is a schematic diagram showing waveforms of various parts of the boost circuit related to the third embodiment of the present invention.

Detailed ways

Embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. In addition, in all the drawings for describing the embodiments, the symbols having the same functions are denoted by the same symbols, and repeated descriptions are omitted.

FIG. 1 is a block diagram showing the basic structure of a liquid crystal display device according to an embodiment of the present invention. As shown in the figure, the liquid crystal display device 100 is composed of a liquid crystal display panel 1 and a control circuit 3 . In addition, the main device 101 is connected to the liquid crystal display device 100 through the elastic substrate 30 . The liquid crystal display device 100 is used as a display unit of this main device. The main device 101 uses the battery 70 as a power source, and the liquid crystal display device 100 is supplied with a power supply voltage from the main device 101 using the wiring 32 .

The liquid crystal display panel 1 includes an element substrate 2 made of an insulating substrate such as transparent glass or plastic and a semiconductor substrate, and an opposing substrate (not shown). The element substrate 2 and the opposite substrate are overlapped with a set gap, and the two substrates are bonded by a frame-shaped sealing member provided near the peripheral portion between the two substrates, and the liquid crystal sealing port provided on a part of the sealing member is sealed. Liquid crystal is sealed inside the sealing member between the two substrates, and a polarizing plate is attached on the outside of the two substrates to form a liquid crystal display panel.

Pixels 8 are arranged in a matrix on the element substrate 2 to form a display region 9 . The pixel 8 is provided with a pixel electrode 11 and a thin film transistor 10 as a switching element. Each pixel corresponds to the intersection of a plurality of scanning signal lines (or gate signal lines) 20 and image signal lines (or drain signal lines) 25 .

The source of the thin film transistor 10 of each pixel is connected to the pixel electrode 11 , the drain is connected to the image signal line 25 , and the gate is connected to the scanning signal line 20 . The thin film transistor 10 functions as a switch for supplying a display voltage (gradation voltage) to the pixel electrode 11 .

In addition, although the terms of source and drain are sometimes reversed due to the relationship of the bias voltage, the one connected to the image signal line 25 is referred to as the drain here.

In addition, although FIG. 1 describes a so-called transverse electric field liquid crystal display panel in which the opposite electrode 15 is provided on the element substrate 2, a so-called vertical electric field liquid crystal display panel in which the opposite electrode 15 is provided on the opposite substrate, This embodiment is also applicable.

The booster circuit 4 , the image signal circuit 50 , and the scanning signal circuit 60 are respectively formed on a transparent insulating substrate (glass substrate, resin substrate, etc.) constituting the element substrate 2 of the liquid crystal display panel 1 . In addition, the control device 3 is an IC chip, and is directly mounted on the liquid crystal display panel 1 . Digital signals (display data, clock signals, control signals, etc.) sent from the control device 3 are input to the booster circuit 4 , the image signal circuit 50 , and the scanning signal circuit 60 through the input terminal 35 . The control device 3 is composed of a semiconductor integrated circuit (LSI), and based on various display control signals such as a clock signal, a display time signal, a horizontal synchronization signal, and a vertical synchronization signal sent from the outside, and display data (R·G·B), Drive and control the boost circuit 4 , the image signal circuit 50 , and the scan signal circuit 60 .

The boost circuit 4, the image signal circuit 50, the scan signal circuit 60 and the thin film transistor are formed in the same process, the scan signal circuit 60 drives the scan signal line 20, the image signal circuit 50 drives the image signal line 25, and the boost circuit 4 Generate and supply necessary voltages to drive each circuit. Reference numerals 36 and 37 denote external capacitive elements, and the capacitive element 36 is provided on the elastic substrate 30 . In addition, the capacitive element 37 is mounted and connected to the liquid crystal display panel 1 through terminals provided on the liquid crystal display panel 1 .

The scan signal circuit 60 sequentially scans each frame of the liquid crystal display panel 1 in each horizontal scan time according to the frame start instruction signal (FLM, hereinafter referred to as start signal) and the shift clock (CL1) sent by the control device 3. The signal line 20 supplies a high-level selection scan voltage (scan signal). Thereby, the plurality of thin film transistors 10 connected to the respective scanning signal lines 20 of the liquid crystal display panel 1 are turned on for one horizontal scanning time.

In addition, the image signal circuit 50 outputs to the image signal line 25 gradation voltages that will display pixels and correspond to gray scales. When the thin film transistor 10 is turned on, a gradation voltage (image signal) is supplied from the image signal line 25 to the pixel electrode 11 . Thereafter, when the thin film transistor 10 is turned on, the pixel electrode 11 holds a gradation voltage based on the image of the pixel to be displayed.

Next, the booster circuit 4 used in the power supply circuit will be described. In small portable devices such as mobile phones, batteries are generally used as a power source. In addition, the output voltage ranges from 1.3V to 3V depending on the amount of current used by the battery. Therefore, it is necessary to use the booster circuit 4 to generate a necessary power supply voltage for the liquid crystal display device.

FIG. 2 shows various signals of a thin film transistor type liquid crystal display device and power supply voltages required for forming the signals. In FIG. 3, VGON is a high voltage of a scanning signal for turning on a thin film transistor (TFT). The range is 7V ~ 15V. VGOFF is a low voltage of a scan signal for turning off a thin film transistor (TFT). The range is -2V ~ -5V. DDVDH is a power supply voltage for the image signal circuit 50 and the scanning signal circuit 60 shown in FIG. 2 .

In the power supply necessary for the above liquid crystal display device, the booster circuit 4 of the charge pump method of the present invention is used to generate the high voltage VGH for the scanning signal circuit and the low voltage VGL for the scanning signal circuit, and the other voltages are formed by the booster circuit. The voltage is formed after equal voltage division.

Next, the booster circuit for high voltage VGH and the booster circuit for low voltage VGL related to this embodiment will be described with reference to FIG. 3 , FIG. 4 , FIG. 5 , and FIG. 6 .

Figure 3 shows a booster circuit for high voltage VGH. The voltage boosting circuit for VGH is composed of a pumping capacitance element Cp, a stabilizing capacitance element Cs, boosting capacitance elements C1, C2, and C3, and transistors TR1 to TR8. Here, the transistors TR1 to TR8 are formed by an NMOS process. TR3 and TR6 are charge transfer switches. The characteristic of this booster circuit is that once the input voltage VA is charged to the extraction capacitive element Cp through the charge transfer switch TR3, the potential of the node NP is boosted by the extraction clock cycle CKP, and the high voltage VGH is supplied to the output terminal through the switch TR6. The present invention is not limited to the circuit configuration of the embodiment as long as the function can be realized.

Here, the circuit constituted by the transistor TR1 and the capacitive element C1 is a circuit for boosting the gate voltage of the charge transfer switch TR3 at the input end. In addition, a circuit constituted by the transistor TR4 and the capacitive element C2 is a circuit for boosting the gate voltage of the output-side charge transfer switch TR6. The circuit constituted by the transistor TR7 and the capacitive element C3 boosts the gate voltage of TR4 to boost the initial voltage of C2. The transistors TR2 , TR5 , and TR8 are diode-connected to the transistors TR3 , TR6 , and TR4 when their respective gate voltages rise, and through these, reverse flow of charge is prevented.

Next, details of the operation of the booster circuit for VGH will be described in detail with reference to FIGS. 3 and 4 . Timings of the power supply circuit control clocks CKA, CKB, CKC, and CKP are set as shown in FIG. 4 . Here, as a specific example, a case where the input voltage VA=5V and the amplitudes of the control clocks CKA, CKB, CKC, and CKP are 5Vpp will be described. First, if a DC voltage VA=5V is input to the input, the capacitance element C1 is charged with a voltage lower than Vth through the diode-connected transistor TR1. If the clock CKA is high at time t5, the node NA is boosted to 10-Vth, TR3 is turned on, and the input voltage VA=5V is charged to the capacitive element Cp. Then, if CKA is low at time t6 (t0), TR3 is turned off, and CKP is high at t7 (t1), node NP is boosted to 10V. Thus, node NC is charged to about 10-Vth through TR7, and if CKC is high at t8 (t2), NC will be temporarily charged to 15-Vth. If CKB is high at t9 (t3), NB (the gate voltage of TR6) is boosted to 15-Vth, and TR6 is turned on. Thus, the charge of Cp is supplied to the output terminal through TR6. By repeating the above work, the charge is supplied from the input terminal to the output terminal repeatedly, and a fixed voltage of 10V is supplied to the output terminal.

In this booster circuit, before boosting by the clock CKC, the potential of the node NC is precharged to about 10-Vth, so the potential of the NC can be set to 10+Vth or more by boosting using CKC. Therefore, the potential of NB can be set at about 10V in advance, and the voltage of NB (the gate voltage of TR6) can be sufficiently increased even when Vth is large by using CKB to boost the voltage. As a result, since the on-resistance of TR6 can be made small, a large current can be supplied to the output terminal without greatly reducing the output voltage.

FIG. 5 shows a booster circuit for low voltage VGL. The booster circuit for low voltage VGL uses the same circuit configuration 300 as the booster circuit for VGH, and is realized by reversing the relationship between input and output. The control clocks CKA, CKB, CKC, CKP and VGH are the same.

In the booster circuit for VGL, when the input voltage VB is input and CKB goes high, the input voltage VB is charged to the node NP. Then, TR6 is cut off, and the potential of NP drops as soon as CKP becomes low. After that, TR3 is turned on, and a current flows from the output terminal to Cp. The charge flowing into Cp is released to the input terminal when TR6 is turned on next. By repeating this work, the output voltage VA gradually decreases, and a fixed negative voltage can be supplied to the output. For example, when the input voltage VB=3V and the amplitude of CKP is 5Vpp, the steady state output voltage is VA=3V-5V=-2V.

Next, the operation of the booster circuit for VGL will be described in detail with reference to FIGS. 5 and 6 . Timings of the control clocks CKA, CKB, CKC, and CKP are the same as in the case of the high voltage VGH. Here, as a specific example, the case where the input voltage VB=3V and the amplitudes of the control clocks CKA, CKB, CKC, and CKP are 5Vpp will be specifically described. First, given that the extraction clock CKP is in a high state, the input voltage VB=3V, at time t3 (t9) when CKB is high, TR6 is turned on, and the node NP is discharged to the input voltage VB=3V (the voltage of Cp is 3V- 5V=-2V). Then, at t4 if CKB and CKC are low, TR6 is turned off. At this time, CKP is also low, and NP is -2V. If CKA is high at t5, the node NA is boosted to 3V, TR3 is turned on, and current flows from the output terminal to Cp. As a result, the output voltage is -2V. Then, at time t6 (t0) if CKA is low, TR3 is cut off, and at t7 (t1) if CKP is high, node NP is boosted to 3V. At this time, NC is charged to about 3-Vth through TR7, and if CKC is high at t8 (t2), NC is temporarily charged to 8-Vth. At t9 (t3) if CKB is high, node NB (the gate voltage of TR6) is boosted to 8V, and TR6 is turned on. As a result, the charge flowing into Cp from the output terminal when TR3 is turned on is discharged at the input terminal through TR6. Repeating the above work can provide a fixed negative voltage VGL=-2V to the output terminal.

In the boost circuit for VGL, like the boost circuit for VGH, the initial voltage of NB can be made higher by using the boost circuit of C3 and TR7, so when boosting the voltage caused by CKB, the voltage of TR6 The gate voltage can then become very large. Therefore, when TR6 is turned on, the on-resistance of TR6 can be made sufficiently small, so that a large current can be supplied to the output terminal without greatly changing the output voltage.

Next, the driving circuit of the liquid crystal display panel 1 to which the voltage boosting circuit of the present invention is applied will be described with reference to FIG. 7 . FIG. 7 is a block diagram showing the basic structure of the liquid crystal display panel 1 of the embodiment of the present invention. As shown in the figure, the liquid crystal display panel 1 has an insulating substrate (element substrate) 2 made of transparent glass or plastic. Pixels 8 are arranged in a matrix on the insulating substrate 2 to form a display area 9 . A pixel electrode 11 and a switching element 10 are provided on the pixel 8 .

Around the display area 9 , along the edge of the insulating substrate 2 , an image signal circuit 50 , a scanning signal circuit 60 , and a booster circuit 4 are formed. The image signal circuit 50, the scanning signal circuit 60, and the booster circuit 4 are formed on the insulating substrate 2 in the same process as the switching element 10, so that they can be miniaturized compared with semiconductor chips formed in other processes.

The semiconductor layer composed of the image signal circuit 50 , the scanning signal circuit 60 , the booster circuit 4 , and the switching element 10 uses a polysilicon film. The polysilicon film is supplied with energy to the amorphous silicon film deposited on the insulating substrate 2 by laser irradiation or the like by the CVD method, etc., and the crystal grain diameter is increased by recrystallization or the like compared with the above-mentioned amorphous silicon film.

The scanning signal line 20 extends from the scanning signal circuit 60 to the display area, and the scanning signal line 20 is electrically connected to the control terminal of the switching element 10 . A scan signal for turning on and off the switching element 10 is output from the scan signal circuit 60 to the scan signal line 20 .

The scanning signal circuit 60 is provided with a shift register circuit 61, and the shift register circuit 61 outputs a pulse signal to the scanning signal line 20 so as to output a voltage for turning on the switching element 10 during one horizontal period.

Although the high voltage boosted by the booster circuit 4 can be used to drive the shift register circuit 61, it is also possible to drive the shift register circuit 61 with a low voltage, and the output pulse signal is converted into a high voltage by the level shift circuit 62. The pulse is output to the scanning signal line 20. At this time, a high-voltage power supply line 64 is wired and electrically connected from the booster circuit 4 to each level shift circuit 62 . Furthermore, the wiring 65 is a signal line for supplying a clock to the shift register circuit 61 .

Adjacent to the scan signal circuit 60, a counter voltage supply circuit 7 is provided. The counter voltage supply circuit 7 divides each counter voltage supply line and supplies the counter voltage to the counter electrodes, and is an effective circuit suitable for an IPS type liquid crystal display device in which the counter electrodes of each pixel are separated. To this end, a high-voltage power supply line is also wired and electrically connected to the relative voltage supply circuit 7 .

From the image signal circuit 50 , the image signal line 25 extends to the display area 9 , and the image signal line 25 is connected to the input terminal of the switching element 10 . The image signal is output from the image signal circuit 50 to the image signal line 25 , and the image signal is written into the pixel electrode 11 through the switching element 10 turned on by the scanning signal.

The image signal circuit 50 has an output gate circuit 53 and outputs an image signal supplied from the outside to the image signal line 25 in accordance with a timing pulse output by the shift register circuit 51 . When the image signal is directly supplied from the outside of the liquid crystal display panel 1, the output voltage of the shift register circuit 51 may not be sufficient to turn on the output gate circuit 53 when the voltage range of the image signal is wide. Therefore, using the level shift circuit 52 , it is possible to output a voltage sufficient to turn the gate circuit 53 into a conductive state within the voltage range of the image signal. Therefore, the image signal circuit 50 is also wired and electrically connected from the booster circuit 4 .

In FIG. 7 , the transfer pulse of the shift register circuit 51 and the boost pulse of the booster circuit 4 are used simultaneously, and the transfer pulse wiring 55 is connected between the shift register circuit 51 and the booster circuit 4 . In addition, the electrode 41 for an output capacitor is formed on the insulating substrate 2 in the same process as that of the switching element 10 .

On the liquid crystal display panel 1 shown in FIG. 7, the scanning signal circuit 60, the image signal circuit 50, and the boosting circuit 4 can be formed on the same substrate, thereby reducing the number of external components and saving the installation space of related components. In addition, the connection reliability of each component is also improved.

The boost circuit related to the second embodiment of the present invention adopts two basic boost circuits, and makes them work in parallel so as to obtain a large output current.

In general, in a gate scanning circuit in a liquid crystal display device, a large amount of charge and discharge current flows when these are driven due to the wiring capacity of gate lines and the like. This charging and discharging current is supplied by the power supply circuits of high voltage VGH and low voltage VGL, and a large output current is required in these circuits. In addition, because the voltages of VGH and VGL correspond to the gate voltages of the on and off gates of the TFT, it is required that the output voltages of VGH and VGL vary very little even when the output current is large. The purpose of this embodiment is to provide a booster circuit that solves these problems.

The boost circuit related to the second embodiment of the present invention will be described with reference to FIG. 8 , FIG. 9 , and FIG. 10 .

FIG. 8 shows a booster circuit for high voltage VGH related to the second embodiment. This booster circuit is composed of two basic booster circuits 300 connected in parallel. 803 is a boost capacitor element, and 804 is a stable capacitor element. Here, since the basic booster circuit 300 is the same as the VGH booster circuit ( FIG. 3 ) described in the first embodiment, description of the circuit configuration is omitted.

The operation of the boost circuit is described in conjunction with FIG. 10 . The phase relationship of the control clocks CKA1, CKB1, CKC1, and CKP1 for the first booster circuit is the same as that of the first embodiment. In addition, the phase relationship of the control clocks CKA2, CKB2, CKC2, and CKP2 for the second booster circuit is It is also the same as the case of the first embodiment. Therefore, the first and second booster circuits operate to boost the input voltage and supply it to the output terminal, similarly to the booster circuit for VGH in the first embodiment.

In this embodiment, as shown in FIG. 10 , the control clocks of the first and second voltage boosting circuits are staggered by a half cycle, and each voltage boosting circuit alternately supplies current to the output terminal every half cycle. Therefore, compared to using a single booster circuit, it is possible to supply twice the current to the output.

FIG. 9 shows a booster circuit for low voltage VGL related to the second embodiment. The booster circuit for low voltage VGL related to the second embodiment is the same as the booster circuit for VGL in the first embodiment, and the relationship between the input and output of the booster circuit for VGH is reversed. Similar to the step-up circuit for VGH, two basic circuits for VGL are driven in parallel with a half-period shift in order to obtain twice the output current. Regarding the control clock, since it is the same as the booster circuit for VGH, description thereof will be omitted.

Also, since the structure of the display device using the power supply circuit related to the second embodiment is the same as that of the first embodiment, description thereof will be omitted.

The boost circuit related to the third embodiment of the present invention is connected in series with two or more charge pump circuits, and because the voltage is boosted sequentially, a higher high voltage VGH and a lower low voltage VGL can be obtained.

11, FIG. 12, FIG. 13, and FIG. 14, the boost circuit related to the third embodiment of the present invention will be described.

FIG. 11 shows a booster circuit for high voltage VGH related to the third embodiment. In this booster circuit, two stages of charge pump circuits for high voltage VGH are connected in series, and the output voltage of the first charge pump circuit 300 is further boosted by the second charge pump circuit to obtain a higher high voltage VGH. Here, the charge transfer switch via the output of the first charge pump circuit also serves as the charge transfer switch at the input of the second charge pump circuit.

The time chart of this boost circuit is shown in Figure 12. As shown in Figure 12, the phase relationship of the control clocks CKA1, CKB1, CKC1, CKP1 of the first charge pump circuit is the same as that of the first embodiment, and the control clocks CKA2, CKB2, CKC2, The phase relationship of CKP2 is also the same as that of the first embodiment. Therefore, the first and second charge pump circuits operate to boost the input voltage and supply it to the output terminal, respectively, in the same manner as the booster circuit for VGH in the first embodiment. In this booster circuit, as shown in FIG. 1 and FIG. 2 , the control clocks of the first and second charge pump circuits are staggered by half a period from each other. Therefore, during the period when the input voltage VA is charged to the extraction capacitance element Cp1 by the first charge pump circuit, the charge stored in the extraction capacitance element Cp2 of the second charge pump circuit is provided to the output terminal; While the electric charge of Cp1 is supplied to the output terminal, the electric charge is charged to the pumping capacitive element Cp2 by the second booster circuit. By alternately repeating these two states and supplying a fixed current to the output terminal, a larger output voltage can be obtained than in the case of using a single charge pump circuit. For example, when the input voltage VA=5V and the sampling clock amplitude is 5Vpp, the output voltage of the first charge pump circuit is 10V, and the output voltage of the second charge pump circuit is 15V.

Next, the operation of this booster circuit will be described in detail based on FIG. 12 . Here, the case where the input voltage VA=5V and the amplitudes of the control clocks CKA1 , CKB1 , CKC1 , CKP1 , CKB2 , CKC2 , CKP2 are 5Vpp will be specifically described as an example. In FIG. 11, the part (300) surrounded by a dotted line is the same as the circuit described in Embodiment 1. In addition, the timing of its control clock is also the same as that of Embodiment 1. Therefore, like Embodiment 1, the boost input The voltage VA=5V, and the voltage of 10V is output to carry out such an operation. Since the operation of the portion (300) surrounded by a dotted line has already been described in detail in Embodiment 1, description is omitted here. The work on other parts is as follows. If the circuit (300) enclosed by the dotted line outputs a voltage of 10V, the node NP2 is 10V, and if CKP2 is high at t5, the node NP2 is boosted to 15V. At this time, node NC2 is charged to about 15-Vth by TR12. If CKC is high at t6, NC2 is temporarily charged to 20V. If CKB2 is high at t7, NB2 (the gate voltage of TR11) is boosted to 20-Vth, and TR11 is turned on. As a result, the charge of Cp is supplied to the output terminal through TR11, and a voltage of 15V is applied to the output terminal. That is to say, the newly added circuit outside the dotted line performs the work of boosting the 10V output from the circuit (300) surrounded by the dotted line to 15V. Therefore, by repeating a series of operations, by combining the circuit ( 300 ) surrounded by a dotted line, the input voltage of 5V can be boosted to 15V as a whole of the circuit.

In the circuit shown in Fig. 11, by boosting the voltage twice, a sufficiently large gate voltage can be supplied to the gates of the charge transfer switches TR6 and TR11, the on-resistance of the switches can be reduced, and the influence of the Vth shift can be suppressed to a small level. Good power supply circuit characteristics can be realized.

Fig. 13 shows a circuit for low voltage VGL related to the third embodiment. The VGL circuit related to the third embodiment is the same as the VGL circuit in the first embodiment, and the input-output relationship of the VGH circuit is reversed. Like the booster circuit for VGH, connecting two charge pump circuits in series and staggering their operation by half a cycle can obtain a lower VGL voltage than when using a single charge pump circuit. For example, when the input voltage VB=3V and the extracted clock amplitude is 5Vpp, the output voltage of the second charge pump circuit is -2V, and the output voltage of the first charge pump circuit is -7V.

The timing diagram of the VGL circuit is shown in Figure 14. As shown in FIG. 14, the phase relationship of the control clocks CKA1, CKB1, CKC1, and CKP1 of the first charge pump circuit is the same as that of the first embodiment. In addition, the control clocks CKA2, CKB2, and CKC2 of the second charge pump circuit The phase relation of CKP2 and CKP2 is also the same as that of the first embodiment. Therefore, the first and second charge pump circuits operate in the same manner as the booster circuit for VGL in the first embodiment to convert the input voltages to low levels and supply them to the output terminals, respectively. In the circuit for VGL, as shown in FIG. 14, the control clocks of the first and second charge pump circuits are shifted by a half cycle from each other. Therefore, while the current flows from the output VA to the extraction capacitance element Cp1 by the first charge pump circuit, the charge stored in the extraction capacitance element Cp2 of the second charge pump circuit is supplied to the input terminal. While the charge of the element Cp1 is supplied to the input terminal, the charge is charged to the pumping capacitive element Cp2 by the second booster circuit. By repeating these two states alternately, the fixed charge is transferred from the output VA to the input VB, and a lower output voltage can be obtained than when a single charge pump circuit is used. For example, when the input voltage VA=5V and the extracted clock amplitude is 5Vpp, the output voltage of the second charge pump circuit is -2V, and the output voltage of the first charge pump circuit is -7V.

Next, the operation of the circuit for VGL will be described in detail based on FIG. 14 . Here, the case where the input voltage VA=5V and the amplitudes of the control clocks CKA1 , CKB1 , CKC1 , CKP1 , CKB2 , CKC2 , CKP2 are 5Vpp will be specifically described as an example. First, given that the extraction clock CKP2 is in a high state, the input voltage VB=3V, at time t7 if CKB2 is high, TR11 is turned on, and the node NP2 is discharged to the input voltage VB=3V (the voltage of Cp2 is 3V-5V= -2V). Then, at t8 if CKB2 and CKC2 are low, TR11 is turned off. At this time, CKP2 is also low, and NP2 is -2V. Therefore, the newly added circuit outside the dotted line performs the work of converting the input voltage VB=3V into -2V and supplying it to the circuit surrounded by the dotted line (300). Regarding the circuit (300) in the dotted line, as described in Embodiment 1, such work is performed: the input voltage is dropped by 5V, and provided to the output terminal. At this time, the -2V voltage output by the second charge pump circuit is converted into -7V output. As for the internal operation of the circuit (300) inside the dotted line, since it has been described in detail in Embodiment 1, the explanation is omitted here. Therefore, by repeating a series of operations and combining with the circuit (300) surrounded by the dotted line, the circuit as a whole can convert an input voltage of VB=3V into an output of -7V.

In the circuit shown in Fig. 13, a sufficiently large gate voltage can be supplied to the charge transfer switches TR6 and TR11 by boosting the voltage twice, so the on-resistance of the switches can be reduced, and the influence of the Vth shift can be suppressed to a small level, which can realize good characteristics of the power circuit.

Based on the same idea, it goes without saying that a higher high voltage VGH or a lower low voltage VGL can be obtained by connecting three or more stages of charge pump circuits in series and staggering them by half a cycle.

Furthermore, the overall configuration of the display device using the booster circuit according to the third embodiment is the same as that of the first embodiment, and description thereof will be omitted.

The voltage conversion circuit of the present invention can be used in a boost circuit that generates a power supply voltage for driving a display device.

The display device of the present invention can be used for a display device mounted on a mobile phone.

Claims (13)

1. A voltage conversion circuit, which converts and outputs the input voltage, is characterized in that: including first to eighth transistors and first to fifth capacitive elements, connecting the drain and the gate of the first transistor to the voltage input terminal, connecting the source of the first transistor to the first node, connecting the drain of the second transistor to the voltage input terminal, connecting the gate of the second transistor to the second node, connecting the source of the second transistor to the first node, connecting the drain of the third transistor to the voltage input terminal, connecting the gate of the third transistor to the first node, and connecting the source of the third transistor to the second node, connecting the drain of the fourth transistor to the second node, connecting the gate of the fourth transistor to the third node, and connecting the source of the fourth transistor to the fourth node, connecting the drain of the fifth transistor to the second node, connecting the gate of the fifth transistor to the voltage output terminal, and connecting the source of the fifth transistor to the fourth node, connecting the drain of the sixth transistor to the second node, connecting the gate of the sixth transistor to the fourth node, and connecting the source of the sixth transistor to the voltage output terminal, connecting the drain and the gate of the seventh transistor to the second node, and connecting the source of the seventh transistor to the third node, connecting the drain of the eighth transistor to the second node, connecting the gate of the eighth transistor to the fourth node, and connecting the source of the eighth transistor to the third node, connecting the first capacitive element between the first control signal input terminal and the first node, connecting the second capacitive element between the second control signal input terminal and the fourth node, connecting the third capacitive element between the third control signal input terminal and the third node, connecting the fourth capacitive element between the fourth control signal input terminal and the second node, connecting the fifth capacitor to at least one of the voltage output terminal and ground or between the voltage input terminal and ground, First to fourth control signals having different rising edge timings are input to the first to fourth control signal input terminals. 2. The voltage conversion circuit according to claim 1, wherein the first to fourth control signals are pulse waveforms, and their rising and falling timings are respectively the rising timing (tA1) of the first control signal, the first The falling timing of the control signal (tA2), the rising timing of the second control signal (tB1), the falling timing of the second control signal (tB2), the rising timing of the third control signal (tC1), the falling timing of the third control signal ( tC2), the rising timing of the fourth control signal (tP1), and the falling timing of the fourth control signal (tP2), these timings are the rising timing of the fourth control signal (tP1), the rising timing of the third control signal Timing (tC1), rising timing (tB1) of the second control signal, falling timing (tP2) of the fourth control signal=falling timing (tC2) of the third control signal=falling timing (tB2) of the second control signal, A rising timing (tA1) of the first control signal, and a falling timing (tA2) of the first control signal. 3. The voltage conversion circuit according to claim 1, characterized in that: two or more of the above-mentioned voltage conversion circuits are connected in parallel, and the above-mentioned first control signal of the first above-mentioned voltage conversion circuit is connected to the second above-mentioned voltage conversion circuit The phase of the above-mentioned first control signal of the above-mentioned voltage conversion circuit is staggered by half a cycle, the phase of the above-mentioned second control signal of the first above-mentioned voltage conversion circuit and the above-mentioned second control signal of the second above-mentioned voltage conversion circuit are staggered by half a cycle, and the phase of the first above-mentioned voltage conversion circuit The phase of the third control signal of the third control signal and the third control signal of the second voltage conversion circuit is staggered by half a period, and the phase of the fourth control signal of the first voltage conversion circuit is different from that of the fourth control signal of the second voltage conversion circuit. Current is supplied from two or more of the above voltage conversion circuits to the common output terminal with a half cycle shifted. 4 . The voltage converting circuit according to claim 1 , wherein the first to eighth transistors are formed by NMOS single channel. 5. The voltage conversion circuit according to claim 1, characterized in that: the initial voltage is applied to the first capacitive element and the second capacitive element through the first transistor and the fourth transistor, according to the first control signal and The second control signal boosts the voltage applied to the gates of the third transistor and the sixth transistor to switch the third transistor and the sixth transistor, The initial voltage is applied to the third capacitive element through the seventh transistor, and the voltage applied to the gate of the fourth transistor is boosted according to the third control signal, and the voltage applied to the fourth node is boosted. 6. A display device with the voltage conversion circuit according to claim 1, comprising: A display panel having a plurality of pixel electrodes arranged in a matrix; a switching element for providing an image signal to the pixel electrode; an image signal line, providing an image signal to the switching element; A scanning signal line, providing a scanning signal for controlling the switching element; a first drive circuit that outputs the image signal and is formed on the display panel in the same process as the switching element; a second driving circuit, outputting the scanning signal; The voltage converting circuit according to claim 1 is formed in the display panel by the same process as that of the switching element. 7. A display device having the voltage conversion circuit according to claim 1, wherein the voltage generated by the voltage conversion circuit according to claim 1 is used as a driving voltage of the display device. 8. A voltage conversion circuit, which converts the input voltage to output, characterized in that: including first to eighth transistors and first to fifth capacitive elements, connecting the drain and the gate of the first transistor to the voltage input terminal, connecting the source of the first transistor to the first node, connecting the drain of the second transistor to the voltage input terminal, connecting the gate of the second transistor to the second node, connecting the source of the second transistor to the first node, connecting the drain of the third transistor to the voltage input terminal, connecting the gate of the third transistor to the first node, and connecting the source of the third transistor to the second node, connecting the first capacitive element between the first control signal input terminal and the first node, A plurality of circuit blocks are connected in series between the above-mentioned third transistor source and the voltage output terminal, the circuit block Connect the drain of the above-mentioned fourth transistor to the above-mentioned second node, connect the gate of the above-mentioned fourth transistor to the third node, connect the source of the above-mentioned fourth transistor to the fourth node, connect the drain of the above-mentioned fifth transistor to Connect the pole to the second node, connect the gate of the fifth transistor to the output of the circuit block, connect the source of the fifth transistor to the fourth node, connect the drain of the sixth transistor to the The second node connects the gate of the sixth transistor to the fourth node, connects the source of the sixth transistor to the output of the circuit block, and connects the drain and gate of the seventh transistor to the first node. Two nodes, the source of the seventh transistor is connected to the third node, the drain of the eighth transistor is connected to the second node, the gate of the eighth transistor is connected to the fourth node, and the The source of the eighth transistor is connected to the third node, the second capacitive element is connected between the second control signal input terminal and the fourth node, and the third capacitive element is connected between the third control signal input terminal and the fourth node. Between the above-mentioned third node, the above-mentioned fourth capacitive element is connected between the fourth control signal input terminal and the above-mentioned second node, the gate of the above-mentioned seventh transistor is used as the input of the circuit block, and the gate of the above-mentioned fifth transistor is gate as the output of this circuit block, connecting said fifth capacitive element to at least one of between said voltage output terminal and ground or between said voltage input terminal and ground, The first to fourth control signal input terminals are input with first to fourth control signals having different rising edge timings, The input terminal of the first circuit block among the plurality of circuit blocks is connected to the source of the third transistor, an output terminal of a first circuit block among the plurality of circuit blocks is connected to an input terminal of a second circuit block among the plurality of circuit blocks, an output terminal of a second circuit block among the plurality of circuit blocks is connected to an input terminal of a third circuit block among the plurality of circuit blocks, An output terminal of an nth circuit block among the plurality of circuit blocks is connected to an input terminal of an n+1th circuit block among the plurality of circuit blocks. 9. The voltage conversion circuit according to claim 8, characterized in that: the rising timing of the respective second control signals of each circuit block connected in series between the source of the third transistor and the voltage output terminal, the respective second The falling timing of the control signal, the rising timing of the respective third control signal, the falling timing of the respective third control signal, the rising timing of the respective fourth control signal, and the falling timing of the respective fourth control signal are, in order of early and late: The rising timing of the fourth control signal, the rising timing of the third control signal, the rising timing of the second control signal, the falling timing of the fourth control signal=the falling timing of the third control signal=the falling timing of the second control signal. 10. The voltage converting circuit according to claim 8, characterized in that: the phase of the second control signal of the first circuit block and the second control signal of the second circuit block are shifted by half a cycle, and the first circuit The phase of the third control signal of the first circuit block and the third control signal of the second circuit block are shifted by half a period, and the phase of the fourth control signal of the first circuit block and the fourth control signal of the second circuit block are Stagger by half a cycle. 11. The voltage conversion circuit according to claim 8, wherein the first to eighth transistors are formed by using a single NMOS channel. 12. A display device having the voltage conversion circuit according to claim 8, comprising: A display panel having a plurality of pixel electrodes arranged in a matrix; a switching element for providing an image signal to the pixel electrode; an image signal line, providing an image signal to the switching element; A scanning signal line, providing a scanning signal for controlling the switching element; a first drive circuit that outputs the image signal and is formed on the display panel in the same process as the switching element; a second driving circuit, outputting the scanning signal; The voltage converting circuit according to claim 8 is formed in the display panel in the same manner as the switching element. 13. A display device having the voltage conversion circuit according to claim 8, wherein the voltage generated by the voltage conversion circuit according to claim 8 is used as a driving voltage of the display device.

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