CN114822356A - Shift register, grid drive circuit and display device - Google Patents

Abstract

The shifting register comprises a first control module, a first output module, a second control module, a third control module, a fourth control module, a fifth control module, a sixth control module and an energy storage module; the first output module provides a first power signal of the first power signal terminal to the first output signal terminal under the voltage control of the second node, and the second output module provides a second power signal of the second power signal terminal to the first output signal terminal under the voltage control of the first node. The first control module, the second control module, the third control module, the fourth control module, the fifth control module, the sixth control module and the energy storage module are matched with each other to control the potentials of the first node, the second node and the third node. The shift register can output a pulse signal with a waveform meeting requirements.

Description

Shift register, gate driving circuit and display device

technical field

This document relates to, but is not limited to, the field of display technology, and in particular, relates to a shift register, a gate driving circuit and a display device.

Background technique

The Gate Driver on Array (GOA) technology of the array substrate integrates the thin film transistor (ThinFilm Transistor, TFT) gate switch circuit on the array substrate of the display panel to drive the display panel, thereby eliminating the need for integrated circuits The bonding area of the Integrated Circuit (IC) and the wiring space of the fan-out area, so as to realize a narrow border.

Oxide thin film transistors have received more and more attention due to their transparent materials, relatively simple fabrication process and low process temperature. For oxide thin film transistors, a new GOA circuit needs to be designed to adapt to the low carrier mobility of oxide thin film transistors.

SUMMARY OF THE INVENTION

In a first aspect, the present disclosure provides a shift register, comprising: a first control module, a first output module, a second output module, a second control module, a third control module, a fourth control module, and a fifth control module , the sixth control module and the energy storage module;

The first control module is connected to the first power supply signal terminal, the first input signal terminal and the second node, and is configured to provide the first power supply signal of the first power supply signal terminal to the first power supply signal terminal under the control of the first input signal of the first input signal terminal. second node;

The first output module is connected to the second node, the first clock signal terminal and the first output signal terminal, and is configured to provide the first clock signal of the first clock signal terminal to the first output signal terminal under the voltage control of the second node ;

The second output module is connected to the first node, the second power signal terminal and the first output signal terminal, and is configured to provide the second power signal from the second power signal terminal to the first output signal terminal under the voltage control of the first node ;

The second control module is connected to the second power signal terminal, the second input signal terminal, the first clock signal terminal and the third node, and is configured to control the second power signal terminal's first power signal terminal under the control of the second input signal of the second input signal terminal The second power signal is provided to the third node, and the second power signal of the second power signal terminal is provided to the third node under the control of the first clock signal of the first clock signal terminal;

a third control module, connected to the third node, the second clock signal terminal and the first node, and configured to provide the second clock signal from the second clock signal terminal to the first node under the voltage control of the third node;

a fourth control module, connected to the third node, the second power signal terminal and the second node, and configured to provide the second power signal from the second power signal terminal to the second node under the voltage control of the third node;

a fifth control module, connected to the first node, the second power signal terminal and the second node, and configured to provide the second power signal from the second power signal terminal to the second node under the voltage control of the first node;

a sixth control module, connected to the second node, the second power signal terminal and the first node, and configured to provide the second power signal from the second power signal terminal to the first node under the voltage control of the second node;

The energy storage module includes a first capacitor, and two ends of the first capacitor are respectively connected to the third node and the second clock signal terminal.

In a second aspect, the present disclosure provides a gate driving circuit, comprising N cascaded shift registers SR(i); the first output signal terminal of the kth shift register SR(k) is connected to the k+1th The first input signal terminals of the shift registers SR(k+1) are connected; 1≤k≤N-1, N>1; at least one shift register SR(i) of the N shift registers adopts the above shift register ; 1≤i≤N.

In a third aspect, the present disclosure provides a display device including the above gate driving circuit.

Embodiments of the present disclosure provide a shift register, a gate driving circuit, and a display device. The shift register includes a first output module, a second output module, a first control module, a second control module, a third control module, a third control module, and a first output module. Four control modules, fifth control module, sixth control module and energy storage module; the first output module provides the first clock signal of the first clock signal terminal to the first output signal terminal under the voltage control of the second node, the second The output module provides the second power signal of the second power signal terminal to the first output signal terminal under the voltage control of the first node, the third control module and the sixth control module control the voltage of the first node, the first control module, the third control module and the sixth control module control the voltage of the first node. The fourth control module and the fifth control module control the voltage of the second node, and the second control module controls the voltage of the third node. Through the cooperation of the six control modules and the energy storage module, the node potential can jump in time, so that the output waveform meets the requirements pulse signal.

Description of drawings

The accompanying drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not limit the technical solutions of the present disclosure.

FIG. 1 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of an equivalent circuit of a shift register provided by an embodiment of the present disclosure;

3 is a schematic diagram of an equivalent circuit (including a second capacitor and a third capacitor) of another shift register provided by an embodiment of the present disclosure;

4 is a schematic diagram of an equivalent circuit (including a tenth transistor) of another shift register provided by an embodiment of the present disclosure;

5 is a schematic diagram of an equivalent circuit (including a second output signal terminal) of another shift register provided by an embodiment of the present disclosure;

FIG. 6 is a signal timing diagram of a shift register according to an embodiment of the present disclosure;

7 is a signal timing diagram of another shift register provided by an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a cascaded structure of a gate driving circuit according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of a cascaded structure of a gate driving circuit according to an embodiment of the present disclosure (the first input signal and the second input signal are the same);

FIG. 10 is a schematic diagram of a cascade structure of a gate driving circuit according to an embodiment of the present disclosure (the first input signal and the second input signal are different).

Detailed ways

In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that embodiments may be implemented in many different forms. Those skilled in the art can easily understand the fact that the manner and content can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following embodiments. The embodiments of the present disclosure and the features of the embodiments may be arbitrarily combined with each other without conflict.

In the drawings, the size of each constituent element, the thickness of a layer, or a region are sometimes exaggerated for clarity. Therefore, one form of the present disclosure is not necessarily limited to this size, and the shapes and sizes of the various components in the drawings do not reflect true scale. In addition, the drawings schematically show ideal examples, and one form of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

In this specification, ordinal numbers such as "first", "second", and "third" are provided to avoid confusion of constituent elements, and are not intended to be limited in quantity.

In this specification, unless otherwise expressly specified and limited, the terms "installed", "connected" and "connected" should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood in specific situations.

In this specification, a transistor refers to an element including at least three terminals of a gate, a drain, and a source. The source and drain of a transistor are symmetrical, and the functions of "source" and "drain" may be interchanged when using transistors with opposite polarities or when the direction of current changes during circuit operation. In the embodiments of the present disclosure, one of the source electrode and the drain electrode is referred to as the first electrode, the other of the source electrode and the drain electrode is referred to as the second electrode, and the gate electrode is referred to as the control electrode.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements. Examples of "elements having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

In the following example, the case where the driving transistor is an N-type thin film transistor is described, and other transistors are of the same or different type as the driving transistor according to the circuit design. Similarly, in other embodiments, the drive transistors may also be shown as P-type thin film transistors. Those skilled in the art can understand that the technology of the present disclosure can also be implemented by changing the types of other transistors accordingly and inverting the respective drive signals and level signals (and/or making other additional adaptive modifications). Program.

An embodiment of the present disclosure provides a shift register. As shown in FIG. 1 , the shift register provided by the embodiment of the present disclosure includes: a first control module 10 , a first output module 20 , a second output module 30 , and a second a control module 40 , a third control module 50 , a fourth control module 60 , a fifth control module 70 , a sixth control module 80 and an energy storage module 90 ;

The first control module is connected to the first power signal terminal VGH, the first input signal terminal IN1 and the second node N2, and is configured to control the first power supply of the first power signal terminal under the control of the first input signal of the first input signal terminal. the signal is provided to the second node;

The first output module is connected to the second node N2, the first clock signal terminal CK1 and the first output signal terminal OUT1, and is configured to provide the first clock signal of the first clock signal terminal to the first output signal terminal under the voltage control of the second node. output signal terminal;

The second output module is connected to the first node N1, the second power signal terminal VGL and the first output signal terminal OUT1, and is configured to provide the second power signal from the second power signal terminal to the first node under the voltage control of the first node. output signal terminal;

The second control module is connected to the second power signal terminal VGL, the second input signal terminal IN2, the first clock signal terminal CK1 and the third node N3, and is configured to control the second input signal terminal under the control of the second input signal from the second input signal terminal. The second power signal of the power signal terminal is provided to the third node, and the second power signal of the second power signal terminal is provided to the third node under the control of the first clock signal of the first clock signal terminal;

a third control module, connected to the third node N3, the second clock signal terminal CK2 and the first node N1, and configured to provide the second clock signal of the second clock signal terminal to the first node under the voltage control of the third node;

a fourth control module, connected to the third node N3, the second power signal terminal VGL and the second node N2, and configured to provide the second power signal from the second power signal terminal to the second node under the voltage control of the third node;

a fifth control module, connected to the first node N1, the second power signal terminal VGL and the second node N2, and configured to provide the second power signal from the second power signal terminal to the second node under the voltage control of the first node;

a sixth control module, connected to the second node N2, the second power signal terminal VGL and the first node N1, and configured to provide the second power signal from the second power signal terminal to the first node under the voltage control of the second node;

The energy storage module includes a first capacitor C1, and two ends of the first capacitor are respectively connected to the third node and the second clock signal terminal CK2.

The shift register provided by the above embodiment includes a first output module, a second output module, a first control module, a second control module, a third control module, a fourth control module, a fifth control module, a sixth control module and a storage module. The first output module provides the first clock signal of the first clock signal terminal to the first output signal terminal under the voltage control of the second node, and the second output module provides the second power signal under the voltage control of the first node. The second power signal of the terminal is provided to the first output signal terminal, the third control module and the sixth control module control the voltage of the first node, the first control module, the fourth control module and the fifth control module control the voltage of the second node, The second control module controls the voltage of the third node, and the cooperation of the six control modules and the energy storage module can make the node potential jump in time, shorten the time of the rising and falling edges of the output pulse signal, and make the output waveform meet the requirements.

Figure 2 provides an equivalent circuit diagram of a shift register.

As shown in FIG. 2 , in some exemplary embodiments, the first control module includes a first transistor T1, the control electrode of the first transistor is connected to the first input signal terminal, and the first transistor T1 is connected to the first input signal terminal. The pole is connected to the first power signal terminal, and the second pole of the first transistor is connected to the second node.

As shown in FIG. 2, in some exemplary embodiments, the first output module includes a second transistor T2, the control electrode of the second transistor is connected to the second node, and the first electrode of the second transistor is connected to the second node The first clock signal terminal, the second pole of the second transistor is connected to the first output signal terminal.

As shown in FIG. 2 , in some exemplary embodiments, the second output module includes a third transistor T3, the control electrode of the third transistor is connected to the first node, and the first electrode of the third transistor is connected to the first node The second power signal terminal, the second pole of the third transistor is connected to the first output signal terminal.

As shown in FIG. 2 , in some exemplary embodiments, the second control module includes a fourth transistor and a fifth transistor, the control electrode of the fourth transistor is connected to the first clock signal terminal, and the fourth transistor The first pole of the fourth transistor is connected to the second power supply signal terminal, the second pole of the fourth transistor is connected to the third node, the control pole of the fifth transistor is connected to the second input signal terminal, and the first pole of the fifth transistor is connected to the third node. The second power supply signal terminal, the second pole of the fifth transistor is connected to the third node.

As shown in FIG. 2 , in some exemplary embodiments, the third control module includes a sixth transistor T6, the control electrode of the sixth transistor is connected to the third node, and the first electrode of the sixth transistor is connected to the third node For the second clock signal terminal, the second pole of the sixth transistor is connected to the first node.

As shown in FIG. 2 , in some exemplary embodiments, the fourth control module includes a seventh transistor T7, the control electrode of the seventh transistor is connected to the third node, and the first electrode of the seventh transistor is connected to the third node The second power supply signal terminal, the second pole of the seventh transistor is connected to the second node.

As shown in FIG. 2 , in some exemplary embodiments, the fifth control module includes an eighth transistor T8, a control electrode of the eighth transistor is connected to the first node, and a first electrode of the eighth transistor is connected to the first node The second power supply signal terminal, the second pole of the eighth transistor is connected to the second node.

As shown in FIG. 2 , in some exemplary embodiments, the sixth control module includes a ninth transistor T9, a control electrode of the ninth transistor is connected to the second node, and a first electrode of the ninth transistor is connected to the second node The second power supply signal terminal, the second pole of the ninth transistor is connected to the first node.

Figure 3 provides an equivalent circuit diagram of another shift register.

As shown in FIG. 3, in some exemplary embodiments, the first output module further includes a second capacitor C2, one end of the second capacitor is connected to the control electrode of the second transistor, and the second capacitor C2 The other end is connected to the second pole of the second transistor. The second capacitor is connected across the gate electrode and the second electrode of the second transistor, and can stabilize the potential of the gate electrode of the second transistor.

As shown in FIG. 3, in some exemplary embodiments, the second output module further includes a third capacitor C3, one end of the third capacitor is connected to the control electrode of the third transistor, and the third capacitor C3 The other end is connected to the first pole of the third transistor. The third capacitor is connected across the gate electrode of the third transistor and the first electrode, and can stabilize the potential of the gate electrode of the third transistor.

Figure 4 provides an equivalent circuit diagram of another shift register.

As shown in FIG. 4 , in some exemplary embodiments, the first output module further includes a tenth transistor T10 , the control electrode of the tenth transistor is connected to the first power supply signal terminal, and the first output module of the tenth transistor T10 One electrode is connected to the second node, and the second electrode of the tenth transistor is connected to the control electrode of the second transistor. The tenth transistor is provided between the second node and the gate electrode of the second transistor, and the potential of the gate electrode of the second transistor can be stabilized.

Figure 5 provides an equivalent circuit diagram of another shift register.

As shown in FIG. 5 , in some exemplary embodiments, the second node N2 is further connected to the second output signal terminal OUT2. The second output signal terminal outputs the second output signal.

In some exemplary embodiments, all transistors in the shift register are N-type transistors.

In some exemplary implementations, when all transistors in the shift register are N-type transistors, one working cycle of the shift register includes the following multiple periods: a first period, a second period, a third period period, the fourth period, and the fifth and sixth periods alternately appearing multiple times;

The first power supply signal and the second power supply signal are DC signals, the first power supply signal is a high level signal, the second power supply signal is a low level signal, the first input signal and the second input signal are pulse signals, and the first clock signal and the second clock signal are periodic pulse signals; the first input signal and the second input signal are high-level signals in the first period, and low-level signals in other periods; the first clock signal is in the first period, the third The period and the fifth period are low-level signals, and the second, fourth, and sixth periods are high-level signals; the second clock signal is a high-level signal in the first, third, and fifth periods , is a low level signal in the second period, the fourth period and the sixth period.

In some exemplary implementations, when all transistors in the shift register are N-type transistors, one working cycle of the shift register includes the following multiple periods: a first period, a second period, a third period period, the fourth period, and the fifth and sixth periods alternately appearing multiple times;

The first power supply signal and the second power supply signal are DC signals, the first power supply signal is a high level signal, the second power supply signal is a low level signal, the first input signal and the second input signal are pulse signals, and the first clock signal and the second clock signal are periodic pulse signals; the first input signal is a high-level signal in the first period, and a low-level signal in other periods; the second input signal is a high-level signal in the first period and the second period The signal is a low-level signal in other periods; the first clock signal is a low-level signal in the first, third and fifth periods, and is a high-level signal in the second, fourth and sixth periods ; The second clock signal is a high level signal in the first period, the third period and the fifth period, and is a low level signal in the second period, the fourth period and the sixth period.

In some exemplary embodiments, all transistors in the shift register are oxide thin film transistors. The carrier mobility of the oxide thin film transistor is low. The cooperation of the six control modules and the energy storage module can make the node potential jump in time, shorten the time of the rising and falling edges of the output pulse signal, and make the output waveform meet the Require.

The working process of the shift register will be described below with reference to the signal timing diagram.

Figure 6 provides a signal timing diagram for the shift register. The shift register adopts any one of the structures shown in Figure 2 to Figure 5, all transistors are N-type transistors, the first power signal terminal provides the first power signal, the second power signal terminal provides the second power signal, and the first clock signal The first clock signal terminal provides the first clock signal, the second clock signal terminal provides the second clock signal, the first input signal terminal provides the first input signal, the second input signal terminal provides the second input signal, and the first output signal terminal outputs the first output signal , the second output signal terminal outputs the second output signal (for FIG. 5 ). The first power supply signal and the second power supply signal are DC signals, the first input signal and the second input signal are pulse signals, the first input signal and the second input signal are the same, and the first clock signal and the second clock signal are periodic pulses signal, the first clock signal and the second clock signal are opposite in phase.

For N-type transistors, when the voltage of the transistor gate (control electrode) is higher than the turn-on voltage, the transistor is turned on, and when the voltage of the transistor gate is lower than the turn-on voltage, the transistor is turned off. A high-level signal is a signal higher than the turn-on voltage of the transistor, and a low-level signal is a signal lower than the turn-on voltage of the transistor. The first power signal is a high-level signal, and the second power signal is a low-level signal.

A working cycle of the shift register may include multiple periods: a first period (t1), a second period (t2), a third period (t3), a fourth period (t4) and a fifth period ( t5) and the sixth period (t6).

(1) The first period (t1 period)

The first input signal and the second input signal are high-level signals, the first clock signal is a low-level signal, and the second clock signal is a high-level signal.

The first clock signal is a low level signal, the fourth transistor is turned off, the second input signal is a high level signal, the fifth transistor is turned on, and the second power supply signal is provided to the third node. The second power signal is a low level signal, so the potential of the third node is a low level.

The potential of the third node is at a low level, and the sixth transistor and the seventh transistor are turned off. The second clock signal is a high level signal, and the second clock signal charges the first capacitor.

The first input signal is a high level signal, the first transistor is turned on, and the first power supply signal is provided to the second node. The first power signal is a high level signal, so the potential of the second node is a high level.

The potential of the second node is at a high level, the ninth transistor is turned on, and the second power signal is supplied to the first node. The second power supply signal is a low level signal, so the potential of the first node is a low level.

The potential of the first node is at a low level, and the third transistor and the eighth transistor are turned off. The potential of the second node is at a high level, the second transistor is turned on, and the first clock signal is provided to the first output signal terminal. The first clock signal is a low-level signal, so the first output signal output by the first output signal terminal is a low-level signal. When the second capacitor is connected across the control electrode and the second electrode of the second transistor, the second node charges the second capacitor.

When the second node is further connected to the second output signal terminal, the second output signal output by the second output signal terminal is a high-level signal.

(2) The second period (t2 period)

The first input signal and the second input signal are low-level signals, the first clock signal is a high-level signal, and the second clock signal is a low-level signal.

The second input signal is a low-level signal, the fifth transistor is turned off, the first clock signal is a high-level signal, the fourth transistor is turned on, and the second power supply signal is provided to the third node. The second power signal is a low level signal, so the potential of the third node is a low level.

The potential of the third node is at a low level, and the sixth transistor and the seventh transistor are turned off.

The first input signal is a low-level signal, the first transistor is turned off, the second node maintains the potential of the previous period (t1), and the potential of the previous period is high.

The potential of the second node is at a high level, the ninth transistor is turned on, and the second power signal is supplied to the first node. The second power supply signal is a low level signal, so the potential of the first node is a low level.

The potential of the first node is at a low level, and the third transistor and the eighth transistor are turned off. The potential of the second node is at a high level, the second transistor is turned on, and the first clock signal is provided to the first output signal terminal. The first clock signal is a high-level signal, so the first output signal output by the first output signal terminal jumps from a low-level signal to a high-level signal. Since the second transistor is always in an on state during the second period, it can quickly follow the transition of the first clock signal, thereby shortening the rising edge time of the first output signal.

When the second node is further connected to the second output signal terminal, the second output signal output by the second output signal terminal is a high-level signal.

(3) The third period (t3 period)

The first input signal and the second input signal are high-level signals, the first clock signal is a low-level signal, and the second clock signal is a high-level signal.

The first clock signal is a low level signal, the fourth transistor is turned off, the second input signal is a low level signal, and the fifth transistor is turned off.

The second clock signal jumps from a low level signal to a high level signal, and the third node also jumps from a low level to a high level under the action of the third capacitor. After the third node jumps to a high level, the sixth transistor and the seventh transistor are turned on, the second clock signal is supplied to the first node, and the second power signal is supplied to the second node. The second clock signal is a high level signal, and the potential of the first node jumps from a low level to a high level. The first input signal is a low level signal, and the first transistor is turned off. The second power signal is a low level signal, and the potential of the second node changes from a high level to a low level.

The potential of the second node is at a low level, and the ninth transistor and the second transistor are turned off.

The potential of the first node is at a high level, and the eighth transistor and the third transistor are turned on. The second power supply signal is provided to the second node, the second power supply signal is a low level signal, and the potential of the second node is a low level. The second power signal is provided to the first output signal terminal, the second power signal is a low-level signal, and the first output signal output by the first output signal terminal jumps from a high-level signal to a low-level signal. When the third capacitor is connected across the control electrode and the first electrode of the third transistor, the first node charges the third capacitor.

After the potential of the third node jumps, the potential of the second node and the first node are controlled to jump at the same time, so that the second transistor is turned off and the third transistor is turned on at the same time, and the first output signal jumps from a high level to a low level. level, shortening the time of the falling edge of the first output signal.

When the second node is further connected to the second output signal terminal, the second output signal output by the second output signal terminal is a low level signal.

(4) Fourth period (t4 period)

The first input signal and the second input signal are low-level signals, the first clock signal is a high-level signal, and the second clock signal is a low-level signal.

The second input signal is a low-level signal, the fifth transistor is turned off, the first clock signal is a high-level signal, the fourth transistor is turned on, and the second power supply signal is provided to the third node. The second power signal is a low level signal, so the potential of the third node changes from a high level to a low level.

The potential of the third node is at a low level, and the sixth transistor and the seventh transistor are turned off.

The first input signal is a low level signal, the first transistor is turned off, and the second node maintains the potential of the previous period (t3), and the potential of the previous period is low level.

The potential of the second node is at a low level, and the ninth transistor and the second transistor are turned off.

The sixth transistor and the ninth transistor are turned off, the first node maintains the potential of the previous period (t3), and the potential of the previous period is a high level.

The potential of the first node is at a high level, and the eighth transistor and the third transistor continue to be turned on. The potential of the second node continues to maintain a low level, and the first output signal continues to maintain a low level signal. The third capacitor maintains the high level of the control electrode of the third transistor.

When the second node is further connected to the second output signal terminal, the second output signal output by the second output signal terminal is a low level signal.

After the fourth period, the fifth period and the sixth period alternate for many times until the end of the working cycle.

(5) Fifth period (t5 period)

The first input signal and the second input signal are low-level signals, the first clock signal is a low-level signal, and the second clock signal is a high-level signal.

The first clock signal is a low level signal, the fourth transistor is turned off, the second input signal is a low level signal, and the fifth transistor is turned off.

The second clock signal jumps from a low level signal to a high level signal, and the third node also jumps from a low level to a high level under the action of the third capacitor. After the third node jumps to a high level, the sixth transistor and the seventh transistor are turned on, the second clock signal is supplied to the first node, and the second power signal is supplied to the second node. The second clock signal is a high level signal, and the potential of the first node continues to maintain a high level. The first input signal is a low level signal, and the first transistor is turned off. The second power signal is a low level signal, and the potential of the second node continues to maintain a low level.

The potential of the second node is at a low level, and the ninth transistor and the second transistor are turned off.

The potential of the first node is at a high level, and the eighth transistor and the third transistor continue to be turned on. The potential of the second node continues to maintain a low level, and the first output signal continues to maintain a low level signal. When the third capacitor is connected across the control electrode and the first electrode of the third transistor, the first node charges the third capacitor.

When the second node is further connected to the second output signal terminal, the second output signal output by the second output signal terminal is a low level signal.

(6) The sixth period (t6 period)

The first input signal and the second input signal are low-level signals, the first clock signal is a high-level signal, and the second clock signal is a low-level signal.

The second input signal is a low-level signal, the fifth transistor is turned off, the first clock signal is a high-level signal, the fourth transistor is turned on, and the second power supply signal is provided to the third node. The second power signal is a low level signal, so the potential of the third node changes from a high level to a low level.

The potential of the third node is at a low level, and the sixth transistor and the seventh transistor are turned off.

The first input signal is a low level signal, the first transistor is turned off, the second node maintains the potential of the previous period (t5), and the potential of the previous period is low level.

The potential of the second node is at a low level, and the ninth transistor and the second transistor are turned off.

The sixth transistor and the ninth transistor are turned off, the first node maintains the potential of the previous period (t5), and the potential of the previous period is a high level.

The potential of the first node is at a high level, and the eighth transistor and the third transistor continue to be turned on. The potential of the second node continues to maintain a low level, and the first output signal continues to maintain a low level signal. The third capacitor maintains the high level of the control electrode of the third transistor.

When the second node is further connected to the second output signal terminal, the second output signal output by the second output signal terminal is a low level signal.

Figure 7 provides another signal timing diagram for the shift register. The shift register adopts any one of the structures shown in Figure 2 to Figure 5, all transistors are N-type transistors, the first power signal terminal provides the first power signal, the second power signal terminal provides the second power signal, and the first clock signal The first clock signal terminal provides the first clock signal, the second clock signal terminal provides the second clock signal, the first input signal terminal provides the first input signal, the second input signal terminal provides the second input signal, and the first output signal terminal outputs the first output signal , the second output signal terminal outputs the second output signal (for FIG. 5 ). The first power supply signal and the second power supply signal are DC signals, the first input signal and the second input signal are pulse signals, the first input signal and the second input signal are different, and the first clock signal and the second clock signal are periodic pulses signal, the first clock signal and the second clock signal are opposite in phase.

A working cycle of the shift register may include multiple periods: a first period (t1), a second period (t2), a third period (t3), a fourth period (t4), and a fifth period ( t5) and the sixth period (t6).

The waveforms of the first input signal in FIG. 6 and the first input signal in FIG. 7 are the same, and the waveforms of the second input signal in FIG. 6 and the second input signal in FIG. 7 are different. The difference is that the second input signal in FIG. The period is a low level, and the second input signal of FIG. 7 is a high level in the second period.

In the second period, according to FIG. 7, it can be seen that the fifth transistor is turned on, and according to FIG. 6, it can be seen that the fifth transistor is turned off. However, no matter whether the fifth transistor is turned on or off, since the first clock signal is at a high level, the fourth transistor is turned on, so the second power signal is always supplied to the third node, so that the potential of the third node becomes a low level.

Therefore, although the second input signals in FIG. 7 and FIG. 6 are different, all the nodes of the shift register (the first node, the second node, the third node) have the same potential change in one working cycle, and the first output The waveforms of the signal and the second output signal are also identical.

As shown in FIG. 8 , an embodiment of the present disclosure further provides a gate driving circuit, including N cascaded shift registers SR(i); a first output signal terminal of the kth shift register SR(k) Connect to the first input signal terminal of the k+1th shift register SR(k+1); 1≤k≤N-1, N>1; at least one shift register SR(i) in the N shift registers The shift register in the above embodiment is adopted; 1≤i≤N.

As shown in FIG. 9 , in some exemplary embodiments, the first output signal terminal of the kth shift register SR(k) is also connected with the second output signal terminal of the k+1th shift register SR(k+1) Input signal terminal connection. In this case, the signals input to the first input signal terminal and the second input signal terminal of the shift register are the same.

As shown in FIG. 10 , in some exemplary embodiments, the gate driving circuit further includes N cascaded other shift registers R(i), the k+1th shift register SR(k+1 ) of the second input signal terminal is connected to the output signal terminal GOUT of the kth other shift register R(k); 1≤k≤N-1, N>1; 1≤i≤N; the kth other shift register The output signal output from the output signal terminal of R(k) satisfies the requirement of the second input signal of the k+1th shift register SR(k+1). In this case, the signals input to the first input signal terminal and the second input signal terminal of the shift register are different.

The above-mentioned gate driving circuit can be connected to a pixel driving circuit of a display panel, and is used to provide various control signals, such as a row scanning signal, a reset signal, and the like, to the pixel driving circuit.

The display panel includes: an organic light-emitting diode (Organic Light-Emitting Diode, OLED for short) display panel.

Embodiments of the present disclosure also provide a display device including the above gate driving circuit.

The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator. Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be regarded as a limitation of the present invention.

Although the embodiments disclosed in the present application are as above, the described contents are only the embodiments adopted to facilitate the understanding of the present application, and are not intended to limit the present invention. Any person skilled in the art to which the present invention belongs, without departing from the spirit and scope disclosed by the present invention, can make any modifications and changes in the form and details of the implementation, but the scope of the patent protection of the present invention still needs to be The scope defined by the appended claims shall prevail.

Claims (13)

1. A shift register, comprising: a first control module, a first output module, a second output module, a second control module, a third control module, a fourth control module, a fifth control module, a sixth control module and energy storage module; The first control module is connected to the first power supply signal terminal, the first input signal terminal and the second node, and is configured to provide the first power supply signal of the first power supply signal terminal to the first power supply signal terminal under the control of the first input signal of the first input signal terminal. second node; The first output module is connected to the second node, the first clock signal terminal and the first output signal terminal, and is configured to provide the first clock signal of the first clock signal terminal to the first output signal terminal under the voltage control of the second node ; The second output module is connected to the first node, the second power signal terminal and the first output signal terminal, and is configured to provide the second power signal from the second power signal terminal to the first output signal terminal under the voltage control of the first node ; The second control module is connected to the second power signal terminal, the second input signal terminal, the first clock signal terminal and the third node, and is configured to control the second power signal terminal's first power signal terminal under the control of the second input signal of the second input signal terminal The second power signal is provided to the third node, and the second power signal of the second power signal terminal is provided to the third node under the control of the first clock signal of the first clock signal terminal; a third control module, connected to the third node, the second clock signal terminal and the first node, and configured to provide the second clock signal from the second clock signal terminal to the first node under the voltage control of the third node; a fourth control module, connected to the third node, the second power signal terminal and the second node, and configured to provide the second power signal from the second power signal terminal to the second node under the voltage control of the third node; a fifth control module, connected to the first node, the second power signal terminal and the second node, and configured to provide the second power signal from the second power signal terminal to the second node under the voltage control of the first node; a sixth control module, connected to the second node, the second power signal terminal and the first node, and configured to provide the second power signal from the second power signal terminal to the first node under the voltage control of the second node; The energy storage module includes a first capacitor, and two ends of the first capacitor are respectively connected to the third node and the second clock signal terminal. 2. shift register according to claim 1, is characterized in that: The first output module includes a second transistor, the control electrode of the second transistor is connected to the second node, the first electrode of the second transistor is connected to the first clock signal terminal, and the second electrode of the second transistor is connected to the second node the first output signal terminal; The second output module includes a third transistor, the control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second power supply signal terminal, and the second electrode of the third transistor is connected to the first node the first output signal terminal. 3. shift register according to claim 1, is characterized in that: The first control module includes a first transistor, the control pole of the first transistor is connected to the first input signal terminal, the first pole of the first transistor is connected to the first power supply signal terminal, and the second pole of the first transistor is connected to the first input signal terminal. pole connected to the second node; The fourth control module includes a seventh transistor, the control pole of the seventh transistor is connected to the third node, the first pole of the seventh transistor is connected to the second power signal terminal, and the second pole of the seventh transistor is connected second node; The fifth control module includes an eighth transistor, the control pole of the eighth transistor is connected to the first node, the first pole of the eighth transistor is connected to the second power supply signal terminal, and the second pole of the eighth transistor is connected second node. 4. shift register according to claim 1, is characterized in that: The third control module includes a sixth transistor, the control electrode of the sixth transistor is connected to the third node, the first electrode of the sixth transistor is connected to the second clock signal terminal, and the second electrode of the sixth transistor is connected to the second clock signal terminal the first node; The sixth control module includes a ninth transistor, the control pole of the ninth transistor is connected to the second node, the first pole of the ninth transistor is connected to the second power supply signal terminal, and the second pole of the ninth transistor is connected to the second node first node. 5. shift register according to claim 1, is characterized in that: The second control module includes a fourth transistor and a fifth transistor, the control pole of the fourth transistor is connected to the first clock signal terminal, the first pole of the fourth transistor is connected to the second power signal terminal, and the fourth transistor The second pole of the transistor is connected to the third node, the control pole of the fifth transistor is connected to the second input signal terminal, the first pole of the fifth transistor is connected to the second power supply signal terminal, and the second pole of the fifth transistor Connect the third node. 6. The shift register according to claim 2, wherein: The first output module further includes a second capacitor, one end of the second capacitor is connected to the control electrode of the second transistor, and the other end of the second capacitor is connected to the second electrode of the second transistor; The second output module further includes a third capacitor, one end of the third capacitor is connected to the control electrode of the third transistor, and the other end of the third capacitor is connected to the first electrode of the third transistor. 7. The shift register according to claim 2, wherein: The first output module further includes a tenth transistor, the control electrode of the tenth transistor is connected to the first power signal terminal, the first electrode of the tenth transistor is connected to the second node, and the second electrode of the tenth transistor is connected to the second node. Connect the gate of the second transistor. 8. The shift register according to claim 1, wherein: The second node is also connected to a second output signal terminal, and the second output signal terminal outputs a second output signal. 9. The shift register according to any one of claims 2-8, wherein: All transistors included in the shift register are oxide thin film transistors. 10. The shift register according to any one of claims 2-8, wherein: When all the transistors in the shift register are N-type transistors, one working cycle of the shift register includes the following multiple periods: a first period, a second period, a third period, a fourth period, and multiple alternating periods the fifth and sixth periods that appear; The first power supply signal and the second power supply signal are DC signals, the first power supply signal is a high level signal, the second power supply signal is a low level signal, the first input signal and the second input signal are pulse signals, and the first clock signal and the second clock signal are periodic pulse signals; the first input signal and the second input signal are high-level signals in the first period, and low-level signals in other periods; the first clock signal is in the first period, the third The period and the fifth period are low-level signals, and the second, fourth, and sixth periods are high-level signals; the second clock signal is a high-level signal in the first, third, and fifth periods , is a low level signal in the second period, the fourth period and the sixth period. 11. A gate drive circuit, comprising: comprising N cascaded shift registers SR(i); a first output signal terminal of the kth shift register SR(k) and the k+1th shift register The first input signal terminal of SR(k+1) is connected; 1≤k≤N-1, N>1; at least one shift register SR(i) in the N shift registers adopts any of the above claims 1-10. The shift register of a term; 1≤i≤N. 12. The gate drive circuit according to claim 11, wherein: The first output signal terminal of the kth shift register SR(k) is also connected to the second input signal terminal of the k+1th shift register SR(k+1). 13. A display device comprising: the gate driving circuit of claim 11 or 12.

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