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CN101106114A - Chip structure and forming method thereof - Google Patents

Chip structure and forming method thereof Download PDF

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Publication number
CN101106114A
CN101106114A CNA2006100902951A CN200610090295A CN101106114A CN 101106114 A CN101106114 A CN 101106114A CN A2006100902951 A CNA2006100902951 A CN A2006100902951A CN 200610090295 A CN200610090295 A CN 200610090295A CN 101106114 A CN101106114 A CN 101106114A
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Prior art keywords
protective layer
layer
chip structure
opening
weld pad
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CNA2006100902951A
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Chinese (zh)
Inventor
谢爵安
戴豊成
吴世英
陈世光
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CNA2006100902951A priority Critical patent/CN101106114A/en
Publication of CN101106114A publication Critical patent/CN101106114A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a chip structure and a forming method thereof. The chip structure comprises a substrate, a welding pad, a first protective layer, a second protective layer and a conductive bump. The bonding pad is formed on the substrate. The first protection layer is formed on the substrate and exposes the bonding pad. The second protective layer is formed on the first protective layer and has a protective layer opening, and the protective layer opening is located above the bonding pad. The conductive bump is formed on the bonding pad, and part of the conductive bump is filled in the opening of the protective layer. The width of the bottom of the opening of the protective layer is larger than that of the top of the opening of the protective layer, so that the second protective layer clamps the conductive bump.

Description

芯片结构及其形成方法 Chip structure and method of forming the same

技术领域technical field

本发明涉及一种芯片结构及其形成方法，特别是一种可抗应力的芯片结构及其形成方法。The invention relates to a chip structure and its forming method, in particular to a stress-resistant chip structure and its forming method.

背景技术Background technique

请分别参考图1A至图1G，图1A至图1G表示传统形成芯片结构的示意图。形成芯片结构需经过以下流程。首先如图1A所示，在基底101上形成第一保护层103，并露出一焊垫105。接着，在第一保护层103上形成一第二保护层107，并利用曝光显影的方式在109上形成一保护层开口。接着，如图1C所示，在第一保护层103上沉积凸块下金属层111(Under Bump Metallurgylayer，UBM)，并进行凸块下金属层111的布图工艺。如图1D所示，在凸块下金属层111上更形成一第一光阻层113。然后，如图1E所示，蚀刻凸块下金属层111，并移除第一光阻层113。再来请参考图1F，在第二保护层107上形成一第二光阻层118，并在保护层开口109中填充导电材料119(例如锡膏)。最后，如图1G所示，回焊(Reflow)导电材料119以形成导电凸块123并去除第二光阻层118，从而形成芯片结构100。Please refer to FIG. 1A to FIG. 1G , respectively. FIG. 1A to FIG. 1G are schematic diagrams of conventionally formed chip structures. Forming the chip structure requires the following processes. First, as shown in FIG. 1A , a first passivation layer 103 is formed on a substrate 101 to expose a pad 105 . Next, a second protection layer 107 is formed on the first protection layer 103 , and an opening in the protection layer is formed on 109 by exposure and development. Next, as shown in FIG. 1C , an Under Bump Metallurgy layer 111 (Under Bump Metallurgy layer, UBM) is deposited on the first protection layer 103, and a patterning process of the UBM layer 111 is performed. As shown in FIG. 1D , a first photoresist layer 113 is further formed on the UBM layer 111 . Then, as shown in FIG. 1E , the UBM layer 111 is etched, and the first photoresist layer 113 is removed. Referring again to FIG. 1F , a second photoresist layer 118 is formed on the second passivation layer 107 , and a conductive material 119 (such as solder paste) is filled in the passivation layer opening 109 . Finally, as shown in FIG. 1G , the conductive material 119 is reflowed to form conductive bumps 123 and the second photoresist layer 118 is removed to form the chip structure 100 .

当完成芯片结构100后，必须对芯片结构100进行可靠度的测试(Reliability test)。测试项目例如，温度、压力及机械性质的变化，而且必须周期且反复的进行测试。然而，目前测试的结果中常会出现在芯片结构100中，导电凸块123和凸块下金属层111，或是凸块下金属层111与焊垫105之间常常会有脱离的现象。追究原因，其实是因为导电凸块123、凸块下金属层111以及焊垫105的膨胀系数不同所致。当三者膨胀系数不同时，容易产生应力来分离导电凸块123、凸块下金属层111及焊垫105。也就是说，许多的传统芯片结构100中，导电凸块123、凸块下金属层111及焊垫105间，彼此的黏着力不足以抵挡可靠度测试中温度、压力及机械性质变化所产生的分离应力。也因此降低了产品的可靠度及竞争力。After the chip structure 100 is completed, a reliability test (Reliability test) must be performed on the chip structure 100 . Test items such as temperature, pressure and changes in mechanical properties must be tested periodically and repeatedly. However, current test results often show that in the chip structure 100 , the conductive bump 123 and the UBM layer 111 , or the UBM layer 111 and the bonding pad 105 often have detachment. The reason is that the expansion coefficients of the conductive bump 123 , the UBM layer 111 and the pad 105 are different. When the expansion coefficients of the three are different, stress is easily generated to separate the conductive bump 123 , the UBM layer 111 and the pad 105 . That is to say, in many conventional chip structures 100, the mutual adhesion between the conductive bump 123, the UBM layer 111 and the bonding pad 105 is not enough to withstand the temperature, pressure and mechanical property changes in the reliability test. separation stress. It also reduces the reliability and competitiveness of the product.

发明内容Contents of the invention

本发明所要解决的技术问题在于提供一种提升抗应力能力的芯片结构，以增加产品的可靠度及竞争力。此外，本发明另一个要解决的问题是还要提供一种制造该芯片结构的方法。The technical problem to be solved by the present invention is to provide a chip structure with improved stress resistance, so as to increase product reliability and competitiveness. In addition, another problem to be solved by the present invention is to provide a method for manufacturing the chip structure.

为解决上述提供一种提升抗应力能力的芯片结构问题，本发明提供之技术手段包括一种芯片结构，该芯片结构具有一基底、一焊垫、一第一保护层、一第二保护层以及一导电凸块。焊垫形成在基底上。第一保护层形成在基底上并露出焊垫。第二保护层形成在第一保护层上，第二保护层具有一保护层开口，保护层开口位于焊垫上方。导电凸块形成在焊垫上，部分导电凸块系填充于保护层开口内。其中，保护层开口底部的宽度大于保护层开口顶部的宽度，使第二保护层钳住导电凸块。In order to solve the above-mentioned problem of providing a chip structure that improves stress resistance, the technical means provided by the present invention include a chip structure, the chip structure has a base, a welding pad, a first protective layer, a second protective layer and A conductive bump. Pads are formed on the substrate. The first protection layer is formed on the base and exposes the pad. The second passivation layer is formed on the first passivation layer, the second passivation layer has a passivation layer opening, and the passivation layer opening is located above the welding pad. The conductive bump is formed on the welding pad, and part of the conductive bump is filled in the opening of the protection layer. Wherein, the width of the bottom of the opening of the protection layer is greater than the width of the top of the opening of the protection layer, so that the second protection layer clamps the conductive bump.

为解决上述芯片结构制造方法问题，本发明提供之技术手段包括一种芯片结构制造方法，该芯片结构制造方法包括：首先，提供一基底。然后，在基底上形成一第一保护层及一焊垫，且焊垫外露于第一保护层。接着，在第一保护层上形成一第二保护层，并且第二保护层具有一保护层开口以露出焊垫，保护层开口底部的宽度大于保护层开口顶部的宽度。最后，形成一导电凸块，部分导电凸块配置在保护层开口中，导电凸块与焊垫电性连接。In order to solve the above problems of the chip structure manufacturing method, the technical means provided by the present invention include a chip structure manufacturing method, the chip structure manufacturing method includes: firstly, providing a substrate. Then, a first protection layer and a welding pad are formed on the base, and the welding pad is exposed on the first protection layer. Next, a second passivation layer is formed on the first passivation layer, and the second passivation layer has an opening in the passivation layer to expose the welding pad, and the width of the bottom of the passivation layer opening is greater than the width of the top of the passivation layer opening. Finally, a conductive bump is formed, part of the conductive bump is disposed in the opening of the protection layer, and the conductive bump is electrically connected to the welding pad.

本发明所提供的芯片结构及其制造方法是利用保护层开口的底部宽度大于顶部宽度，从而可协助第二保护层夹持住导电凸块，防止导电凸块脱落离开焊垫及凸块下金属层。因此可增加芯片结构的可靠度及提升芯片结构的抗应力值。The chip structure and its manufacturing method provided by the present invention utilize the bottom width of the opening of the protective layer to be larger than the top width, thereby assisting the second protective layer to clamp the conductive bump and prevent the conductive bump from falling off from the solder pad and the metal under the bump. layer. Therefore, the reliability of the chip structure can be increased and the anti-stress value of the chip structure can be improved.

附图说明Description of drawings

图1A至图1G为表示传统形成芯片结构的示意图；FIG. 1A to FIG. 1G are schematic diagrams showing a conventional chip structure;

图2A至图2H分别表示形成芯片结构流程示意图；2A to 2H respectively represent a schematic flow chart of forming a chip structure;

图3为表示第二保护层形成底切示意图；Fig. 3 is a schematic diagram showing the formation of an undercut in the second protective layer;

第4图绘示形成芯片结构的流程图。FIG. 4 shows a flow chart of forming a chip structure.

其中，附图标记说明如下：Wherein, the reference signs are explained as follows:

100芯片结构      200芯片结构100-chip structure 200-chip structure

101基底          201基底101 bases 201 bases

103第一保护层    203第一保护层103 first protective layer 203 first protective layer

105焊垫          205焊垫105 solder pads 205 solder pads

107第二保护层    207第二保护层107 second protective layer 207 second protective layer

109保护层开口    209第二保护层109 protective layer opening 209 second protective layer

111凸块下金属层  211凸块下金属层111 UBM 211 UBM

113第一光阻层    213第一光阻层113 The first photoresist layer 213 The first photoresist layer

118第二光阻层    218第二光阻层118 second photoresist layer 218 second photoresist layer

119导电材料      244导电材料119 Conductive material 244 Conductive material

123导电凸块      223导电凸块123 conductive bumps 223 conductive bumps

237焦点          239光罩237 focus 239 mask

240光阻层开口240 photoresist openings

具体实施方式Detailed ways

请参考图2A至图2H以及图4，图2A至图2F分别表示形成芯片结构的流程示意图，图4表示形成芯片结构的流程图。如图2A所示，首先为步骤301，在基底201(Wafer)上形成第一保护层203(passivation layer)，并露出焊垫205(Pad)。焊垫205的材料通常是铝或铜，由此与外部电路形成电性连接。第一保护层203用于保护基底201并平坦化表面。接下来步骤303，如图2B所示，在第一保护层203上进一步形成一第二保护层207，并在第二保护层207上形成一保护层开口209。保护层开口209底部的宽度b1大于保护层开口209顶部的宽度b2，从而形成一底切(Undercut)。第二保护层207的材料例如为感光聚酰亚胺(photosensitive polyimide)，可用于达到吸收应力(Stress Buffer)及缓冲应力的效果。然后步骤305如图2C所示，在第二保护层207及焊垫205上沉积凸块下金属层211(Under Bump Metallurgy layer，UBM layer)。由于保护层开口209具有底切，因此当沉积凸块下金属层211时，第二保护层207上的凸块下金属层211不会连接至焊垫205上的凸块下金属层211。凸块下金属层211通常由一黏着层(adhesion layer)、阻障层(barrier layer)与一润湿层所组成(粘着层、阻障层及润湿层未显示在图中)。黏着层可以为焊垫205及第一保护层203提供良好的黏着性，其材料可为铝、钛、铬、钨化钛等。阻障层用于防止导电凸块223(绘示于第2H图中)与焊垫205的金属互相扩散，其材料可为镍钒、镍等。润湿层向凸块下金属层211与导电凸块223之间提供良好的粘附性，其材料可为铜、钼、铂。Please refer to FIG. 2A to FIG. 2H and FIG. 4 , FIG. 2A to FIG. 2F are respectively schematic flowcharts of forming a chip structure, and FIG. 4 is a flowchart of forming a chip structure. As shown in FIG. 2A , firstly, step 301 is to form a first passivation layer 203 (passivation layer) on a substrate 201 (Wafer) and expose a solder pad 205 (Pad). The material of the pad 205 is usually aluminum or copper, thereby forming an electrical connection with an external circuit. The first protective layer 203 is used to protect the substrate 201 and planarize the surface. Next step 303 , as shown in FIG. 2B , further forming a second protection layer 207 on the first protection layer 203 , and forming a protection layer opening 209 on the second protection layer 207 . The width b1 of the bottom of the protective layer opening 209 is greater than the width b2 of the top of the protective layer opening 209 , thereby forming an undercut. The material of the second protection layer 207 is, for example, photosensitive polyimide, which can be used to achieve the effect of absorbing stress (Stress Buffer) and buffering stress. Then step 305, as shown in FIG. 2C , deposits an Under Bump Metallurgy layer (UBM layer) on the second protection layer 207 and the pad 205 . Since the passivation layer opening 209 has an undercut, the UBM layer 211 on the second passivation layer 207 is not connected to the UBM layer 211 on the pad 205 when the UBM layer 211 is deposited. The UBM layer 211 is generally composed of an adhesion layer, a barrier layer and a wetting layer (the adhesion layer, the barrier layer and the wetting layer are not shown in the figure). The adhesive layer can provide good adhesion for the bonding pad 205 and the first protective layer 203 , and its material can be aluminum, titanium, chromium, titanium tungsten and so on. The barrier layer is used to prevent metal interdiffusion between the conductive bump 223 (shown in FIG. 2H ) and the pad 205 , and its material may be nickel vanadium, nickel, or the like. The wetting layer provides good adhesion between the UBM layer 211 and the conductive bump 223 , and its material can be copper, molybdenum, platinum.

接下来是步骤307，请参考图2D，在凸块下金属层211上形成一第一光阻层213，并图案化第一光阻层213。然后为步骤309，请参考图2E对部分的凸块下金属层211进行蚀刻，并移除第一光阻层213。接着步骤311，形成一第二光阻层218，并图案化第二光阻层218，使第二光阻层218具有一光阻层开口240。然后步骤313，在光阻层开口240内填充导电材料244，导电材料244例如为锡膏。而填充的方式较佳为以印刷方式填入到光阻层开口240内。最后，步骤315中回焊导电材料244以形成一导电凸块223，并移除第二光阻层218，而成为芯片结构200。Next is step 307 , please refer to FIG. 2D , forming a first photoresist layer 213 on the UBM layer 211 and patterning the first photoresist layer 213 . Then in step 309 , please refer to FIG. 2E to etch part of the UBM layer 211 and remove the first photoresist layer 213 . Next to step 311 , a second photoresist layer 218 is formed, and the second photoresist layer 218 is patterned so that the second photoresist layer 218 has a photoresist layer opening 240 . Then step 313 , filling the opening 240 of the photoresist layer with a conductive material 244 , such as solder paste. The filling method is preferably to fill the opening 240 of the photoresist layer by printing. Finally, in step 315 , the conductive material 244 is reflowed to form a conductive bump 223 , and the second photoresist layer 218 is removed to form the chip structure 200 .

如图2H所示，在芯片结构200中由于保护层开口209底部宽度b1大于顶部宽度b2，使保护层开口209的截面大致呈梯型。因此在芯片结构200中，导电凸块223的底部被锚定在保护层开口209内。当芯片结构200进行可靠度测试时，梯形状的保护层开口209可以增加导电凸块223抗应力的能力(应力是由不同的温度压力及机械性质变化所产生)。以下将说明，如何形成梯形状的保护层开口209。形成方式可透过下列几种，包括：第一种是以调整曝光机焦距的方式。第二种是采用过度显影的方式。As shown in FIG. 2H , in the chip structure 200 , since the bottom width b1 of the protection layer opening 209 is greater than the top width b2 , the cross section of the protection layer opening 209 is roughly trapezoidal. Therefore, in the chip structure 200 , the bottom of the conductive bump 223 is anchored in the protective layer opening 209 . When the reliability test of the chip structure 200 is performed, the trapezoid-shaped protective layer opening 209 can increase the stress resistance of the conductive bump 223 (the stress is generated by different temperature, pressure and mechanical property changes). How to form the trapezoidal protective layer opening 209 will be described below. There are several ways to form it, including: The first way is to adjust the focal length of the exposure machine. The second is the way of excessive development.

请参考图3，图3为第二保护层形成底切的示意图。在形成每一个保护层开口209时，通过调整曝光机，使光线经过光罩239，曝光时光线射入第二保护层207，光线焦点237位于第二保护层207的上方，并在底部形成一锐角θ，再经过显影去除部分的第二保护层207，使每个保护层开口209形成下部大上部小的梯形状。另外，第二种方式通过光线照在第二保护层207上方，第二保护层207所吸收光线的能量较高，因此通过显影时间的增加，第二保护层207底部被移除的量大于顶部，因而可以形成底切(Undercut)形状。Please refer to FIG. 3 , which is a schematic diagram of forming an undercut in the second protection layer. When forming each protective layer opening 209, by adjusting the exposure machine, the light passes through the mask 239, and the light enters the second protective layer 207 during exposure. The light focus 237 is located above the second protective layer 207, and forms a The acute angle θ is developed to remove part of the second protective layer 207 , so that each opening 209 of the protective layer forms a trapezoid with a larger lower part and a smaller upper part. In addition, in the second method, the second protective layer 207 is irradiated with light on the top of the second protective layer 207, and the energy of the light absorbed by the second protective layer 207 is relatively high. Therefore, by increasing the development time, the amount removed at the bottom of the second protective layer 207 is greater than that at the top. , thus forming an undercut (Undercut) shape.

本发明上述实施例所揭露的芯片结构，保护层开口的底部宽度大于顶部宽度，可协助第二保护层夹持住导电凸块，防止导电凸块脱落离开焊垫及凸块下金属层。因此，以增加芯片结构的可靠度及提升芯片结构的抗应力值。In the chip structure disclosed in the above embodiments of the present invention, the bottom width of the protective layer opening is larger than the top width, which can assist the second protective layer to clamp the conductive bump and prevent the conductive bump from falling off the pad and the UBM layer. Therefore, to increase the reliability of the chip structure and improve the anti-stress value of the chip structure.

以上所述仅为本发明其中的较佳实施例而已，并非用来限定本发明的实施范围；即凡依本发明权利要求所作的均等变化与修饰，皆为本发明专利范围所涵盖。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the implementation scope of the present invention; that is, all equivalent changes and modifications made according to the claims of the present invention are covered by the patent scope of the present invention.

Claims (10)

1. a chip structure is characterized in that, this chip comprises:
One substrate;
One weld pad is formed in this substrate;
One first protective layer is formed in this substrate and exposes this weld pad;
One second protective layer is formed on this first protective layer, and this second protective layer has a protective layer opening, and this protective layer opening is positioned at this weld pad top; And
One conductive projection is formed on this weld pad, and this conductive projection of part is filled in this protective layer opening;
Wherein the width of this protective layer open bottom makes this second protective layer vise this conductive projection greater than the width of this protective layer open top.
2. chip structure as claimed in claim 1 is characterized in that, this chip structure comprises that further (Under Bump Metallurgy layer UBM), is formed between this conductive projection and this weld pad projection lower metal layer.
3. chip structure as claimed in claim 2 is characterized in that, this projection lower metal layer more is formed between this conductive projection and this second protective layer.
4. a method that forms the described chip structure of claim 1 is characterized in that, this method may further comprise the steps:
One substrate is provided;
In this substrate, form one first protective layer and a weld pad, and this weld pad is for exposing to this first protective layer;
Form one second protective layer on this first protective layer, and this second protective layer has a protective layer opening to expose this weld pad, the width of this protective layer open bottom is greater than the width of this protective layer open top; And
Form a conductive projection, this conductive projection of part is configured in this protective layer opening, and this conductive projection and this weld pad electrically connect.
5. the method for formation chip structure as claimed in claim 4 is characterized in that, on this first protective layer, form after the step of this second protective layer and form the step of this conductive projection at this protective layer opening before more may further comprise the steps:
Deposition one projection lower metal layer on this second protective layer and this weld pad;
On this projection lower metal layer, form one first photoresist layer, and this first photoresist layer of patterning; And
This projection lower metal layer of part is carried out etching, and remove this first photoresist layer.
6. the method for formation chip structure as claimed in claim 5 is characterized in that, the step that forms this conductive projection comprises:
Form one second photoresist layer;
This second photoresist layer of patterning makes this second photoresist layer have a photoresist layer opening, and this photoresist layer opening is positioned at this protective layer opening top;
In this photoresist layer opening and this protective layer opening, fill an electric conducting material; And
This electric conducting material of reflow, and remove this second photoresist layer to form this conductive projection.
7. the method for formation chip structure as claimed in claim 4 is characterized in that, comprises in the step that forms this second protective layer:
This second protective layer of coating on this first protective layer, the material of this second protective layer is light-sensitive polyimide (photosensitive polyimide);
Use a light shield so that this second protective layer is exposed; And
This second protective layer is carried out overdevelop, to form this protective layer opening.
8. the method for formation chip structure as claimed in claim 4 is characterized in that, this second protective layer is being carried out more comprising in the step of exposing:
Adjust the exposure focal length of an exposure machine, the top that the feasible time line focus that exposes is positioned at this second protective layer forms acute angle.
9. the method for formation chip structure as claimed in claim 8 is characterized in that, further comprises in the step of this second protective layer of developing:
Control is developed time of this second protective layer, makes the top of the area of this second protective layer bottom institute liquid that is developed erosion greater than this second protective layer.
10. the method for formation chip structure as claimed in claim 9 is characterized in that, comprises in the step that forms this second protective layer:
This second protective layer of coating on this first protective layer, the material of this second protective layer is light-sensitive polyimide (photosensitive poiyimide);
Use a light shield so that this second protective layer is exposed, the time line focus that exposes is positioned at the top of this second protective layer; And
This second protective layer is developed to form this protective layer opening.
CNA2006100902951A 2006-07-11 2006-07-11 Chip structure and forming method thereof Pending CN101106114A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102201351A (en) * 2010-03-25 2011-09-28 新科金朋有限公司 Semiconductor device and method for forming dual UBM structure for lead free bump connection
CN102244019A (en) * 2010-05-12 2011-11-16 台湾积体电路制造股份有限公司 Semiconductor device and method for manufacturing the same
CN104465426A (en) * 2014-12-25 2015-03-25 颀中科技（苏州）有限公司 Protruding block manufacturing method and protruding block assembly
CN104952735A (en) * 2014-03-25 2015-09-30 中芯国际集成电路制造(上海)有限公司 Chip packaging structure having metal post and formation method of chip packaging structure
CN108666298A (en) * 2017-03-27 2018-10-16 中芯国际集成电路制造(北京)有限公司 Die stress test suite and preparation method thereof
CN109166791A (en) * 2018-07-23 2019-01-08 上海集成电路研发中心有限公司 A kind of hybrid bonded structure of autoregistration and preparation method thereof

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102201351A (en) * 2010-03-25 2011-09-28 新科金朋有限公司 Semiconductor device and method for forming dual UBM structure for lead free bump connection
US9711438B2 (en) 2010-03-25 2017-07-18 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming a dual UBM structure for lead free bump connections
CN102201351B (en) * 2010-03-25 2016-09-14 新科金朋有限公司 Semiconductor device and the method forming the double UBM structures connected for unleaded projection
US8993431B2 (en) 2010-05-12 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating bump structure
US9257401B2 (en) 2010-05-12 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating bump structure and bump structure
CN102244019A (en) * 2010-05-12 2011-11-16 台湾积体电路制造股份有限公司 Semiconductor device and method for manufacturing the same
CN104952735A (en) * 2014-03-25 2015-09-30 中芯国际集成电路制造(上海)有限公司 Chip packaging structure having metal post and formation method of chip packaging structure
CN104952735B (en) * 2014-03-25 2018-10-16 中芯国际集成电路制造(上海)有限公司 Chip-packaging structure and forming method thereof with metal column
CN104465426A (en) * 2014-12-25 2015-03-25 颀中科技（苏州）有限公司 Protruding block manufacturing method and protruding block assembly
CN104465426B (en) * 2014-12-25 2018-04-27 颀中科技（苏州）有限公司 The production method of convex block
CN108666298A (en) * 2017-03-27 2018-10-16 中芯国际集成电路制造(北京)有限公司 Die stress test suite and preparation method thereof
CN108666298B (en) * 2017-03-27 2019-12-10 中芯国际集成电路制造(北京)有限公司 Chip stress testing assembly and preparation method thereof
CN109166791A (en) * 2018-07-23 2019-01-08 上海集成电路研发中心有限公司 A kind of hybrid bonded structure of autoregistration and preparation method thereof

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