CN101075481B - Shift register and signal generator thereof - Google Patents

Abstract

A shift register includes a first switch, a transistor, a controlled switching element, and a second switch. The first switch includes a first input terminal, a first control terminal, and a first output terminal. The first input terminal is coupled to the input signal, and the first control terminal is coupled to the first clock signal. The transistor has a gate, a first source/drain and a second source/drain. The gate is coupled to the first output terminal, and the first source/drain is coupled to the second clock signal. The controlled switching element includes a first controlled input terminal, a second controlled input terminal, a switch control terminal, and a second switch. The first controlled input terminal is coupled to the third clock signal. The second controlled input terminal is coupled to the first voltage, and the switch control terminal is coupled to the first output terminal. The second switch includes a second input terminal, a second control terminal, and a second output terminal. The second input terminal is coupled to the first voltage, the second control terminal is coupled to the controlled output terminal, and the second output terminal is coupled to the second source/drain of the transistor for outputting the output signal.

Description

Shift register and its signal generator

technical field

The present invention relates to a shift register and a signal generator thereof, and in particular to a shift register and a signal generator thereof which avoid floating of a signal output end.

Background technique

FIG. 1A is a structural diagram of a shift register circuit of a scan driver known in US Patent Publication No. 20040174189. 1A, the shift register 100 includes three N-type metal oxide semiconductor (N-type Metal Oxide Semiconductor, NMOS) field effect transistors 101, 102 and 103 and a capacitor 104. The drain of the first transistor 101 is coupled to the input signal IN, the gate of the transistor 101 is controlled by the clock signal CKA, and the source of the transistor 101 is used to output the control signal C1. The drain of the second transistor 102 is coupled to the clock signal CKB, the gate of the transistor 102 is controlled by the control signal C1 , and the source of the transistor 102 is used to output an output signal OUT. In addition, the drain of the third transistor 103 is coupled to the source of the transistor 102, the source of the transistor 103 is coupled to the voltage VSS, and the gate of the transistor 103 is controlled by the clock signal CKA, wherein the clock signal CKB It is the inverted signal of the clock signal CKA. The capacitor 104 is coupled between the source and the gate of the transistor 102 .

Please also refer to FIG. 1B , which shows a timing diagram of related signals of the shift register 100 in FIG. 1A . As shown in FIG. 1B , in the first clock period T1 , the input signal IN has a VSS level (for example, 0V), and the clock signals CKA and CKB have VDD (for example, 9V) and VSS levels, respectively. At this time, the transistor 101 is turned on, so that the control signal C1 has a level of (VDD-Vt), where Vt is the threshold voltage (Threshold Voltage) of the transistor 101 . At the same time, the clock signal CKA also turns on the transistor 103 , so that the output signal OUT has the VSS level, and the transistor 102 is also turned on. At this time, the capacitor 104 is charged to store a cross voltage of (VDD-Vt-VSS). Then, in the second clock period T2, the input signal IN has a VDD level, and the clock signals CKA and CKB have VSS and VDD levels, respectively. At this time, the transistor 101 is not turned on. The clock signal CKB rises from the VSS level to the VDD level, and at the same time increases the source voltage of the transistor 102 (the voltage at point P). Therefore, through the voltage across the capacitor 104 , the gate voltage of the transistor 102 also rises accordingly, and the transistor 102 is turned on because the gate voltage is higher than the source voltage. However, since the clock signal CKA has a VSS level, the transistor 103 is not turned on, so that the drain of the transistor 103 , that is, the signal output terminal P may appear in a floating state.

Next, in the third clock period, the input signal IN has a VSS level, and the clock signals CKA and CKB have VSS and VDD levels. As mentioned above, the transistors 101 and 103 are both non-conductive, so that the signal output terminal P also appears in a floating state. When the signal output terminal P is in a floating state, the scan line signal of the scan driver is easily interfered by the control voltage Vcom and the data line signal, which will cause the output signal of the scan line to be unstable, affect the subsequent pixel voltage, and cause the display image to flicker phenomenon, degrading image quality.

Contents of the invention

In view of this, the object of the present invention is to provide a novel shift register and its signal generator. A controlled switching element is added between the gate of the third transistor and the gate of the second transistor, so that when the third transistor is not conducting, the controlled switching element is turned on, so as to avoid the signal output terminal being in Image flicker phenomenon caused by the floating state, thereby improving the image quality of the display.

According to the object of the present invention, a shift register is provided for receiving an input signal and outputting an output signal accordingly. The shift register includes a first switch, a transistor, a controlled switching element, and a second switch. The first switch includes a first input terminal, a first control terminal and a first output terminal. The first input terminal is coupled to the input signal, and the first control terminal is coupled to the first clock signal. The transistor has a gate, a first source/drain and a second source/drain. The gate is coupled to the first output terminal, and the first source/drain is coupled to the second clock signal. The controlled switching element includes a first controlled input terminal, a second controlled input terminal, a switch control terminal and a second switch. The first controlled input terminal is coupled to the third clock signal. The second controlled input terminal is coupled to the first voltage, and the switch control terminal is coupled to the first output terminal. The second switch includes a second input terminal, a second control terminal and a second output terminal. The second input terminal is coupled to the first voltage, the second control terminal is coupled to the controlled output terminal, and the second output terminal is coupled to the second source/drain of the transistor for outputting the output signal.

Wherein the first clock signal controls the first switch to be turned on, and outputs an input signal, so that the controlled switching element is turned on, and the third clock signal makes the controlled output terminal output a second voltage, and controls the second switch to be turned on, and the output signal The level of is the first voltage;

Wherein the first clock signal controls the first switch to be non-conductive, and the second clock signal boosts and lowers the level of the first output end, so that the transistor is turned on, and the output signal is the second clock signal, and at the same time, the level of the first output end changes, so that The controlled switch element is turned on, and the third clock signal makes the controlled output end output the first voltage, and controls the second switch not to be turned on.

According to the object of the present invention, a signal generator including a multi-stage shift register is proposed. The shift registers of each stage are used to receive the input signal from the upper stage shift register and output an output signal accordingly. The shift register of each stage includes a first switch, a transistor, a controlled switching element and a second switch. The first switch includes a first input terminal, a first control terminal and a first output terminal. The first input terminal is coupled to the input signal, and the first control terminal is coupled to the first clock signal. The transistor has a gate, a first source/drain and a second source/drain. The gate is coupled to the first output terminal, and the first source/drain is coupled to the second clock signal. The controlled switching element includes a first controlled input terminal, a second controlled input terminal, a switch control terminal and a second switch. The first controlled input terminal is coupled to the third clock signal. The second controlled input terminal is coupled to the first voltage, and the switch control terminal is coupled to the first output terminal. The second switch includes a second input terminal, a second control terminal and a second output terminal. The second input terminal is coupled to the first voltage, the second control terminal is coupled to the controlled output terminal, and the second output terminal is coupled to the second source/drain of the transistor for outputting the output signal.

Wherein the first clock signal controls the first switch to be turned on, and outputs an input signal, so that the controlled switching element is turned on, and the third clock signal makes the controlled output terminal output a second voltage, and controls the second switch to be turned on, and the output signal The level of is the first voltage;

Wherein the first clock signal controls the first switch to be non-conductive, and the second clock signal boosts and lowers the level of the first output end, so that the transistor is turned on, and the output signal is the second clock signal, and at the same time, the level of the first output end changes, so that The controlled switch element is turned on, and the third clock signal makes the controlled output end output the first voltage, and controls the second switch not to be turned on.

According to the purpose of the present invention, a shift register is proposed, including a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor. The source of the first transistor receives an input signal, and the gate of the first transistor receives a first clock signal. The gate of the second transistor is coupled to the drain of the first transistor, the source of the second transistor receives the second clock signal, and the drain of the second transistor outputs an output signal. The drain of the third transistor is coupled to the source of the second transistor, and the source of the third transistor receives the reference voltage. The gate and drain of the fourth transistor are coupled to the first clock signal, and the source of the fourth transistor is coupled to the gate of the third transistor. The drain of the fifth transistor is coupled to the source of the fourth transistor, the source of the fifth transistor receives the reference voltage, and the gate of the fifth transistor is coupled to the gate of the second transistor.

In order to make the above-mentioned purposes, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, and in conjunction with the accompanying drawings, the detailed description is as follows:

Description of drawings

FIG. 1A is a structural diagram of a shift register circuit of a scan driver known in US Patent Publication No. 20040174189.

FIG. 1B is a timing diagram of related signals of the shift register in FIG. 1A .

FIG. 2 is a block diagram of a signal generator circuit according to a preferred embodiment of the present invention.

FIG. 3 is a circuit diagram of the shift register in FIG. 2 .

FIG. 4 is a timing diagram of signals related to the shift register in FIG. 2 .

FIGS. 5A-5C are schematic diagrams respectively showing the switching states of the transistors in the shift register in FIG. 2 in the first period to the third period.

[Description of main component labels]

1: Gate

2: Source

3: drain

100, 210: shift register

101, 102, 103: Transistors

104: capacitance

200: signal generator

201, 202, 203, 204, 205: transistors

Detailed ways

Please refer to FIG. 2 , which shows a circuit block diagram of a signal generator according to a preferred embodiment of the present invention. The signal generator 200 is, for example, a scan driver of a display, which includes a multi-stage shift register 210 . The shift registers 210 of each stage are used to receive the input signals IN (STV, OUT1, . The first-stage shift register 210 receives a start signal STV.

Please also refer to FIG. 3 , which shows a circuit structure diagram of the shift register 210 in FIG. 2 . The shift register 210 of each stage includes NMOS transistors 201 , 202 , 203 , 204 and 205 . The drain ( 3 ) of the transistor 201 is coupled to the input signal IN, and the gate ( 1 ) of the transistor 201 is coupled to the first clock signal CKA. The gate ( 1 ) of the transistor 202 is coupled to the source ( 2 ) of the transistor 201 (or node A0 ), and the drain ( 3 ) of the transistor 202 is coupled to the second clock signal CKB. The transistor 204 is a diode-coupled transistor, its gate ( 1 ) and drain ( 3 ) are coupled to a positive terminal (+), and its source ( 2 ) is a negative terminal (-). The positive terminal (+) of the transistor 204 is coupled to the first clock signal CKA. The source (2) of the transistor 205 is coupled to the first voltage VSS, for example -6~-7V, the gate (1) of the transistor 205 is coupled to the source (2) of the transistor 201, and the drain of the transistor 205 (3) Coupled to the negative terminal (−) of the transistor 204 (or node A1 ). In addition, the source (2) of the transistor 203 is coupled to the first voltage VSS, the gate (1) of the transistor 203 is coupled to the drain (3) of the transistor 205, and the drain (3) of the transistor 203 is coupled to The source (2) of the transistor 202 is used to output the output signal OUT.

It should be noted that, as shown in FIG. 2 , the second clock signal CKB ( CK3 or CK4 ) is an inverted signal of the first clock signal CKA ( CK1 or CK2 ). Moreover, the phase of the first clock signal CKA (=CK1) or the second clock signal CKB (=CK3) of any shift register 210 is the same as that of the first clock signal CKA (=CK2) or the second clock signal CKA (=CK2) of the shift register 210 of the next stage. The two clock signals CKB (=CK4) have a phase difference of 1/4 clock period (T/4).

FIG. 4 is a timing diagram of signals related to the shift register 210 in FIG. 2 , and FIGS. 5A to 5C are diagrams respectively showing the transistors 201 to 205 of the shift register 210 in the first cycle to the third cycle T1 to T3 in FIG. 2 . Schematic diagram of the switch state. Please refer to FIG. 4 and FIG. 5A at the same time. In the first period T1 (T1=T/4), the input signal IN and the first clock signal CKA have a VDD level (for example, 20V), so that the transistor 201 is turned on and the transistor 201 The source (A0 voltage) has a (VDD-Vt) level, where Vt is the initial voltage value of the transistor 201 . Simultaneously, the gate voltage (= A0 voltage) of transistor 205 is (VDD-Vt) (about 20V-2.5V=17.5V) is higher than the source voltage VSS of transistor 205 (about-6～-7V), therefore Transistor 205 is turned on. Since the drain voltage (A1 voltage) of the transistor 205, that is, the negative terminal voltage of the transistor 204 is determined by the bias voltage of the transistor 204 at the same time, the drain voltage of the transistor 205 will be higher than its source voltage VSS and lower than the transistor 204 positive terminal voltage VDD. At this time, the gate voltage (=A1 voltage) of the transistor 203 is higher than the source voltage VSS of the transistor 203, so the transistor 203 is turned on, and the output signal OUT outputs the first voltage VSS.

Please refer to FIG. 4 and FIG. 5B at the same time. Then, in the second period T2 (T2=T/4), the input signal IN and the second clock signal CKB have a VDD level, and the first clock signal CKA has a VSS level. making transistor 201 non-conductive. At this time, since the gate-source parasitic capacitance Cgs of the transistor 202 has stored the cross voltage (VDD-Vt-VSS) in the previous period, when the second clock signal CKB changes from the VSS level to the VDD level, the source of the transistor 202 The terminal voltage will be pulled up accordingly, and the gate voltage (A0 voltage) of the transistor 202 will be increased through the capacitor Cgs, so that the transistor 202 is completely turned on, and the output signal OUT has a VDD level. Finally, the A0 voltage is pulled up to (2*VDD-Vt-VSS). Meanwhile, the gate voltage (=A0 voltage) of the transistor 205 is (2*VDD-Vt-VSS) (~2*20V-2.5V-(-6V)=43.5V) which is higher than the source voltage VSS of the transistor 205 (approximately -6~-7V), so the transistor 204 is turned on, the voltage of A1 is VSS, and the transistor 203 is not turned on. In this way, the drain of the transistor 203 (that is, the signal output terminal) can be coupled to the first voltage VSS via the parasitic capacitance Cgs of the transistor 202 and the node A0 to form a current path, so as to avoid the non-conduction of the transistor 103 in the prior art. The floating state of the signal output terminal generated at the time.

Please refer to FIG. 4 and FIG. 5C at the same time, then in the third period T3 (T3=T/4), the input signal IN and the first clock signal CKA have a VSS level, and the second clock signal CKB has a VDD level, so that Transistor 201 is still not conducting. The voltage of A0 remains at the level of (2*VDD-Vt-VSS), and the transistor 202 is turned on, so that the output signal OUT has the VDD level of the second clock signal CKB. Similarly, at this time, the transistor 205 is turned on, and the voltage of A1 is at the VSS level, so that the transistor 203 is not turned on. The drain of the transistor 203 (that is, the signal output terminal) can also be coupled to the first voltage VSS via the parasitic capacitance Cgs of the transistor 202 and the node A0 to form a current path, so as to avoid the signal generated when the transistor 103 is not turned on in the prior art. Floating state of the output. Therefore, according to the shift register 210 of the present invention, the phase of the input signal IN can be delayed by 1/4 clock period (T/4).

It should be noted that when the output signal OUT of any stage of shift register 210 is input to the next stage of shift register 210, since the output signal OUT is delayed by T/4 time compared with the input signal IN, while the next stage The first clock signal CKA (=CK2) and the second clock signal CKB (=CK4) of the shift register 210 are also compared with the first clock signal CKA (=CK1) and the second clock signal CKB (=CK4) of the shift register 210 of this stage respectively. CK3) Delay T/4 time. Therefore, the timing level changes of the input signal IN, the clock signals CKA and CKB, and the output signal OUT of the shift register 210 of the next stage are completely consistent with the timing level changes of the shift register 210 of this stage. The phase of IN is delayed by T/4.

As mentioned above, although the present invention is described by taking the shift register 210 having NMOS transistors 201 - 205 as an example, the shift register 210 of the present invention can also be realized by using PMOS transistors. Alternatively, the transistors 201 , 203 and 205 can also be realized by using other switch elements, such as the first switch, the second switch and the third switch respectively. Or even transistors 204 and 205 may be controlled switching elements of other circuit configurations, including a first controlled input terminal coupled to a third clock signal, a second controlled input terminal coupled to a first voltage VSS, a second controlled input terminal coupled to a first voltage VSS, and a second controlled input terminal coupled to a second clock signal. A switch control terminal of the switch output terminal and a controlled output terminal coupled to the second switch control terminal. As long as the first switch is turned on, the input signal controls the controlled switch element to be turned on, and the third clock signal makes the controlled output terminal output a second voltage to turn on the second switch; and when the first switch is not turned on, the second switch is turned on. The second clock signal makes the transistor 202 turn on, and the gate of the buck-boost transistor 202 makes the controlled switching element turn on, and the third clock signal makes the controlled output end output the first voltage to turn off the second switch, which can avoid the signal output end (The second switch output terminal) is in a floating state to achieve the purpose of improving the image quality of the display, and therefore all do not depart from the technical scope of the present invention.

The advantage of the shift register and its signal generator disclosed in the above embodiments of the present invention is that it uses three transistors and a simple controlled switch element, and the controlled switch element is turned on when the transistor coupled to the signal output terminal is not turned on. In order to form a current path between the signal output terminal and the operating voltage, the problem of flickering of the display image caused by the floating state of the signal output terminal is avoided, thereby improving the display image quality of the display.

In summary, although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make various modifications without departing from the spirit and scope of the present invention. Changes and modifications, so the protection scope of the present invention should be defined by the scope of the appended claims.

Claims (17)

1. A kind of shift register, in order to receive input signal, and output an output signal accordingly, this shift register comprises: First switch, including: a first input terminal coupled to the input signal; a first control terminal coupled to a first clock signal; and first output terminal; a transistor having a gate, a first source/drain and a second source/drain, the gate is coupled to the first output terminal, and the first source/drain is coupled to a second clock signal; as well as Controlled switching elements, including: the first controlled input terminal is coupled to the third clock signal; the second controlled input terminal is coupled to the first voltage; a switch control terminal coupled to the first output terminal; and a controlled output; and A second switch, including: a second input terminal coupled to the first voltage; a second control terminal coupled to the controlled output terminal; a second output terminal coupled to the second source/drain of the transistor for outputting the output signal, Wherein, the first clock signal controls the first switch to be turned on, and outputs the input signal, so that the controlled switching element is turned on, and the third clock signal makes the controlled output terminal output a second voltage, and controls the first the two switches are turned on, and the level of the output signal is the first voltage; Wherein, the first clock signal controls the first switch to be non-conductive, the second clock signal boosts and lowers the level of the first output terminal, so that the transistor is conductive, the output signal is the second clock signal, and the The level of the first output end changes, so that the controlled switching element is turned on, the third clock signal makes the controlled output end output the first voltage, and controls the second switch to be non-conductive, Wherein the third clock signal is the first clock signal. 2. The shift register according to claim 1, wherein the controlled switching element further comprises: a diode coupled to the transistor, has a positive terminal and a negative terminal, and the positive terminal is coupled to the third clock signal; and A third switch, including: a third input terminal coupled to the first voltage; a third control terminal coupled to the first output terminal; and The third output terminal is coupled to the negative terminal of the diode-coupled transistor and the second control terminal. 3. The shift register according to claim 2, wherein the first switch, the second switch, the third switch, the diode-coupled transistor and the transistor are all implemented by NMOS transistors. 4. The shift register according to claim 3, wherein the first voltage has a low level, and the second voltage is higher than the first voltage. 5. The shift register according to claim 1, wherein the second clock signal is an inverted signal of the first clock signal. 6. A signal generator comprising: Multi-level shift registers, each level of shift register is used to receive the input signal from the upper level shift register, and output an output signal accordingly, each level of shift register includes: First switch, including: a first input terminal coupled to the input signal; a first control terminal coupled to a first clock signal; and first output terminal; a transistor having a gate, a first source/drain and a second source/drain, the gate is coupled to the first output terminal, and the first source/drain is coupled to a second clock signal; as well as Controlled switching elements, including: a first controlled input terminal coupled to the third clock signal; the second controlled input terminal is coupled to the first voltage; a switch control terminal coupled to the first output terminal; and a controlled output; and A second switch, including: a second input terminal coupled to the first voltage; a second control terminal coupled to the controlled output terminal; a second output terminal coupled to the second source/drain of the transistor for outputting the output signal, Wherein, the first clock signal controls the first switch to be turned on, and outputs the input signal, so that the controlled switching element is turned on, and the third clock signal makes the controlled output terminal output a second voltage, and controls the first the two switches are turned on, and the level of the output signal is the first voltage; Wherein, the first clock signal controls the first switch to be non-conductive, the second clock signal boosts and lowers the level of the first output terminal, so that the transistor is conductive, the output signal is the second clock signal, and the The level of the first output end changes, so that the controlled switching element is turned on, the third clock signal makes the controlled output end output the first voltage, and controls the second switch to be non-conductive, Wherein the third clock signal is the first clock signal. 7. The signal generator according to claim 6, wherein the controlled switching element further comprises: a diode coupled to the transistor, has a positive terminal and a negative terminal, and the positive terminal is coupled to the first clock signal; and A third switch, including: a third input terminal coupled to the first voltage; a third control terminal coupled to the first output terminal; and The third output terminal is coupled to the negative terminal of the diode-coupled transistor and the second control terminal. 8. The signal generator according to claim 7, wherein the first switch, the second switch, the third switch, the diode-coupled transistor and the transistor are all implemented by NMOS transistors. 9. The signal generator according to claim 8, wherein the first voltage has a low level, and the second voltage is higher than the first voltage. 10. The signal generator according to claim 6, wherein the second clock signal is an inverted signal of the first clock signal. 11. The signal generator according to claim 10, wherein the phase of the first clock signal of the shift register of the current stage is different from the phase of the first clock signal of the shift register of the next stage by 1/4 clock period. 12. The signal generator according to claim 6 is a scan driver. 13. A shift register comprising: a first transistor, receiving an input signal through a source of the first transistor, and receiving a first clock signal through a gate of the first transistor; a second transistor, the gate of the second transistor is coupled to the drain of the first transistor, the source of the second transistor receives a second clock signal, and the drain of the second transistor outputs an output signal; a third transistor, the drain of the third transistor is coupled to the source of the second transistor, and the source of the third transistor receives a reference voltage; a fourth transistor, the gate of the fourth transistor and the drain of the fourth transistor are coupled to the first clock signal, and the source of the fourth transistor is coupled to the gate of the third transistor; and A fifth transistor, the drain of the fifth transistor is coupled to the source of the fourth transistor, the source of the fifth transistor receives the reference voltage, and the gate of the fifth transistor is coupled to the gate of the second transistor. 14. The shift register according to claim 13, wherein the first clock signal controls the first transistor to be turned on, and outputs the input signal to make the fifth transistor turn on, and the first clock signal makes the fourth The source of the transistor outputs a second voltage, and controls the third transistor to be turned on, and the level of the output signal is the reference voltage; Wherein, the first clock signal controls the first transistor to be non-conductive, the second clock signal boosts and lowers the level of the drain of the first transistor, so that the second transistor is conductive, and the output signal is the second At the same time, the level of the drain of the first transistor changes to make the fifth transistor turn on, the first clock signal makes the source of the fourth transistor output the reference voltage, and controls the third transistor not to turn on Pass. 15. The shift register according to claim 14, wherein the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are all realized by NMOS transistors. 16. The shift register according to claim 15, wherein the reference voltage has a low level, and the second voltage is higher than the reference voltage. 17. The shift register according to claim 16, wherein the second clock signal is an inverted signal of the first clock signal.

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