CN103956133B - shift register circuit and shift register - Google Patents

Abstract

The invention discloses a shift temporary storage circuit having multiple shift temporary registers. Each shift register has at least four input terminals, a pull-up circuit, a first switch, a first pull-down circuit and a second pull-down circuit. The control terminal of the first switch is coupled to the node. The pull-up circuit is used to pull up the potential of the node. The first pull-down circuit is used to pull down the potential of the output terminal of the shift register. The second pull-down circuit is used to pull down the potential of the node. The above four input terminals receive different clock signals respectively to suppress the surge generated at the node due to the coupling effect of the parasitic capacitance of the first switch, and to avoid the two transistors of the first pull-down circuit and the second pull-down circuit from generating Positive bias stress effect.

Description

Shift register circuit and shift register

technical field

The present invention relates to a shift register circuit and a shift register, in particular to a shift register capable of alleviating the coupling effect (coupling effect) and positive bias stress (positive bias stress; PBS) effect of transistor parasitic capacitance. Temporary storage circuit and shift register.

Background technique

Generally speaking, a display panel includes a plurality of pixels, a gate driving circuit and a source driving circuit. The gate driving circuit includes a multi-level shift register for providing multiple gate driving signals to control the on and off of the pixels. The source driving circuit is used for writing data signals to the turned-on pixels. In addition, the current display panel often adopts a gate driver on array (GOA) technology to provide the gate driving signal required by the pixels. Different from the traditional gate driver, the circuit using GOA can reduce the production cost of the panel because its manufacturing process can be combined with the manufacturing process of the thin film transistor array (TFT array) of the display panel.

Please refer to Figure 1 and Figure 2. FIG. 1 is a circuit diagram of a conventional shift register 100 . FIG. 2 is a timing diagram of the shift register 100 of FIG. 1 . The shift register 100 includes four switches T1a to T1d. Among them, the switches T1a and T1c receive input signals G _N-1 and G _N+1 respectively, and the input signals G _N-1 and G _N+1 come from the output terminals of the previous stage and the subsequent stage shift register . The first terminal of the switch T1b receives the clock signal CK, the control terminal of the switch T1b is coupled to the node Q _N , and the second terminal of the switch T1b is coupled to the output terminal of the shift register 100 to output the output signal G _N . The first terminals of the switches _T1c and T1d are respectively coupled to the node QN and the output terminal of the shift register 100, and the second terminals of the switches T1c and T1d are both coupled to the system voltage terminal VSS. The potential of the system voltage terminal VSS may be the same as the low gate potential VGL. In addition, the input signal G _N+1 is transmitted to the control terminals of the switches T1c and T1d to control the opening and closing of the switches T1c and T1d. In addition, another clock signal XCK is used to control the operation of the previous stage and the next stage shift register, and the clock signal XCK and the clock signal CK will be between the gate high potential VGH and the gate low potential VGL switch.

During the time period _TA , the switch T1a is turned on due to the input signal G _N-1 being at the high gate potential VGH, so that the potential of the node Q _N is pulled up to the high gate potential VGH, and the switch T1b is turned on. In addition, the switches T1c and T1d are turned off because the input signal G _N+1 is at the gate low potential VGL. Since the switch T1b is turned on and the clock signal CK is at the gate low potential VGL, the output signal G _N output from the output terminal of the shift register 100 is at the gate low potential VGL.

During the period TB, the switches T1a, _T1c and T1d are turned off due to the input signals G _N−1 and G _N+1 being at the gate low potential VGL, so that the node Q _N is in a floating state. In addition, because the potential of the clock signal CK is the gate high potential VGH, and due to the coupling effect of the parasitic capacitance of the switch T1b, the potential of the node Q _N is raised to approximately twice the VGH, and the output signal G _N The potential is the gate high potential VGH.

During the period T _C , the switch T1a is turned off due to the input signal G _N-1 being at the gate low potential VGL, and the switches T1c and T1d are turned on due to the input signal G _N+1 being at the gate high potential VGH. The potential of the node Q _N is pulled down to the gate low potential VGL because the switch _T1c is turned on, and the potential of the output signal GN is also pulled down to the gate low potential VGL because the switch T1d is turned on.

However, due to the coupling effect of the parasitic capacitor of the switch T1b, the input signal G _N-1 outputted from the output terminal of the shift register in the previous stage has not yet been received by the low gate potential VGL again. Before being pulled up to the gate high potential VGH, since the potential of the clock signal CK is still switching between the gate high potential VGH and the gate low potential VGL, it is easy to generate a glitch at the node Q _N , and Furthermore, the waveform of the output signal G _N of the shift register 100 is incorrect. In addition, since the switches T1c and T1d use the low gate potential VGL as their low-level signal, the switches T1c and T1d are prone to produce positive bias stress (positive bias stress; PBS) effect, so that the switches T1c and T1d can be used for a long time. After the operation, the threshold voltage will have a positive shift, resulting in a decrease in the driving capability of the switches T1c and T1d.

Contents of the invention

An embodiment of the invention provides a shift register. The shift register includes a signal terminal, a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, an output terminal, a pull-up circuit, a first switch, a first pull-down circuit and a second Two pull-down circuits. The signal end receives an input signal. The first input end receives a first clock signal. The second input end receives the second clock signal. The third input end receives a third clock signal. The fourth input terminal receives a fourth clock signal. The pull-up circuit is coupled to the signal terminal and the first input terminal, and is used for controlling the electrical connection between the signal terminal and the node according to the first clock signal. The first switch is coupled to the second input terminal, the node and the output terminal, and is used for controlling the electrical connection between the second input terminal and the output terminal according to the potential of the node. The first pull-down circuit is coupled to the third input terminal, the output terminal and the fourth input terminal, and is used for controlling the electrical connection between the output terminal and the fourth input terminal according to the third clock signal. The second pull-down circuit is coupled to the node and the first input terminal, and is used for controlling the electrical connection between the node and the first input terminal according to the fourth clock signal or the fifth clock signal.

An embodiment of the invention provides a shift register circuit. The shift register circuit includes a plurality of shift registers. Each shift register signal terminal, first input terminal, second input terminal, third input terminal, fourth input terminal, output terminal, pull-up circuit, first switch, first pull-down circuit, second pull-down circuit and a third pull-down circuit. The pull-up circuit is coupled to the signal terminal, the node and the first input terminal, and is used for controlling the electrical connection between the signal terminal and the node according to the potential of the first input terminal. The first switch is coupled to the second input terminal, the node and the output terminal, and is used for controlling the electrical connection between the second input terminal and the output terminal according to the potential of the node. The first pull-down circuit is coupled to the third input terminal, the output terminal and the fourth input terminal, and is used for controlling the electrical connection between the output terminal and the fourth input terminal according to the potential of the third input terminal. The second pull-down circuit is coupled to the node, the first input terminal and the fourth input terminal, and is used for controlling the electrical connection between the node and the first input terminal according to the potential of the fourth input terminal. The third pull-down circuit is coupled to the node, the third input terminal and the fourth input terminal, and is used for controlling the electrical connection between the node and the fourth input terminal according to the potential of the third input terminal. Wherein the first input terminal, the second input terminal, the third input terminal and the fourth input terminal respectively receive different clock signals.

An embodiment of the invention provides a shift register circuit. The shift register circuit includes a plurality of shift registers. Each shift register signal terminal, first input terminal, second input terminal, third input terminal, fourth input terminal, fifth input terminal, output terminal, pull-up circuit, first switch, first pull-down circuit and a second pull-down circuit. The pull-up circuit is coupled to the signal terminal, the node and the first input terminal, and is used for controlling the electrical connection between the signal terminal and the node according to the potential of the first input terminal. The first switch is coupled to the second input terminal, the node and the output terminal, and is used for controlling the electrical connection between the second input terminal and the output terminal according to the potential of the node. The first pull-down circuit is coupled to the third input terminal, the output terminal and the fourth input terminal, and is used for controlling the electrical connection between the output terminal and the fourth input terminal according to the potential of the third input terminal. The second pull-down circuit is coupled to the node, the first input terminal and the fifth input terminal, and is used for controlling the electrical connection between the node and the first input terminal according to the potential of the fifth input terminal. Wherein the first input terminal, the second input terminal, the third input terminal, the fourth input terminal and the fifth input terminal respectively receive different clock signals.

Through the shift register of the embodiment of the present invention, since the switches of each pull-down circuit use the clock signal as its low-level signal, the switches of each pull-down circuit can be subject to positive bias stress due to long-time operation ( Under the influence of the PBS) effect, a periodic reverse bias stress (NBS) effect is applied to the switch of the pull-down circuit to produce a recovery effect on the threshold voltage (Vth) and improve the problem of reduced driving capability. In addition, the switch of the second pull-down circuit can be slightly turned on or fully turned on in time, so that the surge generated at the control terminal of the first switch due to the coupling effect of the parasitic capacitance of the first switch can be suppressed.

Description of drawings

Fig. 1 is the circuit diagram of the shift register of prior art;

FIG. 2 is a timing diagram of the shift register of FIG. 1;

3 is a circuit diagram of a shift register according to an embodiment of the present invention;

4 is a schematic diagram of a shift register circuit according to an embodiment of the present invention;

FIG. 5 is a timing diagram of the shift register circuit of FIG. 4;

6 is a circuit diagram of a shift register according to another embodiment of the present invention;

FIG. 7 is a schematic diagram of a shift register circuit according to another embodiment of the present invention.

Among them, reference signs;

100, 300, 300_5, 500_5 shift register

300_1, 500_1 shift register, first shift register

300_2, 500_2 shift register, second shift register

300_3, 500_3 shift register, third shift register

300_4, 500_4 shift register, fourth shift register

310 pull-up circuit

320 first switch

330 First pull-down circuit

340, 540 second pull-down circuit

350 third pull-down circuit

400, 700 shift register circuit

C1 capacitor, the first capacitor

C2 capacitor, second capacitor

CK, XCK clock signal

CK1 clock signal, second clock signal

CK_1 clock signal, sixth clock signal

CK2 clock signal, fifth clock signal

CK_2 clock signal, third clock signal

CK3 clock signal, fourth clock signal

CK_3 clock signal, seventh clock signal

CK4 clock signal, eighth clock signal

CK_4 clock signal, the first clock signal

G _N output signal

G _N-1 , G ₁ to G ₅ input signal

G _N+1 input signal, output signal

IN signal terminal

IN1 first input terminal

IN2 Second input terminal

IN3 Third input terminal

IN4 Fourth input terminal

IN5 Fifth input terminal

Q _N node

The node of the shift register after Q _N+1

Out output terminal

SP start signal

T1a, T1e switch

T1b switch, first switch

T1c switch, third switch

T1d switch, second switch

T1 period, first period

T2, T4, T6, T _A , T _B , T _C period

T3 period, second period

T5 period, third period

T7 period, fourth period

T _P cycle

VGH gate high potential

2VGH twice the gate high potential

VGL gate low potential

VGL1 first gate low potential

VGL2 second gate low potential

VSS system voltage terminal

detailed description

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

Please refer to FIG. 3 , which is a circuit diagram of a shift register 300 according to an embodiment of the present invention. The shift register 300 includes a signal terminal IN, a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, a fourth input terminal IN4, an output terminal Out, a pull-up circuit 310, a switch T1b, a first lower The pull-down circuit 330 , the second pull-down circuit 340 and the third pull-down circuit 350 . The first input terminal IN1, the second input terminal IN2, the third input terminal IN3 and the fourth input terminal IN4 respectively receive different clock signals CK_4, CK1, CK_2 and CK3, and the signal terminal IN is used to receive the previous stage shift The input signal G _N-1 outputted from the output terminal of the register.

The pull-up circuit 310 is coupled to the signal terminal IN, the node _QN and the first input terminal IN1, and is used for controlling the electrical connection between the signal terminal IN and the node _QN according to the potential of the first input terminal IN1. The switch T1b is coupled to the second input terminal IN2, the node Q _N and the output terminal Out, and is used for controlling the electrical connection between the second input terminal IN2 and the output terminal Out according to the potential of the node Q _N. The first pull-down circuit 330 is coupled to the third input terminal IN3, the output terminal Out and the fourth input terminal IN4, and is used to control the voltage between the output terminal Out and the fourth input terminal IN4 according to the potential of the third input terminal IN3. sexual connection. The second pull _- down circuit 340 is coupled to the node QN, the first input terminal IN1, and the fourth input terminal IN4, and is used to control the electrical property between the node _QN and the first input terminal IN1 according to the potential of the fourth input terminal IN4. connect. The third pull _- down circuit 350 is coupled to the node QN, the third input terminal IN3 and the fourth input terminal IN4, and is used to control the electrical property between the node _QN and the fourth input terminal IN4 according to the potential of the third input terminal IN3 connect. The first input terminal IN1 , the second input terminal IN2 , the third input terminal IN3 and the fourth input terminal IN4 respectively receive different clock signals CK_4 , CK1 , CK_2 and CK3 .

In an embodiment of the present invention, the pull-up circuit 310 includes a switch T1a, wherein the first terminal of the switch T1a is coupled to the signal terminal IN, the second terminal of the switch T1a is coupled to the node Q _N , and the control terminal of the switch T1a is coupled to connected to the first input terminal IN1. The switch T1 a controls the electrical connection between the signal terminal IN and the node Q _N according to the clock signal CK_4 . Moreover, the first pull-down circuit 330 may include a capacitor C1 and a switch T1d, wherein the capacitor C1 is coupled between the node Q _N and the output terminal Out. A first terminal of the switch T1d is coupled to the output terminal Out, a second terminal of the switch T1d is coupled to the fourth input terminal IN4, and a control terminal of the switch T1d is coupled to the third input terminal IN3. The switch T1d controls the electrical connection between the output terminal Out and the fourth input terminal IN4 according to the clock signal CK_2. In addition, the second pull-down circuit 340 includes a switch T1e, wherein the first terminal of the switch T1e is coupled to the node Q _N , the second terminal of the switch T1e is coupled to the first input terminal IN1, and the control terminal of the switch T1e is coupled to the first input terminal IN1. Four input terminal IN4. The switch T1e controls the electrical connection between the node Q _N and the first input terminal IN1 according to the clock signal CK3. In addition, the third pull-down circuit 350 may include a capacitor C2 and a switch T1c, wherein the capacitor C2 is coupled between the node Q _N and the third input terminal IN3. A first terminal of the switch T1c is coupled to the node Q _N , a second terminal of the switch T1c is coupled to the fourth timing input IN4 , and a control terminal of the switch T1c is coupled to the third input IN3 . T1c controls the electrical connection between the node Q _N and the fourth input terminal IN4 according to the clock signal CK_2 . Since the switches T1c and T1d use the clock signal CK3 as their low-level signal, and the switch T1e uses the clock signal CK_4 as its low-level signal, the switches T1c, T1d and T1e may be forward-biased due to long-time operation. Under the influence of the positive bias stress (PBS) effect, the periodic negative bias stress (negative bias stress; NBS) effect is applied to the switches T1c, T1d and T1e, so the critical voltage of the switches T1c, T1d and T1e will be There is a recovery effect, and thus the driving capabilities of the switches T1c, T1d and T1e can be improved.

The shift register 300 can be used for the gate driver of the display panel, and the gate drive circuit can include a multi-stage shift register 300 for providing multiple gate signals to control the on and off of the pixels of the display panel. closure. Please refer to Figure 4 and Figure 5. FIG. 4 is a schematic diagram of a shift register circuit 400 according to an embodiment of the present invention, and FIG. 5 is a timing diagram of the shift register circuit 400 in FIG. 4 . The shift register circuit 400 includes a plurality of shift registers (such as 300_1 to 300_5 ). Wherein, the circuit structure of each shift register 300_1 to 300_5 is the same as the circuit structure of the shift register 300 in FIG. 3 . The shift registers 300_1 to _{300_5} respectively output the output signals _G1 to G5 to the corresponding gate lines (or scan lines) through the output terminals Out, so as to sequentially turn on the coupling with different gate lines of the display panel. connected pixels. The signal terminals IN of the shift registers 300_2 to 300_5 respectively receive the output signals G ₁ to G ₄ of the previous stage shift registers 300_1 to 300_4 , while the signal terminal IN of the shift register 300_1 receives Start signal SP. In addition, the first input terminal IN1, the second input terminal IN2, the third input terminal IN3 and the fourth input terminal IN4 of the shift register 300_1 and the shift register 300_5 respectively receive the clock signals CK_4, CK1, CK_2 and CK3; the first input terminal IN1, the second input terminal IN2, the third input terminal IN3 and the fourth input terminal IN4 of the shift register 300_2 respectively receive the clock signals CK_1, CK2, CK_3 and CK4; the shift register The first input terminal IN1, the second input terminal IN2, the third input terminal IN3 and the fourth input terminal IN4 of 300_3 respectively receive clock signals CK_2, CK3, CK_4 and CK1; and the first input terminal of the shift register 300_4 IN1 , the second input terminal IN2 , the third input terminal IN3 and the fourth input terminal IN4 respectively receive clock signals CK_3 , CK4 , CK_1 and CK2 . Among them, the potentials of the clock signals CK1, CK2, CK3 and CK4 will be switched between the gate high potential VGH and the first gate low potential VGL1, and the potentials of the clock signals CK_1, CK_2, CK_3 and CK_4 will be at the gate high potential Switch between VGH and the second low gate potential VGL2, and the second low gate potential VGL2 is lower than the first low gate potential VGL1. In one embodiment of the present invention, the high gate potential VGH is plus 20 volts, the first low gate potential VGL1 is minus 10 volts, and the second gate low potential VGL2 is minus 13 volts, but the present invention is not based on this limit.

In addition, each of the clock signals CK1 to CK4 will be raised from the first gate low potential VGL1 to the gate high potential VGH every other period T _P , and each of the clock signals CK_1 to CK_4 will be raised to the gate high potential VGH every other period T _P The second gate low potential VGL2 is raised to the gate high potential VGH. The clock signals CK1 and CK_1 have similar timings, the clock signals CK2 and CK_2 have similar timings, the clock signals CK3 and CK_3 have similar timings, and the clock signals CK4 and CK_4 have similar timings. In detail, the time point when the clock signal CK1 is raised from the first low gate potential VGL1 to the high gate potential VGH and the time point when the clock signal CK1 is lowered from the high gate potential VGH to the first low gate potential VGL1 are related to The time point when the clock signal CK_1 is raised from the second low gate potential VGL2 to the high gate potential VGH and the time point when the clock signal CK_1 is lowered from the second low gate potential VGL2 to the second low gate potential VGH are consistent. Similarly, the time point when the clock signal CK2 is raised from the first low gate potential VGL1 to the high gate potential VGH and the time point when the clock signal CK2 is lowered from the high gate potential VGH to the first low gate potential VGL1 will be different from the timing. The time point when the pulse signal CK_2 is raised from the second low gate potential VGL2 to the high gate potential VGH and the time point when the pulse signal CK_2 is lowered from the second low gate potential VGL2 to the second low gate potential VGL2 are consistent. The time point when the clock signal CK3 is raised from the first gate low potential VGL1 to the gate high potential VGH and the time point when the gate high potential VGH is lowered to the first gate low potential VGL1 will be consistent with the clock signal CK_3 The time point when the second gate low potential VGL2 is raised to the gate high potential VGH is the same as the time point when the gate high potential VGH is lowered to the second gate low potential VGL2 . The time point when the clock signal CK4 is raised from the first gate low potential VGL1 to the gate high potential VGH and the time point when the gate high potential VGH is lowered to the first gate low potential VGL1 will be consistent with the clock signal CK_4 The time point when the second gate low potential VGL2 is raised to the gate high potential VGH is the same as the time point when the gate high potential VGH is lowered to the second gate low potential VGL2 .

Moreover, the clock signals CK1 to CK4 are not at the gate high potential VGH at the same time, and the clock signals CK1 to CK4 are not at the gate high potential VGH at the same time. Taking FIG. 5 as an example, the clock signals CK4, CK1, CK2 and CK3 are sequentially at the gate high potential VGH during the period T1, T3, T5 and T7 respectively, and the clock signals CK_4, CK_1, CK_2 and CK_3 are respectively in the period T1, T3, T5 and T7 are sequentially at the gate high potential VGH.

In addition, since the shift register circuit 400 operates according to eight clock signals CK1 to CK4 and CK_1 to CK_4 , the shift register circuit 400 can be called an eight phase shift register circuit. The clock signals received by the four input terminals IN1 to IN4 of the Nth shift register of the shift register circuit 400 will be connected with the four input terminals IN1 of the (N+4)th shift register. The clock signals received by IN4 are the same, where N is a positive integer. For example, the first input terminal IN1, the second input terminal IN2, the third input terminal IN3 and the fourth input terminal IN4 of the first shift register 300_1 respectively receive clock signals CK_4, CK1, CK_2 and CK3, and The clock signals received by the first input terminal IN1, the second input terminal IN2, the third input terminal IN3 and the fourth input terminal IN4 of the fifth shift register 300_5 will also be the clock signals CK_4, CK1, CK_2 and CK3.

In order to clearly illustrate the features and advantages of the shift register 300, please refer to FIG. 3 and FIG. 5 again. During the period T1, the input signal G _N-1 and the clock signal CK_4 received by the shift register 300 are at the gate high potential VGH, so that the switch T1a of the pull-up circuit 310 is turned on, and causes the node Q _N to The potential is the gate high potential VGH. In addition, because the clock signals CK3 and CK_2 are at the first low gate potential VGL1 and the second gate low potential VGL2 respectively, and the clock signal CK_4 is at the gate high potential VGH, the switches T1e, T1c and T1d are turned off. In addition, since the clock signal CK1 is at the first gate low potential VGL1 and the switch T1b is turned on, the potential of the output signal G _N will be the first gate low potential VGL1. In addition, since the clock signal CK3 is at the first gate low potential VGL1 and the clock signal CK_4 is at the gate high potential VGH, the voltage difference between the gate and the source of the switch T1e will be a very large negative value, As a result, the switch T1e will be tightly closed.

During the period T2, the input signal G _N-1 and the clock signal CK_4 received by the shift register 300 are the first gate low potential VGL1 and the second gate low potential VGL2 respectively, so that the pull-up circuit 310 Switch T1a is closed. In addition, because the clock signals CK3 and CK_2 are at the first low gate potential VGL1 and the second low gate potential VGL2 respectively, the switches T1e, T1c and T1d are turned off. Therefore, the potential of the node Q _N is maintained at the gate high potential VGH because the node Q _N is in a floating state. In addition, because the potential of the clock signal CK1 is still at the first low gate potential _VGL1 , the potential of the output signal GN will remain at the first low gate potential VGL1.

During the period T3, the input signal G _N-1 and the clock signal CK_4 received by the shift register 300 are the first gate low potential VGL1 and the second gate low potential VGL2 respectively, so that the pull-up circuit 310 Switch T1a is closed. In addition, because the clock signal CK_2 is at the second low gate potential VGL2, the switches T1c and T1d are turned off. Moreover, because the clock signal CK1 is at the high gate potential VGH, and the switch _T1b is turned on, the potential of the output signal GN is raised to the high gate potential VGH. In addition, the potential of the node Q _N is raised to twice the gate high potential VGH (ie 2VGH) due to the coupling effect of the parasitic capacitance of the switch T1b and the coupling effect of the capacitor C1. In addition, since the clock signal CK3 is at the first low gate potential VGL1, and the clock signal CK_4 is at the second gate low potential VGL2, the voltage difference between the gate and the source of the switch T1e will be a positive value (approximately 3 volts), and because the potential of the node Q _N is 2VGH, the switch T1e is slightly turned on, and a current flows from the node Q _N to the first input terminal IN1 through the switch T1e.

During the period T4, the input signal G _N-1 and the clock signal CK_4 received by the shift register 300 are the first gate low potential VGL1 and the second gate low potential VGL2 respectively, so that the pull-up circuit 310 Switch T1a is closed. In addition, because the potential of the clock signal CK_2 is the second gate low potential VGL2, the switches T1c and T1d are turned off. In addition, because the clock signal CK1 is pulled down to the first low gate potential VGL1, the potential of the node Q _N is pulled down from twice the gate high potential 2VGH to the gate high potential due to the coupling effect of the parasitic capacitance of the switch T1b VGH. Moreover, because the clock signal CK1 is at the first gate low potential VGL1, and the potential of the node Q _N is at the gate high potential VGH, the switch T1b is turned on, so that the potential of the output signal G _N is pulled down to the first gate potential. Gate low potential VGL1. In addition, since the clock signal CK3 is at the first low gate potential VGL1, and the clock signal CK_4 is at the second gate low potential VGL2, the voltage difference between the gate and the source of the switch T1e will be a positive value (approximately 3 volts), and because the potential of the node QN is VGH, the switch _T1e is slightly turned on, and a current flows from the node QN to the first input terminal IN1 through the switch _T1e .

During the period T5, the input signal G _N-1 and the clock signal CK_4 received by the shift register 300 are the first gate low potential VGL1 and the second gate low potential VGL2 respectively, so that the pull-up circuit 310 Switch T1a is closed. In addition, because the potential of the clock signal CK_2 is the gate high potential VGH, the switches T1c and T1d are turned on, and the potential of the node Q _N is pulled down to the first gate low potential VGL1, and the output signal G _N The potential is maintained at the first gate low potential VGL1. Moreover, because the potential of the node Q _N is the first gate low potential VGL1, the switch T1b is turned off. In addition, since the clock signal CK3 is at the first low gate potential VGL1, and the clock signal CK_4 is at the second gate low potential VGL2, the voltage difference between the gate and the source of the switch T1e will be a positive value (approximately 3 volts), so the switch T1e will be turned on slightly. And because the potential of the node Q _N is that the first gate low potential VGL1 is higher than the second gate low potential VGL2 of the first input terminal IN1, a very slight current flows from the node Q _N through the switch T1e to the first input terminal IN1. Terminal IN1.

During the period T6, the input signal G _N-1 and the clock signal CK_4 received by the shift register 300 are the first gate low potential VGL1 and the second gate low potential VGL2 respectively, so that the pull-up circuit 310 Switch T1a is closed. In addition, because the potential of the clock signal CK_2 is the second gate low potential VGL2, the switches T1c and T1d are turned off. In addition, since the potential of the clock signal CK_2 is pulled down from the high gate potential VGH to the second low gate potential VGL2 , the potential of the node Q _N will drop slightly due to the coupling effect of the capacitor C2 . The switch T1b is turned off because the potential of the node Q _N is lower than the first low gate potential VGL1, and the potential of the output signal G _N remains at the first low gate potential VGL1. In addition, since the clock signal CK3 is at the first low gate potential VGL1, and the clock signal CK_4 is at the second gate low potential VGL2, the voltage difference between the gate and the source of the switch T1e will be a positive value (approximately 3 volts), so that the switch T1e will be slightly turned on.

During the period T7, the input signal G _N-1 and the clock signal CK_4 received by the shift register 300 are the first gate low potential VGL1 and the second gate low potential VGL2 respectively, so that the pull-up circuit 310 Switch T1a is closed. In addition, because the clock signal CK_2 is at the second low gate potential VGL2, the switches T1c and T1d are turned off. Moreover, because the clock signal CK3 is at the high gate potential VGH, the switch _T1e is fully turned on, so that the potential of the node QN is pulled down to the second low gate potential VGL2. The potential of the output signal GN is still maintained at the first gate low potential _VGL1 . In addition, the waveform of the potential of the node Q _N+1 and the waveform of the output signal G _N+1 of the shift register in the latter stage are similar to the waveform of the potential of the node Q _N and the waveform of the output signal G _N respectively. That is to say no more.

It can be known from the above description that the switch T1e in the shift register 300 is slightly turned on during the period T3 to T6, and is fully turned on during the period T7. Therefore, before the input signal G _N-1 outputted from the output terminal of the previous stage shift register is pulled up from the first gate low potential VGL1 to the gate high potential VGH again, although the clock signal CK1 It will still switch between the gate high potential VGH and the first gate low potential VGL1, but due to the effect of the switch T1e, the surge at the node Q _N of the shift register 300 can be effectively avoided, so it can It is ensured that the shift register 300 can output the output signal G _N with the correct waveform.

In an embodiment of the present invention, the third pull-down circuit 350 of the shift register 300 can be omitted, and the control terminal of the switch T1e of the second pull-down circuit 340 is changed to receive the clock signal CK2. Please refer to FIG. 6 , which is a circuit diagram of a shift register 500 according to another embodiment of the present invention. The shift register 500 includes a signal terminal IN, a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, a fourth input terminal IN4, a fifth input terminal IN5, an output terminal Out, a pull-up circuit 310, The switch T1b, the first pull-down circuit 330 and the second pull-down circuit 540 . The first input terminal IN1, the second input terminal IN2, the third input terminal IN3, the fourth input terminal IN4 and the fifth input terminal IN5 respectively receive different clock signals CK_4, CK1, CK_2, CK3 and CK2, and the signal terminal IN It is used for receiving the input signal G _N-1 outputted from the output terminal of the previous stage shift register.

The functions and operation modes of the pull-up circuit 310, the switch T1b and the first pull-down circuit 330 of the shift register 500 are the same as those of the pull-up circuit 310, the switch T1b and the first pull-down circuit 330 of the shift register 300, So no more details. In addition, the second pull-down circuit 540 of the shift register 500 is coupled to the node _QN , the first input terminal IN1 and the fifth input terminal IN5, and is used to control the node _QN and the fifth input terminal IN5 according to the potential of the fifth input terminal IN5. An electrical connection between the input terminals IN1. In an embodiment of the invention, the second pull-down circuit 540 includes a switch T1e. A first terminal of the switch T1e is coupled to the node Q _N , a second terminal of the switch T1e is coupled to the first input terminal IN1 , and a control terminal of the switch T1e is coupled to the fifth input terminal IN5 . The switch _T1e controls the electrical connection between the node QN and the first input terminal IN1 according to the clock signal CK2. Since the switches T1d and T1e respectively use the clock signals CK3 and CK_4 as their low-level signals, the switches T1d and T1e can be controlled under the influence of the positive bias stress (PBS) effect due to the long-time operation of the switches T1d and T1e. T1e exerts a periodic reverse bias stress (NBS) effect, so the threshold voltages of the switches T1d and T1e have a recovery effect, and thus the driving capabilities of the switches T1d and T1e can be improved.

The shift register 500 can be used for the gate driver of the display panel, and the gate drive circuit can include a multi-stage shift register 500 for providing multiple gate signals to control the opening and closing of the pixels of the display panel. closure. Please refer to Figure 7 and Figure 5. FIG. 7 is a schematic diagram of a shift register circuit 700 according to an embodiment of the present invention. The shift register circuit 700 includes a plurality of shift registers (such as 500_1 to 500_5 ). Wherein, the circuit structure of each shift register 500_1 to 500_5 is the same as the circuit structure of the shift register 500 in FIG. 6 . The shift registers 500_1 to _{500_5} respectively output the output signals _G1 to G5 to the corresponding gate lines (or scan lines) through the output terminals Out, so as to sequentially turn on the coupling with different gate lines of the display panel. connected pixels. The signal terminals IN of the shift registers 500_2 to 500_5 respectively receive the output signals G ₁ to G ₄ of the preceding shift registers 500_1 to 500_4 , while the signal terminals IN of the shift register 500_1 receive Start signal SP. In addition, the first input terminal IN1, the second input terminal IN2, the third input terminal IN3, the fourth input terminal IN4 and the fifth input terminal IN5 of the shift register 500_1 and the shift register 500_5 respectively receive the clock signal CK_4, CK1, CK_2, CK3, and CK2. The first input terminal IN1, the second input terminal IN2, the third input terminal IN3, the fourth input terminal IN4 and the fifth input terminal IN5 of the shift register 500_2 respectively receive clock signals CK_1, CK2, CK_3, CK4 and CK3 . The first input terminal IN1, the second input terminal IN2, the third input terminal IN3, the fourth input terminal IN4 and the fifth input terminal IN5 of the shift register 500_3 respectively receive clock signals CK_2, CK3, CK_4, CK1 and CK4 . The first input terminal IN1, the second input terminal IN2, the third input terminal IN3, the fourth input terminal IN4 and the fifth input terminal IN5 of the shift register 500_4 respectively receive clock signals CK_3, CK4, CK_1, CK2 and CK1 .

Since the shift register circuit 700 operates according to eight clock signals CK1 to CK4 and CK_1 to CK_4 , the shift register circuit 700 is also an eight-phase shift register circuit. The clock signals received by the five input terminals IN1 to IN5 of the Nth shift register of the shift register circuit 700 will be connected with the five input terminals IN1 of the (N+4)th shift register. The clock signal received by IN5 is the same, where N is a positive integer. For example, the first input terminal IN1, the second input terminal IN2, the third input terminal IN3, the fourth input terminal IN4 and the fifth input terminal IN5 of the first shift register 500_1 respectively receive clock signals CK_4, CK1, CK_2, CK3 and CK2, and the time received by the first input terminal IN1, the second input terminal IN2, the third input terminal IN3, the fourth input terminal IN4 and the fifth input terminal IN5 of the fifth shift register 500_5 The pulse signals are also clock signals CK_4 , CK1 , CK_2 , CK3 and CK2 .

Please refer to FIG. 6 and FIG. 5 again. During the period T1, the input signal G _N-1 and the clock signal CK_4 received by the shift register 500 are at the gate high potential VGH, so that the switch T1a of the pull-up circuit 310 is turned on, and the node Q _N is turned on. The potential is the gate high potential VGH. In addition, because the clock signals CK3 and CK_2 are at the first low gate potential VGL1 and the second low gate potential VGL2 respectively, the switch T1d is turned off. Furthermore, since the clock signal CK_4 is at the high gate potential VGH, and the clock signal CK2 is at the first low gate potential VGL1, the voltage difference between the gate and the source of the switch T1e will be extremely large. Negative value, so that switch T1e will be closed tightly. In addition, since the clock signal CK1 is at the first gate low potential VGL1 and the switch T1b is turned on, the potential of the output signal G _N will be the first gate low potential VGL1.

During the period T2, the input signal G _N-1 and the clock signal CK_4 received by the shift register 500 are the first gate low potential VGL1 and the second gate low potential VGL2 respectively, so that the pull-up circuit 310 Switch T1a is closed. In addition, because the clock signals CK3 and CK_2 are at the first low gate potential VGL1 and the second low gate potential VGL2 respectively, the switch T1d is turned off. Moreover, because the potential of the clock signal CK2 is the first gate low potential VGL1, the switch T1e is turned off. Therefore, the potential of the node Q _N is maintained at the gate high potential VGH because the node Q _N is in a floating state. In addition, because the potential of the clock signal CK1 is still at the first low gate potential _VGL1 , the potential of the output signal GN will remain at the first low gate potential VGL1.

During the period T3, the input signal G _N-1 and the clock signal CK_4 received by the shift register 500 are the first gate low potential VGL1 and the second gate low potential VGL2 respectively, so that the pull-up circuit 310 Switch T1a is closed. In addition, because the clock signal CK_2 is at the second low gate potential VGL2, the switch T1d is turned off. Moreover, because the clock signal CK1 is at the high gate potential VGH, and the switch _T1b is turned on, the potential of the output signal GN is raised to the high gate potential VGH. In addition, the potential of the node Q _N is raised to twice the gate high potential VGH (ie 2VGH) due to the coupling effect of the parasitic capacitance of the switch T1b and the coupling effect of the capacitor C1. In addition, because the clock signal CK2 is at the first low gate potential VGL1, and the clock signal CK_4 is at the second gate low potential VGL2, the voltage difference between the gate and the source of the switch T1e will be positive (approximately 3 volts), and because the potential of the node Q _N is 2VGH, the switch T1e is slightly turned on, and a current flows from the node Q _N to the first input terminal IN1 through the switch T1e.

During the period T4, the input signal G _N-1 and the clock signal CK_4 received by the shift register 500 are the first gate low potential VGL1 and the second gate low potential VGL2 respectively, so that the pull-up circuit 310 Switch T1a is closed. In addition, because the potential of the clock signal CK_2 is the second gate low potential VGL2 , the switch T1d is turned off. In addition, because the clock signal CK1 is pulled down to the first low gate potential VGL1, the potential of the node Q _N is pulled down from twice the gate high potential 2VGH to the gate high potential due to the coupling effect of the parasitic capacitance of the switch T1b VGH. Moreover, because the clock signal CK1 is at the first gate low potential VGL1, and the potential of the node Q _N is at the gate high potential VGH, the switch T1b is turned on, so that the potential of the output signal G _N is pulled down to the first gate potential. Gate low potential VGL1. In addition, because the clock signal CK2 is at the first low gate potential VGL1, and the clock signal CK_4 is at the second gate low potential VGL2, the voltage difference between the gate and the source of the switch T1e will be a positive value (approximately 3 volts), and because the potential of the node QN is VGH, the switch _T1e is slightly turned on, and a current flows from the node QN to the first input terminal IN1 through the switch _T1e .

During the period T5, the input signal G _N-1 and the clock signal CK_4 received by the shift register 500 are the first gate low potential VGL1 and the second gate low potential VGL2 respectively, so that the pull-up circuit 310 Switch T1a is closed. In addition, because the potentials of the clock signals CK and CK_2 are at the gate high potential VGH, the switches T1d and _T1e are turned on, and the potential of the node QN is pulled down to the second gate low potential VGL2, and the output signal G The potential of _N is maintained around the low potential VGL1 of the first gate. Moreover, because the potential of the node Q _N is the second gate low potential VGL2, the switch T1b is turned off.

During the period T6, the input signal G _N-1 and the clock signal CK_4 received by the shift register 500 are the first gate low potential VGL1 and the second gate low potential VGL2 respectively, so that the pull-up circuit 310 Switch T1a is closed. In addition, because the potential of the clock signal CK_2 is the second gate low potential VGL2 , the switch T1d is turned off. In addition, since the clock signal CK2 is at the first low gate potential VGL1, and the clock signal CK_4 is at the second gate low potential VGL2, the voltage difference between the gate and the source of the switch T1e will be a positive value (approximately 3 volts), so that the switch T1e is slightly turned on, so that the potential of the node Q _N is maintained at the second low gate potential VGL2, and the potential of the output signal G _N is maintained near the first low gate potential VGL1.

During the period T7, the input signal G _N-1 and the clock signal CK_4 received by the shift register 500 are the first gate low potential VGL1 and the second gate low potential VGL2 respectively, so that the pull-up circuit 310 Switch T1a is closed. In addition, because the clock signal CK_2 is at the second low gate potential VGL2, the switch T1d is turned off. Moreover, since the clock signal CK2 is at the first low gate potential VGL1, and the clock signal CK_4 is at the second gate low potential VGL2, the voltage difference between the gate and the source of the switch T1e will be a positive value ( about 3 volts), so that the switch T1e is slightly turned on, so that the potential of the node Q _N is maintained at the second low gate potential VGL2, and the potential of the output signal G _N is maintained near the first low gate potential VGL1. In addition, the waveform of the potential of the node Q _N+1 and the waveform of the output signal G _N+1 of the shift register in the latter stage are similar to the waveform of the potential of the node Q _N and the waveform of the output signal G _N respectively. That is to say no more.

It can be known from the above description that the switch T1e in the shift register 500 is slightly turned on during the periods T3, T4, T6 and T7, and is fully turned on during the period T5. Therefore, before the input signal G _N-1 outputted from the output terminal of the previous stage shift register is pulled up from the first gate low potential VGL1 to the gate high potential VGH again, although the clock signal CK1 It will still switch between the gate high potential VGH and the first gate low potential VGL1, but due to the effect of the switch T1e, the surge at the node Q _N of the shift register 500 can be effectively avoided, so it can It is ensured that the shift register 500 can output the output signal G _N with the correct waveform.

In addition, in the above description, the clock signals CK1, CK_1, CK2, CK_2, CK3, CK_3, CK4, and CK_4 may also be referred to as the second clock signal, the sixth clock signal, the fifth clock signal, the third clock signal, respectively. The clock signal, the fourth clock signal, the seventh clock signal, the eighth clock signal and the first clock signal. The shift registers 300_1 and 500_1 can also be referred to as a first shift register. The shift registers 300_2 and 500_2 can also be referred to as second shift registers. The shift registers 300_3 and 500_3 can also be called the third shift register. The shift registers 300_4 and 500_4 can also be called the fourth shift register. The capacitor C1 can also be called a first capacitor, and the capacitor C2 can also be called a second capacitor. The switches T1b, T1c, and T1d may also be referred to as a first switch, a third switch, and a second switch, respectively. In addition, the time periods T1 , T3 , T5 and T7 may also be referred to as a first time period, a second time period, a third time period and a fourth time period, respectively. In addition, G _N+1 in the figure refers to the "input signal" of the shift register 100 in the prior art, but in the embodiment of the present invention refers to the "output signal" of the subsequent stage shift register. signal", to be explained.

In summary, through the shift register of the embodiment of the present invention, since the switches of each pull-down circuit use the clock signal as its low-level signal, it is possible to prevent the switches of each pull-down circuit from being damaged due to long-term operation. Under the influence of the positive bias stress (PBS) effect, a periodic reverse bias stress (NBS) effect is applied to the switch of the pull-down circuit to restore the threshold voltage (Vth) and improve the problem of reduced driving capability. In addition, the switch of the second pull-down circuit can be slightly turned on or fully turned on in time, so that the surge generated at the control terminal of the first switch due to the coupling effect of the parasitic capacitance of the first switch can be suppressed.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (13)

1. A shift register, characterized in that, comprising: a signal terminal for receiving an input signal; a first input terminal for receiving a first clock signal; a second input terminal for receiving a second clock signal; a third input terminal for receiving a third clock signal; a fourth input terminal for receiving a fourth clock signal; an output terminal; a pull-up circuit, coupled to the signal terminal and the first input terminal, and used to control the electrical connection between the signal terminal and a node according to the first clock signal; a first switch, coupled to the second input terminal, the node and the output terminal, and used to control the electrical connection between the second input terminal and the output terminal according to the potential of the node; A first pull-down circuit, coupled to the third input terminal, the output terminal and the fourth input terminal, and used to control the electric voltage between the output terminal and the fourth input terminal according to the third clock signal sexual connection; and a second pull-down circuit, coupled to the node and the first input terminal, and used to control the electrical connection between the node and the first input terminal according to the fourth clock signal or a fifth clock signal ; The first clock signal, the second clock signal, the third clock signal and the fourth clock signal are respectively in a first time period, a second time period, a third time period and a fourth time period. gate high potential, and the order of the first period, the second period, the third period and the fourth period on the time axis is the first period, the second period, the third period and the In a fourth period, the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are not at the gate high potential at the same time. 2. The shift register according to claim 1, wherein the first pull-down circuit comprises: a first capacitor coupled between the node and the output terminal; and A second switch, a first terminal of the second switch is coupled to the output terminal, a second terminal of the second switch is coupled to the fourth input terminal, and a control terminal of the second switch is coupled to the the third input terminal. 3. The shift register according to claim 1, wherein the second pull-down circuit controls the electrical connection between the node and the first input terminal according to the four clock signals. 4. The shift register according to claim 3, further comprising: A third pull-down circuit is coupled to the node, the third input terminal and the fourth input terminal, and is used for controlling the electrical connection between the node and the fourth input terminal according to the third clock signal. 5. The shift register according to claim 4, wherein the third pull-down circuit comprises: a second capacitor coupled between the node and the third input terminal; and a third switch, a first terminal of the third switch is coupled to the node, a second terminal of the third switch is coupled to the fourth input terminal, and a control terminal of the third switch is coupled to the third input. 6. The shift register according to claim 1, further comprising a fifth input terminal for receiving the five clock signals, wherein the second pull-down circuit is further coupled to the fifth input terminal to control the electrical connection between the node and the first input terminal according to the five clock signal, and the fifth clock signal is the gate high potential during the third period. 7. The shift register according to claim 1 or 6, wherein the second clock signal and the fourth clock signal are between the gate high potential and a first gate low potential switching, the first clock signal and the third clock signal are switched between the gate high potential and a second gate low potential, and the first gate low potential is higher than the second gate low potential . 8. A shift register circuit comprising a plurality of shift registers, characterized in that each shift register comprises: a signal terminal; a first input terminal; a second input terminal; a third input terminal; a fourth input terminal; an output terminal; a pull-up circuit, coupled to the signal terminal, a node and the first input terminal, and used to control the electrical connection between the signal terminal and the node according to the potential of the first input terminal; a first switch, coupled to the second input terminal, the node and the output terminal, and used to control the electrical connection between the second input terminal and the output terminal according to the potential of the node; A first pull-down circuit, coupled to the third input terminal, the output terminal and the fourth input terminal, and used to control the electric potential between the output terminal and the fourth input terminal according to the potential of the third input terminal sexual connection; a second pull-down circuit, coupled to the node, the first input terminal and the fourth input terminal, and used to control the electrical connection between the node and the first input terminal according to the potential of the fourth input terminal; as well as a third pull-down circuit, coupled to the node, the third input terminal and the fourth input terminal, and used to control the electrical connection between the node and the fourth input terminal according to the potential of the third input terminal; Wherein the first input terminal, the second input terminal, the third input terminal and the fourth input terminal respectively receive different clock signals; The shift registers include a first shift register, a second shift register, a third shift register and a fourth shift register; The signal end of the first shift register receives a start signal, the first input end of the first shift register receives a first clock signal, and the first shift register receives a first clock signal. The second input end receives a second clock signal, the third input end of the first shift register receives a third clock signal, and the fourth input end of the first shift register receives a fourth clock signal; Wherein the signal end of the second shift register is coupled to the output end of the first shift register, and the first input end of the second shift register receives a sixth clock signal, The second input end of the second shift register receives a fifth clock signal, the third input end of the second shift register receives a seventh clock signal, and the second shift register The fourth input terminal of the register receives an eighth clock signal; Wherein the signal end of the third shift register is coupled to the output end of the second shift register, the first input end of the third shift register receives the third clock signal, The second input end of the third shift register receives the fourth clock signal, the third input end of the third shift register receives the first clock signal, and the third shift register the fourth input terminal of the register receives the second clock signal; and Wherein the signal end of the fourth shift register is coupled to the output end of the third shift register, and the first input end of the fourth shift register receives the seventh clock signal, The second input end of the fourth shift register receives the eighth clock signal, the third input end of the fourth shift register receives the sixth clock signal, and the fourth shift register The fourth input end of the register receives the fifth clock signal. 9. The shift register circuit according to claim 8, wherein the third pull-down circuit comprises: a second capacitor coupled between the node and the third input terminal; and a third switch, a first terminal of the third switch is coupled to the node, a second terminal of the third switch is coupled to the fourth input terminal, and a control terminal of the third switch is coupled to the third input. 10. A shift register circuit comprising a plurality of shift registers, characterized in that each shift register comprises: a signal terminal; a first input terminal; a second input terminal; a third input terminal; a fourth input terminal; a fifth input terminal; an output terminal; a pull-up circuit, coupled to the signal terminal, a node and the first input terminal, and used to control the electrical connection between the signal terminal and the node according to the potential of the first input terminal; a first switch, coupled to the second input terminal, the node and the output terminal, and used to control the electrical connection between the second input terminal and the output terminal according to the potential of the node; A first pull-down circuit, coupled to the third input terminal, the output terminal and the fourth input terminal, and used to control the electric potential between the output terminal and the fourth input terminal according to the potential of the third input terminal sexual connection; and a second pull-down circuit, coupled to the node, the first input terminal and the fifth input terminal, and used to control the electrical connection between the node and the first input terminal according to the potential of the fifth input terminal; Wherein the first input terminal, the second input terminal, the third input terminal, the fourth input terminal and the fifth input terminal respectively receive different clock signals; The shift registers include a first shift register, a second shift register, a third shift register and a fourth shift register; The signal end of the first shift register receives a start signal, the first input end of the first shift register receives a first clock signal, and the first shift register receives a first clock signal. The second input terminal receives a second clock signal, the third input terminal of the first shift register receives a third clock signal, and the fourth input terminal of the first shift register receives a a fourth clock signal, and the fifth input end of the first shift register receives a fifth clock signal; Wherein the signal end of the second shift register is coupled to the output end of the first shift register, and the first input end of the second shift register receives a sixth clock signal, The second input end of the second shift register receives the fifth clock signal, the third input end of the second shift register receives a seventh clock signal, and the second shift register The fourth input end of the register receives an eighth clock signal, and the fifth input end of the second shift register receives the fourth clock signal; Wherein the signal end of the third shift register is coupled to the output end of the second shift register, the first input end of the third shift register receives the third clock signal, The second input end of the third shift register receives the fourth clock signal, the third input end of the third shift register receives the first clock signal, and the third shift register The fourth input terminal of the register receives the second clock signal, and the fifth input terminal of the third shift register receives the eighth clock signal; and Wherein the signal end of the fourth shift register is coupled to the output end of the third shift register, and the first input end of the fourth shift register receives the seventh clock signal, The second input end of the fourth shift register receives the eighth clock signal, the third input end of the fourth shift register receives the sixth clock signal, and the fourth shift register The fourth input end of the register receives the fifth clock signal, and the fifth input end of the fourth shift register receives the second clock signal. 11. The shift register circuit according to claim 10, wherein the first pull-down circuit comprises: a first capacitor coupled between the node and the output terminal; and A second switch, a first terminal of the second switch is coupled to the output terminal, a second terminal of the second switch is coupled to the fourth input terminal, and a control terminal of the second switch is coupled to the the third input terminal. 12. The shift register circuit according to claim 10, wherein the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are respectively in a first clock signal A period, a second period, a third period and a fourth period are a gate high potential, the eighth clock signal, the sixth clock signal, the fifth clock signal and the seventh clock signal The signal is at the gate high potential during the first period, the second period, the third period and the fourth period, and the first period, the second period, the third period and the fourth period are The sequence on the time axis is the first period, the second period, the third period and the fourth period, the first clock signal, the second clock signal, the third clock signal and the The fourth clock signal is not at the gate high potential at the same time, and the fifth clock signal, the sixth clock signal, the seventh clock signal and the eighth clock signal are not at the gate high potential at the same time. 13. The shift register circuit according to claim 12, wherein the second clock signal, the fourth clock signal, the fifth clock signal and the eighth clock signal are connected to the gate switching between a high potential and a low potential of a first gate, the first clock signal, the third clock signal, the sixth clock signal and the seventh clock signal are at the high potential of the gate and a first gate The low potentials of the two gates are switched, and the low potential of the first gate is higher than the low potential of the second gate.