CN101039155B - Method, apparatus and system for controlling synchronization clock of communication interface - Google Patents
Method, apparatus and system for controlling synchronization clock of communication interface Download PDFInfo
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- CN101039155B CN101039155B CN2007100649089A CN200710064908A CN101039155B CN 101039155 B CN101039155 B CN 101039155B CN 2007100649089 A CN2007100649089 A CN 2007100649089A CN 200710064908 A CN200710064908 A CN 200710064908A CN 101039155 B CN101039155 B CN 101039155B
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Abstract
The invention provides a method for controlling the synchronous clock of the communication interface, comprises as follow: the logical operation result is obtained by using the control signal to control the control signal to do logical operation with the outside clock signal; The logical operation result is inputted into the communication interface and the synchronous clock of the communication interface is opened or closed according to the logical operation result. The invention also provides a device and system based on the method for controlling the synchronous clock of the communication interface. By realizing the technology scheme of the invention, the invention can adopt synchronous design on the communication interface; meanwhile the intention to save the power of the system on which the communication interface is arranged is achieved.
Description
Technical field
The present invention relates to application-specific integrated circuit (ASIC) (ASIC) design field, relate in particular to a kind of method, Apparatus and system of controlling the synchronised clock of communication interface.
Background technology
In the ASIC design, the relative asynchronous design of Synchronization Design has the design of being easy to and revises, and the characteristics little with process relation, Given this, in the ASIC design, pays the utmost attention to usually and adopts Synchronization Design to realize circuit.
Referring to Fig. 1, Fig. 1 is the connection layout of baseband processor and audio process in the mobile terminal system.In system shown in Figure 1, baseband processor is by internal integrated circuit (I
2C) or serial peripheral interface (SPI) bus control audio processor.Owing to have register and digital module in the audio process, therefore, communication interface between baseband processor and the audio process often adopts Synchronization Design, so that the work that utilizes synchronised clock to come control register and digital module, but therefore system power dissipation also can increase.
System power dissipation is from two aspects: the one, and quiescent dissipation, another is a dynamic power consumption.Because quiescent dissipation is less relatively, so system power dissipation is mainly from dynamic power consumption, and dynamic power consumption is directly proportional with the frequency of clock in the system.The frequency that is to say clock is low more, and then system power dissipation is few more; In other words, if do not use clock in the system, system power dissipation will be very little so.
For reducing system power dissipation, prior art makes improvements above-mentioned Design of Communication Interface, employing can not need to come by clock the asynchronous design of control register and digital module, by the design delay time signal, simulation control register or digital control register such as are read and write at operation, therefore, can save the power consumption of audio process.But known, the relative Synchronization Design of asynchronous design, design difficulty is big.Because asynchronous design is not used clock, therefore when realizing circuit, adopt combinational logic circuit usually, utilize the operations such as read-write of gate delay control data, and the design of gate delay is loaded down with trivial details.If the employing Synchronization Design can utilize trigger to come the read-write operation of control data so, and is simple.And asynchronous design is subjected to technogenic influence bigger, and stability is relatively poor relatively; Whether the sequential that the circuit of realizing by asynchronous design is difficult to adopt electric design automation (EDA) instrument to detect asynchronous design meets design requirement.
Summary of the invention
The invention provides a kind of method of controlling the synchronised clock of communication interface, described communication interface is to adopt the communication interface of Synchronization Design between the baseband processor of portable terminal and the audio process, and this method comprises:
Utilize control signal, control described control signal and external timing signal and carry out the resulting logic operation result of logical operation; Wherein, when needing configuration register and/or digital module to need work in the audio process, controlling described logic operation result is described external timing signal; When not needing configuration register and digital module not to need work in the audio process, controlling described logic operation result is described control signal;
Described logic operation result is imported described communication interface, when described logic operation result is described external timing signal, realization is enabled the synchronised clock of described communication interface, when described logic operation result is described control signal, realize closing to the synchronised clock of described communication interface.
Described logical operation is or logical operation;
Utilize control signal, control described control signal and external timing signal and carry out the resulting logic operation result of logical operation and comprise:
Described control signal is set to low level signal, described external timing signal and described control signal carry out or logical operation after, the logic operation result that obtains is an external timing signal;
Described control signal is set to high level signal, described external timing signal and described control signal carry out or logical operation after, the logic operation result that obtains is a control signal.
Described logical operation is and logical operation;
Utilize control signal, control described control signal and external timing signal and carry out the resulting logic operation result of logical operation and comprise:
Described control signal is set to high level signal, described external timing signal and described control signal carry out with logical operation after, the logic operation result that obtains is an external timing signal;
Described control signal is set to low level signal, described external timing signal and described control signal carry out with logical operation after, the logic operation result that obtains is a control signal.
Preferably, described control signal is produced by the baseband processor of portable terminal.
The invention provides a kind of device of controlling the synchronised clock of communication interface, described communication interface is to adopt the communication interface of Synchronization Design between the baseband processor of portable terminal and the audio process, and this device comprises:
Control signal generating unit, clock signal generation unit, arithmetic logic unit and communication interface;
Control signal generating unit is used to produce control signal, and described control signal is transferred to arithmetic logic unit;
The clock signal generation unit is used to produce external timing signal, and described external timing signal is transferred to arithmetic logic unit;
Arithmetic logic unit, be used for and carry out logical operation from the control signal of described control signal generating unit with from the external timing signal of described clock signal generation unit, when needing configuration register and/or digital module to need work in the audio process, the control logic operation result is described external timing signal, when not needing configuration register and digital module not to need work in the audio process, controlling described logic operation result is described control signal; And, logic operation result is transferred to described communication interface, when described logic operation result is described external timing signal, realization is enabled the synchronised clock of described communication interface, when described logic operation result is described control signal, realize closing to the synchronised clock of described communication interface.
Preferably, described arithmetic logic unit is: or arithmetic logic unit; Perhaps, with arithmetic logic unit.
The invention provides a kind of system that controls the synchronised clock of communication interface, comprise: the device of the synchronised clock of the baseband processor of portable terminal, control communication interface and the audio process of portable terminal, and described communication interface is to adopt the communication interface of Synchronization Design between the baseband processor of portable terminal and the audio process;
Wherein, the device of the synchronised clock of described control communication interface comprises:
Control signal generating unit, clock signal generation unit, arithmetic logic unit and communication interface;
Control signal generating unit is set on the baseband processor, is used to produce control signal, and described control signal is transferred to arithmetic logic unit;
The clock signal generation unit is used to produce external timing signal, and described external timing signal is transferred to arithmetic logic unit;
Arithmetic logic unit, be used for and carry out logical operation from the control signal of described control signal generating unit with from the external timing signal of described clock signal generation unit, when needing configuration register and/or digital module to need work in the audio process, the control logic operation result is described external timing signal, when not needing configuration register and digital module not to need work in the audio process, controlling described logic operation result is described control signal; And, logic operation result is transferred to described communication interface, when described logic operation result is described external timing signal, realization is enabled the synchronised clock of described communication interface, when described logic operation result is described control signal, realize closing to the synchronised clock of described communication interface;
The audio process of portable terminal is used to settle described communication interface.
Preferably, described audio process comprises: analogue device control register, digital device control register, analogue device and digital device.
As seen from the above technical solution, the present invention is by carrying out logical operation with external timing signal and control signal, come the control logic operation result by control signal, and with the synchronizing clock signals input communication interface of logic operation result as communication interface, like this, when needs are enabled the synchronised clock of communication interface, utilize suitable control signal, and, select external timing signal by carrying out logical operation with external timing signal, as the synchronizing clock signals of communication interface; When needing the synchronised clock of communication close interface, utilize suitable control signal to shield external timing signal, its essence promptly is the clock of communication close interface, thereby when communication interface adopts Synchronization Design, reaches the purpose of saving communication interface place system power dissipation.
Description of drawings
Fig. 1 is that communication interface adopts the baseband processor of Synchronization Design and the connection layout of audio process;
Fig. 2 is that communication interface adopts the baseband processor of asynchronous design and the connection layout of audio process;
Fig. 3 is the schematic diagram that the present invention is based on the synchronised clock of the control communication interface that above-mentioned Fig. 2 provides;
Fig. 4 is the method flow diagram of the synchronised clock of control communication interface in the preferred embodiment of the present invention;
Fig. 5 is the apparatus structure schematic diagram of the synchronised clock of control communication interface in the preferred embodiment of the present invention;
Fig. 6 is the system configuration schematic diagram of the synchronised clock of control communication interface in the preferred embodiment of the present invention.
Embodiment
For making technical solution of the present invention and advantage clearer, below in conjunction with the accompanying drawings and the specific embodiments the present invention is described in further detail.
In view of the various advantages of Synchronization Design, in the technical scheme that the present invention proposes, still consider the communication interface between baseband processor and the audio process is adopted the Synchronization Design of using clock.Inventor of the present invention further considers, in audio process, both there had been digital module and digital module control register, there are analogue device and analogue device control register again, usually, analogue device need be worked with digital module, but in the practical application, the normal existence needs analogue device work, and the idle situation of digital module, and, because the configuration effort of the digital module control register of the analogue device control register of control analogue device and control figure module also is temporary transient usually, therefore, do not need work at digital module, and under the situation that does not also need each register is configured, can consider the synchronised clock of communication interface is closed, and need work at digital module, or when needing configuration register, start the clock of communication interface.
In view of situation about existing in the above-mentioned practical application, the present invention is by carrying out logical operation with external timing signal and control signal, come the control logic operation result by control signal, and with the synchronizing clock signals input communication interface of logic operation result as communication interface, with control communication interface synchronised clock unlatching or close, thereby when communication interface adopts Synchronization Design, reduce the power consumption of communication interface place system.
Fig. 3 is the schematic diagram that the present invention is based on the synchronised clock of the control communication interface that above-mentioned Fig. 2 provides.Fig. 4 is the method flow diagram of the synchronised clock of control communication interface in a preferred embodiment of the present invention.Below in conjunction with Fig. 3 and Fig. 4, illustrate that above-mentioned flow process may further comprise the steps:
In the present embodiment, control signal can be produced by baseband processor, and by the GPIO pin of baseband processor this control signal is exported.The GPIO pin is that baseband processor is the device as audio process and so on, and the pin of signal output and input is provided.External timing signal can be produced by crystal oscillator among Fig. 3.
Logical operation can be or logical operation, perhaps with logical operation, by among Fig. 3 or door, perhaps realize respectively with door, so external timing signal and control signal be exactly or, perhaps with two input signals of door.
If logical operation is or logical operation, utilize control signal to control described control signal so and external timing signal carries out logical operation, obtain logic operation result, specifically can be:
Enable when needs under the situation of synchronised clock of communication interface, as, when needing among Fig. 3 to dispose certain register, perhaps when digital module was in running order, baseband processor produced low level signal as control signal.After the external timing signal that crystal oscillator produces and the low level signal process or logical operation as control signal, the logic operation result that obtains is: external timing signal.This moment from Fig. 3 or the signal of door output be exactly the external timing signal that above-mentioned crystal oscillator produces.
Under the situation of the synchronised clock that needs the communication close interface, as, temporarily do not need to dispose each register, and digital module not being when needing work, baseband processor produces high level signal as control signal.After the external timing signal that crystal oscillator produces and the high level signal process or logical operation as control signal, the logic operation result that obtains is: control signal, i.e. high level signal.At this moment, from Fig. 3 or the signal of door output be exactly this high level signal.
If logical operation is and logical operation, utilize control signal to control described control signal so and external timing signal carries out logical operation, obtain logic operation result, specifically can be:
Enable when needs under the situation of synchronised clock of communication interface, as, need certain register of configuration, perhaps when digital module is in running order, baseband processor generation high level signal is as control signal.The external timing signal that crystal oscillator produces with as the high level signal of control signal through with logical operation after, the logic operation result that obtains is: external timing signal.At this moment, the signal of exporting with door from Fig. 3 is exactly the external timing signal that above-mentioned crystal oscillator produces.
Under the situation of the synchronised clock that needs the communication close interface, as, after temporarily not needing to dispose each register configuration and finishing, and digital module is not when needing work, and baseband processor produces low level signal as control signal.The external timing signal that crystal oscillator produces with as the low level signal of control signal through with logical operation after, the logic operation result that obtains is: control signal, i.e. low level signal.At this moment, the signal of exporting with door from Fig. 3 is exactly this low level signal.
In the present embodiment, when the logic operation result that obtains when step 401 is external timing signal, enable the synchronised clock of communication interface; Perhaps, when the logic operation result that obtains when step 401 is control signal, the synchronised clock of communication close interface.That is to say that enable at needs under the situation of synchronised clock of communication interface, the logic operation result that obtains in the step 401 is an external timing signal.In this case, utilize control signal that baseband processor produces and external timing signal to carry out logical operation after, can select external timing signal, and with the synchronizing clock signals of this external timing signal as communication interface.The external timing signal frequency is determined that by crystal oscillator frequency therefore, the frequency of the synchronised clock of communication interface is this crystal oscillator frequency just.
Under the situation of the synchronised clock that needs the communication close interface, carry out logical operation by control signal and the external timing signal that utilizes baseband processor to produce, mask external timing signal, the result who makes the logical operation that obtains is a control signal.And, because control signal is a low level signal or high level signal, no matter and be low level signal or high level signal, all can be regarded as is the one-period infinity, the clock signal that frequency is almost equal to zero.Therefore, will be as the control signal input communication interface of logic operation result, the synchronizing clock signals that makes communication interface its essence is the synchronised clock of having closed communication interface for not having the low level signal or the high level signal of upset, thereby saves the power consumption of communication interface place system.
The present invention also provides a kind of device of controlling the synchronised clock of communication interface based on the method for the synchronised clock of above-mentioned control communication interface.Fig. 5 is the apparatus structure schematic diagram of the synchronised clock of control communication interface in a preferred embodiment of the present invention, and wherein, this device comprises:
Control signal generating unit 501, clock signal generation unit 502, arithmetic logic unit 503 and communication interface 504.
Control signal generating unit 501 is used to produce control signal, and this control signal is transferred to arithmetic logic unit 503.This control signal can be high level signal or low level signal.This control signal generating unit 501 can be the baseband processor of portable terminal shown in Figure 3, and by the GPIO pin on the baseband processor control signal is transferred to arithmetic logic unit 503.
Clock signal generation unit 502 is used to produce external timing signal, and this external timing signal is transferred to arithmetic logic unit 503.This clock signal generation unit 502 can be a crystal oscillator shown in Figure 3, and the frequency of external timing signal is by this crystal oscillator frequency decision.
Above-mentioned arithmetic logic unit 503 can be one or arithmetic logic unit; Perhaps, be one and arithmetic logic unit.In the practical application, the logic operation result of the control signal that control signal generating unit 501 produces and the arithmetic logic unit 503 of selected use is corresponding.
When the arithmetic logic unit 503 that adopts is one or arithmetic logic unit, if the control signal that control signal generating unit 501 produces is a high level signal, the logic operation result of arithmetic logic unit 503 is control signals so, i.e. this high level signal; If the control signal that control signal generating unit 501 produces is a low level signal, the logic operation result of arithmetic logic unit 503 is external timing signals so.
When the arithmetic logic unit 503 that adopts is one during with arithmetic logic unit, if the control signal that control signal generating unit 501 produces is a high level signal, the logic operation result of arithmetic logic unit 503 is external timing signals so; If the control signal that control signal generating unit 501 produces is a low level signal, the logic operation result of arithmetic logic unit 503 is control signals so, i.e. this low level signal.
In the practical application, mate the control signal of control signal generating unit 501 and the arithmetic logic unit 503 that is adopted as required, when needs are enabled the synchronised clock of communication interface, the control signal of utilizing control signal generating unit 501 to produce is selected external timing signal, as the synchronizing clock signals of communication interface; When needing the synchronised clock of communication close interface, the control signal of utilizing control signal generating unit 501 to produce masks external timing signal, with high level or low level control signal synchronizing clock signals as communication interface, the input communication interface promptly is the synchronised clock of communication close interface.
The present invention provides a kind of system that controls the synchronised clock of communication interface also based on said method and device.Fig. 6 is the structural representation of a preferred embodiment of this system, and wherein, this system comprises:
The audio process and the baseband processor of the device of the synchronised clock of above-mentioned control communication interface shown in Figure 5 and portable terminal shown in Figure 3.This audio process is used to settle communication interface in the present embodiment.This communication interface is the interface between above-mentioned baseband processor and this audio process, and control signal generating unit 501 can be arranged on the baseband processor.
In sum, the present invention is by carrying out logical operation with external timing signal and control signal, come the control logic operation result by control signal, and with the synchronizing clock signals input communication interface of logic operation result as communication interface, like this, when needs are enabled the synchronised clock of communication interface, utilize suitable control signal, and, select external timing signal by carrying out logical operation with external timing signal, as the synchronizing clock signals of communication interface; When needing the synchronised clock of communication close interface, utilize suitable control signal to shield external timing signal, its essence promptly is the clock of communication close interface, thereby when communication interface adopts Synchronization Design, reaches the purpose of saving communication interface place system power dissipation.
Claims (8)
1. a method of controlling the synchronised clock of communication interface is characterized in that, described communication interface is to adopt the communication interface of Synchronization Design between the baseband processor of portable terminal and the audio process, and this method comprises:
Utilize control signal, control described control signal and external timing signal and carry out the resulting logic operation result of logical operation; Wherein, when needing configuration register and/or digital module to need work in the audio process, controlling described logic operation result is described external timing signal; When not needing configuration register and digital module not to need work in the audio process, controlling described logic operation result is described control signal;
Described logic operation result is imported described communication interface, when described logic operation result is described external timing signal, realization is enabled the synchronised clock of described communication interface, when described logic operation result is described control signal, realize closing to the synchronised clock of described communication interface.
2. method according to claim 1 is characterized in that described logical operation is or logical operation;
Utilize control signal, control described control signal and external timing signal and carry out the resulting logic operation result of logical operation and comprise:
Described control signal is set to low level signal, described external timing signal and described control signal carry out or logical operation after, the logic operation result that obtains is an external timing signal;
Described control signal is set to high level signal, described external timing signal and described control signal carry out or logical operation after, the logic operation result that obtains is a control signal.
3. method according to claim 1 is characterized in that described logical operation is and logical operation;
Utilize control signal, control described control signal and external timing signal and carry out the resulting logic operation result of logical operation and comprise:
Described control signal is set to high level signal, described external timing signal and described control signal carry out with logical operation after, the logic operation result that obtains is an external timing signal;
Described control signal is set to low level signal, described external timing signal and described control signal carry out with logical operation after, the logic operation result that obtains is a control signal.
4. method according to claim 1 and 2 is characterized in that, described control signal is produced by the baseband processor of portable terminal.
5. a device of controlling the synchronised clock of communication interface is characterized in that, described communication interface is to adopt the communication interface of Synchronization Design between the baseband processor of portable terminal and the audio process, and this device comprises:
Control signal generating unit, clock signal generation unit, arithmetic logic unit and communication interface;
Control signal generating unit is used to produce control signal, and described control signal is transferred to arithmetic logic unit;
The clock signal generation unit is used to produce external timing signal, and described external timing signal is transferred to arithmetic logic unit;
Arithmetic logic unit, be used for and carry out logical operation from the control signal of described control signal generating unit with from the external timing signal of described clock signal generation unit, when needing configuration register and/or digital module to need work in the audio process, the control logic operation result is described external timing signal, when not needing configuration register and digital module not to need work in the audio process, controlling described logic operation result is described control signal; And, logic operation result is transferred to described communication interface, when described logic operation result is described external timing signal, realization is enabled the synchronised clock of described communication interface, when described logic operation result is described control signal, realize closing to the synchronised clock of described communication interface.
6. device according to claim 5 is characterized in that, described arithmetic logic unit is: or arithmetic logic unit; Perhaps, with arithmetic logic unit.
7. system that controls the synchronised clock of communication interface, it is characterized in that, comprise: the device of the synchronised clock of the baseband processor of portable terminal, control communication interface and the audio process of portable terminal, and described communication interface is to adopt the communication interface of Synchronization Design between the baseband processor of portable terminal and the audio process;
Wherein, the device of the synchronised clock of described control communication interface comprises:
Control signal generating unit, clock signal generation unit, arithmetic logic unit and communication interface;
Control signal generating unit is set on the baseband processor, is used to produce control signal, and described control signal is transferred to arithmetic logic unit;
The clock signal generation unit is used to produce external timing signal, and described external timing signal is transferred to arithmetic logic unit;
Arithmetic logic unit, be used for and carry out logical operation from the control signal of described control signal generating unit with from the external timing signal of described clock signal generation unit, when needing configuration register and/or digital module to need work in the audio process, the control logic operation result is described external timing signal, when not needing configuration register and digital module not to need work in the audio process, controlling described logic operation result is described control signal; And, logic operation result is transferred to described communication interface, when described logic operation result is described external timing signal, realization is enabled the synchronised clock of described communication interface, when described logic operation result is described control signal, realize closing to the synchronised clock of described communication interface;
The audio process of portable terminal is used to settle described communication interface.
8. system according to claim 7 is characterized in that, described audio process comprises: analogue device control register, digital device control register, analogue device and digital device.
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| CN2007100649089A CN101039155B (en) | 2007-03-28 | 2007-03-28 | Method, apparatus and system for controlling synchronization clock of communication interface |
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| CN2007100649089A CN101039155B (en) | 2007-03-28 | 2007-03-28 | Method, apparatus and system for controlling synchronization clock of communication interface |
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| CN102662894B (en) * | 2012-03-23 | 2015-04-22 | 中国航天科技集团公司第九研究院第七七一研究所 | General bus slave unit interface |
| CN111339001B (en) * | 2020-03-09 | 2021-07-30 | 厦门润积集成电路技术有限公司 | Low-power-consumption single bus communication method and system |
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| US6188641B1 (en) * | 1999-03-31 | 2001-02-13 | Fujitsu Limited | Synchronous semiconductor memory device having input circuit with reduced power consumption |
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| CN1716771A (en) * | 2004-06-30 | 2006-01-04 | 因芬尼昂技术股份公司 | clock control unit |
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| CN1162182A (en) * | 1996-01-17 | 1997-10-15 | 三菱电机株式会社 | Synchronous type semiconductor memory that reduces current consumed by its input buffer circuit |
| CN1204126A (en) * | 1997-06-26 | 1999-01-06 | 三菱电机株式会社 | Synchronous semiconductor memory device capable of reducing electricity consumption on standby |
| US6188641B1 (en) * | 1999-03-31 | 2001-02-13 | Fujitsu Limited | Synchronous semiconductor memory device having input circuit with reduced power consumption |
| US6349071B1 (en) * | 2000-02-16 | 2002-02-19 | Sharp Kabushiki Kaisha | Synchronous semiconductor storage device |
| CN1716771A (en) * | 2004-06-30 | 2006-01-04 | 因芬尼昂技术股份公司 | clock control unit |
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