CN101038923A

CN101038923A - Non-volatile memory device and method of manufacturing the same

Info

Publication number: CN101038923A
Application number: CNA2007100854789A
Authority: CN
Inventors: 朴允童; 金元柱; 具俊谟; 金锡必; 玄在雄; 李政勋
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2006-03-17
Filing date: 2007-03-07
Publication date: 2007-09-19
Also published as: KR100773564B1; KR20070094444A; KR100785039B1; KR20070094582A

Abstract

The present invention provides a nonvolatile memory device which is less susceptible to read disturbance and has improved short channel effect and a manufacturing method thereof. The nonvolatile memory device may include a semiconductor substrate having a body and a pair of fins. The bridge insulating layer may not electrically connect upper portions of the pair of fins to define a void between the pair of fins, wherein the outer surface of the pair of fins is the surface of the pair of fins that does not face the void, and the pair of fins The inner surface is the surface of the pair of fins facing the void. The non-volatile memory device may also include at least one control gate electrode covering at least a portion of an outer surface of the pair of fins, extending over the bridge insulating layer, and isolated from the semiconductor substrate. At least one pair of gate insulating layers may be located between the control gate electrode and the pair of fins, and at least one pair of storage nodes may be located between the at least one pair of gate insulating layers and at least one control gate electrode.

Description

Non-volatile memory device and manufacture method thereof

Technical field

The present invention relates to a kind of non-volatile memory device and manufacture method thereof.And more specifically, the present invention relates to a kind of non-volatile memory device and manufacture method thereof with fin channel district.

Background technology

Along with the size of semiconductor product reduces, must increase by the data volume that semiconductor product is handled.Therefore, after deliberation a kind of increase be used in the service speed of the non-volatile memory device in the semiconductor product and the method for integrated level.For example, by using fin field-effect transistor (Fin-FET) to have the situation of semiconductor device of the integrated level of increase, the area of raceway groove can be exaggerated with increase service speed and simultaneously the width of fin can be reduced to increase integrated level.The Fin-FET of use silicon-on-insulator (SOI) substrate can be considered to further improve the possible method of short-channel effect.

The SOI substrate may be quite expensive.Therefore, carried out attempting to use the body Semiconductor substrate similar to form fin-FET or fin memory cell to the characteristic of SOI substrate.Yet,, need fin-shaped Cheng Degeng closer to each other to increase the integrated level of device even in this situation.Therefore, between adjacent fin, can produce and read to disturb.Even when using the SOI substrate, according to the dielectric property of insulator, for example the short-channel effect of drain induced barrier reduction may cause problem.

Summary of the invention

Illustrative examples of the present invention provides a kind of non-volatile memory device that is not subject to read to disturb and have the short-channel effect of improvement.

Illustrative examples of the present invention also provides a kind of manufacture method of non-volatile memory device that is not subject to read to disturb and has the short-channel effect of improvement.

According to illustrative examples of the present invention, non-volatile memory device can comprise: have main body and the right Semiconductor substrate of fin outstanding from main body and that separate relative to each other, and the right top of non-electric-connecting described fin with described fin between define the bridge insulating barrier of vacancy, the right outer surface of wherein said fin is the right surface of fin of not facing described vacancy, and the right inner surface of described fin is the right surface of fin in the face of described vacancy.

This non-volatile memory device can at least one control grid electrode, covers at least a portion of the right outer surface of described fin, extends above described bridge insulating barrier, and isolates from described Semiconductor substrate.At least one pair of gate insulation layer can described at least one control grid electrode and described fin between.At least one pair of memory node can be between described at least one pair of gate insulation layer and described at least one control grid electrode.At least one control grid electrode can comprise a plurality of control grid electrodes, and at least one pair of gate insulation layer can comprise many to gate insulation layer, and at least one pair of memory node can comprise many to memory node.The bridge insulating barrier can be positioned at described fin on the top, and described vacancy be defined in described bridge insulating barrier and described fin between.The bridge insulating barrier can extend connecting the top of the right inner surface of described fin, and described vacancy be defined in described bridge insulating barrier and described fin between.

This non-volatile memory device can also be included in the bottom next door and the device isolation layer between described at least one control grid electrode and main body of the right outer surface of described fin.This at least one pair of gate insulation layer can be formed on the right outer surface of described fin.This at least one pair of gate insulation layer can also be formed on the right top portion of described fin.This non-volatile memory device can also be included at least one drain region that is formed at least one source region of described fin centering on the side of described at least one control grid electrode and is formed at described fin centering on the opposite side of described at least one control grid electrode.This Semiconductor substrate can form by etching body semiconductor wafer.This at least one pair of gate insulation layer can also be formed on the right upper end of described fin.

According to illustrative examples, the method for making non-volatile memory device can comprise: the etching semiconductor substrate is to define main body and all right from the outstanding fin of main body; The bridge insulating barrier that form to connect the right part of described fin, with described fin between define vacancy; Form part and cover gate insulation layer in the face of the right outer surface of the fin of described vacancy; Form the storage node layer that covers described gate insulation layer; With the control grid electrode that forms the described storage node layer of covering and above described bridge insulating barrier, extend.

Description of drawings

With reference to the accompanying drawings, by describing its one exemplary embodiment in detail, it is more obvious that above and other features and advantages of the present invention will become, in the accompanying drawings:

Fig. 1 illustrates the schematic diagram of non-volatile memory device according to an embodiment of the invention;

Fig. 2 is the schematic diagram along the non-volatile memory device shown in Fig. 1 that I-I ' got of Fig. 1;

Fig. 3 is the schematic diagram along the non-volatile memory device shown in Fig. 1 that II-II ' got of Fig. 1;

Fig. 4 is the schematic diagram that non-volatile memory device according to another embodiment of the present invention is shown;

Fig. 5 is the curve chart that the electrical characteristics of soi structure and SOV structure are shown;

Fig. 6 is the perspective view that non-volatile memory device according to another embodiment of the present invention is shown; And

Fig. 7 to 13 illustrates according to the non-volatile memory device of illustrative examples of the present invention and the perspective view of manufacture method thereof.

Embodiment

With reference to the accompanying drawing that wherein shows embodiments of the invention the present invention is described more all sidedly thereafter.Yet the present invention can realize and should not be construed as being limited to the embodiment of explaination here with many different forms.But, provide these embodiment to make the disclosure, and pass on scope of the present invention all sidedly to those those skilled in the art fully with complete.In the accompanying drawings, for clear layer and the regional thickness exaggerated.

Be appreciated that when element or layer be called as another element or layer " on " or when " being connected to ", " being coupled to " another element or layer, it can be directly on other elements or layer, directly connect or be coupled to other element or layer, the element in the middle of maybe can existing or layer.On the contrary, when element be called as " directly " other elements or layer " on " or when " being directly connected to ", " being directly coupled to " other element or layer, then do not have intermediary element or layer to exist.The similar in the whole text similar element of label indication.Terminology used here " and/or " comprise one or more any and all combinations of associated listed items.

First, second can be used for describing various elements, parts, zone, layer and/or part in this with C grade though be appreciated that term, and these elements, parts, zone, layer and/or part are not limited by these terms should.These terms only are used to distinguish an element, parts, zone, layer or part and other elements, parts, zone, layer or part.Therefore, first element discussed below, parts, zone, layer or part can be called as second element, parts, zone, layer or part, and without departing the teaching of the invention.

The convenience in order to describe here can the usage space relative terms, such as " following ", " below ", D score, " top ", " on " etc., an element or parts and other (all) elements or (all) parts relation are as shown in FIG. described.Be appreciated that the space relative terms is intended to comprise the different directions of device in using or operating except the direction of being painted in the drawings.For example, if device in the drawings is reversed, the element that is described as be in " below " or " following " of other elements or parts then should be oriented in " top " of described other elements or parts.Therefore, exemplary term " below " can comprise below and top both direction.Device also can have other orientation (revolve and turn 90 degrees or other orientation) and explain that correspondingly employed space describes language relatively here.

Here employed term is only for the purpose of describing special embodiment and be not intended to limit the present invention.As used herein, singulative also is intended to comprise plural form, unless content is clearly indicated the other meaning.Will also be understood that, the term that uses in this specification " comprises " having specified and has described parts, integral body, step, operation, element and/or member, do not exist or increases one or more miscellaneous parts, integral body, step, operation, element, member and/or its group but do not get rid of.

Reference section is shown in has described embodiments of the invention here, and this diagram is the schematic diagram of desirable embodiment of the present invention.Therefore, can expect because for example variation of the illustrated shape that causes of manufacturing technology and/or tolerance.Therefore, embodiments of the invention should not be construed as the special region shape shown in being limited to here, but comprise because departing from of the shape that is caused by manufacturing for example.For example, the injection region that is illustrated as rectangle can have the feature of rounding or curve usually and/or have the gradient of implantation concentration at its edge rather than the binary from the injection region to non-injection region changes.Similarly, can be by injecting the district that imbeds that forms in some injections of region generating between the surface of imbedding the district and injecting by its generation.Therefore, the zone shown in the figure be in essence schematically and their shape be not intended to illustrate device the zone true form and be not intended to limit the scope of the invention.

Unless otherwise defined, otherwise all terms used herein have (comprising technology and scientific terminology) meaning of general technical staff of the technical field of the invention's common sense.For example should also be understood that those terms that in normally used dictionary, define should be interpreted as having with the correlation technique environment in the consistent meaning, and should not be construed as the excessive ideal or the excessive formal meaning, unless clearly so limit.

Along with grid length is reduced to quite low value, short-channel effect may be general in MOSFET, and can be defined as to show as gradually with source region and drain region and shorten.

Fig. 1 illustrates the schematic diagram of non-volatile memory device according to an embodiment of the invention.Fig. 2 is the schematic diagram along the non-volatile memory device shown in Fig. 1 that I-I ' got of Fig. 1.Fig. 3 is the schematic diagram along the non-volatile memory device shown in Fig. 1 that II-II ' got of Fig. 1.Non-volatile memory device according to present embodiment shows the unit cell structure.For example, the unit cell structure can be used to flash memory and/or sonos silicon (SONOS) memory.In addition, the unit cell structure can form NAND cell array structure or NOR cell array structure.

Referring to figs. 1 to 3, non-volatile memory device can comprise Semiconductor substrate 110, bridge insulating barrier 115, gate insulation layer to 125a and 125b, memory node to 130a and 130b and control grid electrode 140.Optionally, can further provide device isolation layer 120.To the structure of non-volatile memory device in more detail be described thereafter.

Semiconductor substrate 110 can comprise main body 102 and from main body 102 outstanding from the fin that separates toward each other to 105a and 105b.More specifically,

fin

105a and 105b separate toward each other in the X1 direction, and extend along the X2 direction.Semiconductor substrate 110 can be by etching body semiconductor wafer, and for example body silicon wafer and/or body SiGe wafer form.Fin 105a and 105b can be by forming with main body 102 identical materials.

Bridge insulating barrier 115 can non-electric-connecting fin 105a and the upper end of 105b between

fin

105a and 105b, to define vacancy 117.Bridge insulating barrier 115 can extend in the upper end of fin 105a and 105b.By so, vacancy 117 can be defined between

fin

105a and 105b and the bridge insulating barrier 115.In illustrative examples, vacancy 117 can be represented the space with the hollow of fills with air.Bridge insulating barrier 115 can for example comprise silicon oxide layer and/or silicon nitride layer.

Vacancy 117 can define with the whole bag of tricks.For example, the buried insulator layer (not shown) can be formed between fin 105a and the 105b, and forms the bridge insulating barrier 115 of the upper end that covers fin 105a and 105b.Can optionally remove buried insulator layer with respect to bridge insulating barrier 115, form vacancy 117 thus.

Control grid electrode 140 can coverage rate at least a portion outer surface of

fin

105a and 105b, wherein inner surface is the surface in the face of vacancy 117, and control grid electrode 140 can cross the top of bridge insulating barrier 115.Control grid electrode 140 can be isolated from Semiconductor substrate 110.For example, control grid electrode 140 can form the top of the outer surface that covers the fin 105a that exposed by device isolation layer 120 and 105b.Device isolation layer 120 can comprise silicon oxide layer and/or silicon nitride layer.

Control grid electrode 140 can pass through

gate insulation layer

125a and 125b and/or memory node 130a and the isolation of 130b electricity with

fin

105a and 105b, and can pass through device isolation layer 120 electricity isolation with main body 102.For example, control grid electrode 140 can comprise the composite bed of polysilicon, metal, metal silicide and/or these materials.

Gate insulation layer

125a and 125b can be interposed in respectively between control grid electrode 140 and fin 105a and the 105b.For example,

gate insulation layer

125a and 125b can be formed at the top of the outer surface of

fin

105a and 105b respectively.

Gate insulation layer

125a and 125b or can be called as tunneling insulation layer are because they can be used as the tunnelling path of electric charge.

Gate insulation layer

125a and 125b can be for example formed by the compound of silica, silicon nitride, high dielectric constant material and/or these materials.

Memory node

130a and 130b can be arranged at respectively between

gate insulation layer

125a and 125b and the control grid electrode 140.For example,

memory node

130a and 130b can form the top with the outer surface that covers

fin

105a and 105b, and can be formed on the outer surface of gate insulation layer 125a and

125b.Memory node

130a and 130b can be used to stored charge.Flash memory can use floating, and the SONOS memory can use electric charge capture layer.

Memory node

130a and 130b can comprise polysilicon, SiGe, silicon and/or metal dots, silicon and/or metal single crystal and/or silicon nitride layer.The memory node 130a and the 130b that are made up of polysilicon and/or SiGe can be used as the charge storage film of floating.The memory node 130a and the 130b that comprise silicon and/or metal dots, silicon and/or metal single crystal and/or silicon nitride layer can be used as trap-charge storage film.

Source region 145 can be formed among fin 105a and the 105b in a side of control grid electrode 140, and drain region 150 can be formed among fin 105a and the 105b at the opposite side of control grid electrode 140.Source region 145 and drain region 150 can be the classification of form, and name is free to change as described.Source region 145 and drain region 150 can form diode junctions for main body 102 and/or the fin 105a different with source region 145 and drain region 150 and other parts of 105b.For example, when source region 145 and drain region 150 usefulness n type doping impurity, the part and/or the main body 102 of other of fin 105a different with source region 145 and

drain region

150 and 105b can be used p type doping impurity.

Non-volatile memory device can also be included in the barrier insulating layer (not shown) between control grid electrode 140 and memory node 130a and the 130b.When

memory node

130a and 130b when forming, can need barrier insulating layer by electric conducting material (such as polysilicon and/or SiGe).Barrier insulating layer can for example be a silicon oxide layer.

Thereafter, with the operating characteristic of describing according to the non-volatile memory device of present embodiment.In aforesaid non-volatile memory device, the depletion region that is formed in the part of the fin 105a in source region 145 and

drain region

150 and 105b can be limited.Because fin 105a and 105b are rather narrow, so depletion region can further be limited.Because the existence of vacancy 117, Width promptly on as shown in Figure 1 the X1 direction depletion region can be limited, and so will only form along the X3 direction.Yet if reduced the width of

fin

105a and 105b, the influence of the depletion region that forms along the X3 direction can reduce.It should be noted that vacancy 117 can have the dielectric constant that is lower than any insulating barrier.

Potential energy in fin 105a between source region 145 and drain region 150 and the 105b part (can be called channel region) and exhaust and significantly to be influenced by vacancy 117.So the arranging and can compare of

fin

105a and 105b and vacancy 117 with the soi structure of routine, and can be named as the structure of silicon (SOV) on the vacancy.

Different according to the SOV structure of using in the structure of present embodiment and the conventional flat crystal tubular construction.This structure can be called as class SOV structure.Conventional SOV structure can be arranged at for example X3 direction of vertical direction, but can be arranged at for example X1 direction of horizontal direction according to the class SOV structure of present embodiment.In class SOV structure according to the present invention,

fin

105a and 105b can not exclusively float from main body 102, and be different with the SOV structure of routine.

SOV structure and/or class SOV structure can reduce because the contingent short-channel effect of expansion of depletion region.Can reduce cut-off current and junction leakage, and can improve to leak and cause potential barrier reduction (DIBL) effect.In any case, can keep body bias being provided to the advantage of

fin

105a and 105b by voltage is provided to main body 102.

Fig. 5 is the curve chart that the electrical characteristics of soi structure and SOV structure are shown.In Fig. 5, represent the curve of SOV structure to obtain by in the flat crystal tubular construction, using the SOV structure, it shows the advantage according to the class SOV structure of present embodiment indirectly.With reference to figure 5, to compare with soi structure, the SOV structure has low cut-off current value and high firing current value.Shown in the illustration among Fig. 5, the SOV structure can have the DIBL value lower than soi structure.Vacancy can have the dielectric constant lower than insulator.Can have the short-channel effect of improvement according to the non-volatile memory device with class SOV structure of present embodiment from above outcome expectancy, for example low cut-off current, high firing current and low DIBL value.

In the non-volatile memory device according to present embodiment,

fin

105a and 105b can be used as bit line, and control grid electrode 140 can be used as word

line.Memory node

130a and 130b can be used as charge storage layer.When

fin

105a and 105b are set to when adjacent one another are, the electric charge that is stored among memory node 130a and the 130b can cause reading disturbing.For example, be stored in the potential energy that adjacent electric charge among the left memory node 130a can change right fin 125b, can disturb the reading of state of right memory node 130b thus, vice versa.Because vacancy 117 for example air has the dielectric constant lower than any insulator, can alleviate and read interference problem.Compare with the soi structure of routine, SOV structure and/or class SOV structure can increase the reliability of read operation.

Fig. 4 is the schematic diagram that non-volatile memory device according to another embodiment of the present invention is shown.Non-volatile memory device shown in Fig. 4 is the variant that changes a little shown in Fig. 1.Therefore, also non-volatile memory device shown in Figure 4 can be used for, and therefore the part of repetition will be no longer described referring to figs. 1 to the description of the non-volatile memory device shown in 3.In two embodiment, reference number similar among the figure is indicated similar element.

With reference to figure 4, bridge insulating barrier 115 ' forms the space between the top of the inner surface of filling fin 105a and 105b.So, vacancy 117 ' can define between bridge insulating barrier 115 ' time and fin 105a and 105b.For example, when forming insulating barrier by physical vapor deposition (PVD) between very narrow fin 105a that separates and 105b, can form bridge insulating barrier 115 ', because bad step covers, bridge insulating barrier 115 ' only connects the upper end of

fin

105a and 105b.

Because the top of

fin

105a and 105b is not covered by bridge insulating barrier 115 ' and is exposed thus, gate insulation layer 125a ' and 125b ' can extend on the outer surface of

fin

105a and 105b, for example extend on the top of the outer surface of the top of

fin

105a and 105b and

fin

105a and 105b.

Non-volatile memory device according to present embodiment can have and the characteristic identical according to the non-volatile memory device of aforesaid embodiment.

Fig. 6 is the schematic diagram that non-volatile memory device according to another embodiment of the present invention is shown.Non-volatile memory device shown in Figure 6 can obtain to enable nand gate by connecting a plurality of non-volatile memory devices.The not description of the part that repeats in previous embodiment of repeated reference, and the similar element of similar in the drawings reference number indication.

With reference to figure 6, a plurality of control grids 140 can extend the top and the bridge insulating barrier 115 of the outer surface of the opposite side, fin 105a and the 105b that cover vacancy 117, and bridge insulating barrier 115 forms to extend between the upper end of fin 105a and 105b.A plurality of gate electrodes 140 are separated from each other.A plurality of

gate insulation layer

125a and 125b are interposed in respectively between control grid electrode 140 and fin 105a and the 105b.A plurality of

memory node

130a and 130b are interposed in respectively between control grid electrode 140 and gate insulation layer 125a and the 125b.

In enable nand gate, the source region 145 of Fig. 3 and the drain region 150 of Fig. 3 can alternately be formed among the

corresponding fin

105a and 105b between the control corresponding gate electrode 140.The order in source region and drain region be not fix and can reverse.In Fig. 6, the quantity of shown control grid electrode 140 is the purpose in order to illustrate only, and scope of the present invention is not limited to such numeral.In addition, the right of

fin

105a and 105b has been shown among Fig. 6, but manyly can further be arranged at column direction the fin (not shown).Be arranged at the control grid electrode in the delegation and can be connected to each other.

Though memory device shown in Figure 1 is used in the enable nand gate of Fig. 6, non-volatile memory device shown in Figure 4 also can be used in the enable nand gate.

Fig. 7-the 13rd illustrates according to the non-volatile memory device of another illustrative examples and the schematic diagram of manufacture method thereof.

With reference to figure 7, at least one pair of first groove 153 is formed in the Semiconductor substrate 110.For example, hard mask layer 150 is formed on the Semiconductor substrate 110.Then, use hard mask layer 150 as etching mask, the expose portion of Semiconductor substrate 110 is etched to form first groove 153.Hard mask layer 150 can comprise nitride layer and/or oxide skin(coating).

With reference to figure 8, device isolation layer 120a is filled in first groove 153 at least.For example, device isolation layer 120a is filled in first groove 153, and complanation exposes up to hard mask layer 150 then.So, device isolation layer 120a is filled in first groove 153 with outstanding from Semiconductor substrate 100.

With reference to figure 9, hard mask layer 150 is removed, and gap insulation layer 155 is formed on from the sidewall of the outstanding device isolation layer 120a of Semiconductor substrate 110.Each gap insulation layer 155 has and is suitable for the width that part exposes the Semiconductor substrate 110 between them.For example, form the gap insulation layer 155 feasible predetermined insulating barrier of anisotropic etching then that deposits.Gap insulation layer 155 can comprise nitride layer, and also is included in the oxide skin(coating) that nitride layer increases below.

With reference to Figure 10, use gap insulation layer 155 as etching mask, the Semiconductor substrate 110 that exposes between gap insulation layer 155 is etched, to form second groove 160.So, defined from the outstanding fin of the main body of Semiconductor substrate 110 105a and 105b.First and second grooves 153 and 160 can have the equal degree of depth or the degree of depth that differs from one another.

With reference to Figure 11, the non-conductive cap rock 157 that forms joint gap insulating barrier 155 is to define fin to the vacancy 117a between 105a and the 105b.Cap rock 157 uses to have the sedimentation that bad step covers and forms, and makes that cap rock 157 can joint gap insulating barrier 155 and be not filled in fin in the space between 105a and the 105b.

For example, cap rock 157 can comprise silicon nitride layer, and can pass through plasma enhanced chemical vapor deposition (PECVD) formation.In this situation, cap rock 157 is growth thickly on gap insulation layer 155, but fin to the bottom of 105a and 105b and sidewall on growth or do not grow a little.Therefore, cap rock 157 be filled into fin to the space between 105a and the 105b in before, joint gap insulating barrier 155.In this situation, consider the depth-width ratio of second groove 160, cap rock 157 can connect the upper end of

fin

105a and 105b.

If cap rock 157 is growth a little on the bottom of

fin

105a and 105b and sidewall, in cap rock 157, define vacancy 117a.Yet when the depth-width ratio of second groove 160 was big, cap rock 157 was grown on the sidewall of

fin

105a and 105b hardly.In this situation, vacancy 117a can be defined between

fin

105a and 105b and the cap rock 157, perhaps between

fin

105a and 105b, gap insulation layer 155 and cap rock 157.

With reference to Figure 12, thereby cap rock 157 is defined bridge insulating barrier 115a by complanation selectively.For example can use and eat-back or cmp (CMP) carries out complanation.Bridge insulating barrier 115a comprises gap insulation layer 155 and cap rock 157.Therefore, vacancy 117a defines between bridge insulating barrier 115a and

fin

105a and 105b.

With reference to Figure 13, form device isolation layer 120 to expose the part of

fin

105a and 105b, for example upper end.For example, can etched predetermined thickness from the outstanding device isolation layer 120a of Semiconductor substrate 110, therefore form device isolation layer 120.

After this,

gate insulation layer

125a and 125b are formed on not on the part in the face of the fin 105a of vacancy 117a and 105b.For example, use thermal oxidation or chemical vapour deposition (CVD),

gate insulation layer

125a and 125b can be formed on from the top of the fin 105a of device isolation layer 120 exposures and 105b.If the use chemical vapour deposition (CVD),

gate insulation layer

125a and 125b can be connected to each other above bridge insulating barrier 115a.

Then, form

storage node layer

130a and 130b with covering gate insulating barrier 125a and 125b.For example,

storage node layer

130a and 130b can be shaped as covering

gate insulating barrier

125a and 125b and the clearance wall from being separated from each other.Replacedly,

storage node layer

130a and 130b can covering

gate insulating barrier

125a and 125b and are connected to each other above bridge insulating barrier 115a.

Subsequently, control grid electrode 140 covering

storage node layer

130a and 130b, and above bridge insulating barrier 115a, extend.Optionally, before forming control grid electrode 140, the barrier insulating layer (not shown) can also be set come covering storage node layer 130a and 130b.Control grid electrode 140 can be by main body 102 insulation of device isolation layer 120 from Semiconductor substrate 110.

Therefore, according to illustrative examples, can use typical manufacturing process to make non-volatile memory device economically with SOV structure.

In this illustrative examples, bridge insulating barrier 115a can be corresponding to the bridge insulating barrier 115 with reference to the described non-volatile memory device of figure 1-3.Therefore, the description with reference to the operating characteristic of the non-volatile memory device shown in the figure 1-3 also can be applied to this illustrative examples.

In addition, obviously can easily be applied to enable nand gate shown in Figure 6 according to the manufacture method of the non-volatile memory device of this illustrative examples.

As the improvement variant of this illustrative examples,

fin

105a and 105b can not use the gap insulation layer 155 shown in Fig. 9 and 10 to form.For example, in Fig. 7 and 8, first and second grooves 153 and 160 use typical photoetching or etching to form continuously or once form, thereby define fin 105a and the 105b that gives prominence to from main body 102.In this situation, in Figure 11-13, bridge insulating barrier 115a can define vacancy 117a by cap rock 157 separately, and does not need gap insulation layer 155.Here, bridge insulating barrier 115a can be corresponding to reference to figure 4 described structures.

Non-volatile memory device according to the present invention has the short-channel effect of class SOV structure and improvement.For example, cut-off current and junction leakage reduce, and firing current increases, and leakage initiation potential barrier reduction (DIBL) effect is enhanced.Yet, kept body bias being applied to the advantage of fin by applying voltage to main body.

In addition, read interference by comparing with conventional soi structure to reduce, non-volatile memory device according to the present invention relates to high reading reliability.

Though specifically show and described the present invention with reference to its one exemplary embodiment, yet one of ordinary skill in the art is appreciated that and do not breaking away under the situation of the spirit and scope of the present invention that defined by claim, can make the different variations on form and the details.

Claims

1. A non-volatile memory device, comprising:

a semiconductor substrate having a body, and a pair of fins protruding from the body and spaced apart relative to each other;

a bridge insulating layer electrically connecting upper portions of the pair of fins to define a void between the pair of fins;

Wherein the outer surface of the pair of fins is the surface of the pair of fins not facing the vacancy, and the inner surface of the pair of fins is the surface of the pair of fins facing the vacancy.

2. The nonvolatile memory device according to claim 1, further comprising:

at least one control gate electrode covering at least a portion of an outer surface of the pair of fins, extending over the bridge insulating layer and isolated from the semiconductor substrate;

at least one pair of gate insulating layers between the at least one control gate electrode and the pair of fins; and

At least one pair of storage nodes is located between the at least one pair of gate insulating layers and the at least one control gate electrode.

3. The nonvolatile memory device according to claim 2, wherein said at least one control gate electrode comprises a plurality of control gate electrodes, said at least one pair of gate insulating layers comprises a plurality of pairs of gate insulating layers, and said at least one The pair of storage nodes includes multiple pairs of storage nodes.

4. The nonvolatile memory device of claim 1, wherein the bridge insulating layer is located on top of the pair of fins, and the void is defined between the bridge insulating layer and the pair of fins.

5. The nonvolatile memory device according to claim 1, wherein the bridge insulating layer extends to connect upper portions of inner surfaces of the pair of fins, and the vacancy is defined between the bridge insulating layer and the pair of fins between.

6. The nonvolatile memory device of claim 2, further comprising a device isolation layer beside lower portions of outer surfaces of the pair of fins and between the at least one control gate electrode and the body.

7. The nonvolatile memory device according to claim 2, wherein the at least one pair of gate insulating layers is formed on outer surfaces of the pair of fins.

8. The nonvolatile memory device according to claim 7, wherein the at least one pair of gate insulating layers is also formed on top portions of the pair of fins.

9. The nonvolatile memory device according to claim 2, further comprising at least one source region formed in the pair of fins on one side of the at least one control gate electrode and At least one drain region in the pair of fins is formed on the other side of the fin.

10. The nonvolatile memory device according to claim 1, wherein the semiconductor substrate is formed by etching a bulk semiconductor wafer.

11. The nonvolatile memory device according to claim 7, wherein the at least one pair of gate insulating layers is also formed on upper ends of the pair of fins.

12. The nonvolatile memory device according to claim 9, wherein the bridge insulating layer is filled in an upper end portion between the pair of fins, and the vacancy is defined between the bridge insulating layer and the pair of fins .

13. A method of manufacturing a nonvolatile memory device, comprising:

etching the semiconductor substrate to define a body and a pair of fins each protruding from the body;

forming a bridge insulating layer connecting portions of the pair of fins to define a void between the pair of fins;

forming a gate insulating layer partially covering outer surfaces of fin pairs not facing the vacancy;

forming a storage node layer covering the gate insulating layer; and

A control gate electrode is formed covering the storage node layer and extending over the bridge insulating layer.

14. The method of claim 13, wherein the bridge insulating layer is also formed on the pair of fins and the body within the void, and the void is defined within the bridge insulating layer.

15. The method of claim 13, wherein the bridge insulating layer is formed by plasma enhanced chemical vapor deposition.

16. The method of claim 15, wherein the bridge insulating layer is filled in an upper end portion between the pair of fins, and the vacancy is defined between the bridge insulating layer and the pair of fins.

17. The method of claim 15, wherein the bridge insulating layer extends over upper ends of the pair of fins, and the void is defined between the bridge insulating layer and the pair of fins.

18. The method of claim 13, wherein defining the body and fin pairs comprises:

forming a first pair of trenches in the semiconductor substrate;

forming a device isolation layer filled in the first trench and protruding from the semiconductor substrate;

forming a gap insulating layer along a protruding sidewall of the device isolation layer; and

The semiconductor substrate exposed between the gap insulating layers is etched to define a pair of fins protruding from the body.

19. The method of claim 18, after defining the pair of fins, further comprising forming a capping layer connecting the gap insulating layer and defining the void between the pair of fins,

Wherein the bridge insulating layer includes the gap insulating layer and a cover layer.

20. The method of claim 19, after forming the capping layer, further comprising etching the device isolation layer to a predetermined depth, thereby exposing portions of outer surfaces of the pair of fins.