KR100943646B1 - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

The present invention relates to semiconductor memory devices and the like. More specifically, the present invention relates to a DRAM device without a capacitor and a method of manufacturing the same.

The semiconductor memory device according to the present invention is formed on a first insulating layer formed on a substrate, a second insulating layer formed on both sides of the first insulating layer spaced apart from each other, a first insulating layer between the second insulating layer, The region includes a floating body in which a protruding pattern protruding from the second insulating layer, a gate structure formed to surround the protruding pattern, and a source and a drain formed at both sides of the protruding pattern.

The semiconductor memory device according to the present invention may be driven as a capacitorless DRAM device without a separate voltage applied for the accumulation of holes. In addition, the degree of integration of the semiconductor memory device may be improved.

Capacitor-less DRAM, Silicon On Insulator (SOI) substrates, pin field effect transistors, fully depleted AOI pin field effect transistors (FD-FinFET on SOI)

Description

Semiconductor memory device and manufacturing method therefor {SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF}

The present invention relates to semiconductor memory devices and the like. More specifically, the present invention relates to a DRAM device without a capacitor and a method of manufacturing the same.

In general, a unit cell of a DRAM device includes one MOS field effect transistor and one capacitor for storing charge. The DRAM device has a simple configuration and is widely used as a memory device of a system because it operates at a high speed when a power is supplied. However, when scaling down a memory device for high integration, it is difficult to scale down the capacitor area with respect to the entire area of the unit cell. Accordingly, a capacitor-less DRAM has been proposed to increase the integration of DRAM devices. The capacitorless DRAM is driven by charging the substrate with a hole using impact ionization. In addition, the state of the DRAM without the capacitor is defined as a state of '1' or '0' depending on the accumulation or egress of holes.

In the case of a capacitorless DRAM using a conventional fully depleted silicon on insulator (FD SOI) substrate, a potential well must be formed by applying a separate voltage to the substrate to accumulate holes. There is a hassle. In addition, in the case of a capacitorless DRAM having a double gate having an asymmetric structure, a potential well is formed by applying a voltage to one side of the gate to charge the hole, thereby making it necessary to manufacture the hole to be accumulated.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a capacitorless semiconductor memory device capable of being driven as a DRAM device without a voltage applied to accumulate holes and a method of manufacturing the same.

The semiconductor memory device according to the present invention is formed on a first insulating layer formed on a substrate, a second insulating layer formed on both sides of the first insulating layer spaced apart from each other, a first insulating layer between the second insulating layer, The region includes a floating body in which a protruding pattern protruding from the second insulating layer, a gate structure formed to surround the protruding pattern, and a source and a drain formed at both sides of the protruding pattern.

The floating body region under the protrusion pattern may have a lower potential than the area of the protrusion pattern when the semiconductor memory device is driven.

The substrate is preferably a silicon on insulator (SOI) substrate.

The second insulating layer is preferably formed using a high density plasma (HDP).

It is preferable that the width of the cross section of the floating body increases as it approaches the first insulating layer.

The method of manufacturing a semiconductor memory device according to the present invention comprises the steps of (a) forming a floating body on a first insulating layer formed in a substrate, and (b) forming a second insulating layer having a thickness thinner than that of the floating body. Forming at both sides, (c) forming a gate structure to surround the upper portion of the floating body, and (d) forming a source and a drain at both upper portions of the floating body.

The substrate is preferably a silicon on insulator (SOI) substrate.

The floating body is preferably formed by removing both sides of the substrate to expose the first insulating layer.

(b) step,

And depositing a second insulating layer on the substrate on which the floating body is formed, and removing a portion of the second insulating layer to expose the upper portion of the floating body.

The second insulating layer is preferably formed using a high density plasma (HDP).

The second insulating layer is preferably removed using a chemical mechanical polishing (CMP) process and a wet etching process.

(c) step,

Forming a gate oxide film on the exposed top surface of the floating body cell, forming a gate structure to surround the top of the floating body cell on which the gate oxide film is formed, and patterning the gate structure to expose both upper portions of the floating body cell; It is preferable to include.

The semiconductor memory device according to the present invention can be driven as a capacitorless DRAM device without a separate voltage applied to form the potential well. In addition, the degree of integration of the semiconductor memory device may be improved.

Hereinafter, a semiconductor memory device according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

1 is a diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor memory device according to an embodiment of the inventive concept may include a first insulation layer 110 formed on a substrate 100 and second insulation portions spaced apart from each other on both sides of the first insulation layer 110. A floating body cell formed on the first insulating layer 110 between the layer 120 and the second insulating layer 120 and having a protruding pattern 130 protruding from the second insulating layer 120. 135, a gate structure 140 formed to surround the protruding pattern 130, and a source 151 and a drain 152 formed at both sides of the protruding pattern 130.

The substrate 100 may be a silicon on insulator (SOI) or SOI substrate having a first insulating layer 110 formed therein. The substrate 100 may be a P-type semiconductor substrate formed of silicon, silicon germanium, and any one of tensile silicon or tensile silicon germanium. The first insulating layer 110 may be formed including silicon oxide (SiO ₂ ) (Subindex).

The second insulating layers 120 are formed to be spaced apart from each other on both sides of the first insulating layer 110. The second insulating layer 120 may be formed through a high density plasma (HDP). The floating body 135 is formed on the first insulating layer 110 between the second insulating layers 120 spaced apart from each other. A protruding pattern 130 having a shape protruding from the second insulating layer 120 is formed in an upper region of the floating body 135. In addition, the source 151 and the drain 152 are formed at both sides of the protruding pattern 130. That is, the source 151 and the drain 152 may be formed at both sides of the upper portion of the floating body 135 with the protrusion pattern 130 interposed therebetween. Accordingly, a channel may be formed in the protrusion pattern 130 when the semiconductor memory device is driven.

The gate structure 140 is formed to surround the protruding pattern 130 of the floating body 135. Here, the gate structure 140 is formed to surround only the protruding pattern 130 of the floating body 135 by the second insulating layer 120. Therefore, the floating body 135 may have a region isolated from the gate structure 140 by the second insulating layer 120. The silicon nitride layer 160 and the gate oxide layer 170 may be sequentially formed between the protruding pattern 130 and the gate structure 140.

In the capacitorless semiconductor memory device according to an embodiment of the present invention, a power supply voltage is first applied to the gate structure 140 and the drain 152 for driving. Accordingly, in the semiconductor memory device, pairs of electrons and holes are generated in regions of the protruding pattern 130 adjacent to the drain 152 having a strong electric field by an applied power supply voltage. Electrons move to the drain 152, and holes are accumulated in the lower region of the floating body 135 adjacent to the first insulating layer 110, which is not surrounded by the gate structure 140. Since the lower region of the floating body 135 is separated from the gate structure 140 by the second insulating layer 120, it is not affected by the gate electric field. Accordingly, the lower region of the floating body 135 has a lower potential than the region of the protruding pattern 130. Due to the lowered potential, the potential well is formed in the floating body 135, and holes may be accumulated in the lower region of the floating body 135 which is not affected by the gate electric field. Accordingly, the semiconductor memory device may perform a function of a partially depleted silicon on insulator (PD SOI or less, PD SOI). Meanwhile, a three-dimensional thin film channel is formed in the protruding pattern 130 formed between the source 151 and the drain 152 by electrons moving to the drain 152. In addition, the semiconductor memory device may form a wider width of the floating body 135 in which holes are accumulated than the protruding pattern 130 in which the 3D thin film channel is formed, so that the potential well may be deeper.

FIG. 2 is a cross-sectional view of the semiconductor memory device along the AA ′ direction shown in FIG. 1.

Referring to FIG. 2, the width of the cross section of the floating body 135 in which the protruding pattern 130 is formed increases as the first insulating layer 110 approaches. As shown in FIG. 2A, the floating body 135 is formed in a structure perpendicular to the substrate 100 together with the protruding pattern 130 so that the floating body 135 is driven when the semiconductor memory device is driven. The hole 180 may be accumulated in the lower region of the hole. In addition, as shown in FIGS. 2-b and 2-c, the floating body 135 may be formed in a trapezoidal or triangular shape together with the protruding pattern 130. In this case, since the lower region of the floating body 135 is thicker than the width of the protrusion pattern 130, more holes 180 are accumulated in the lower region.

3 is a diagram illustrating a simulation of a potential well formed in each floating body of a semiconductor memory device and a conventional semiconductor memory device according to an embodiment of the present invention.

In order to fill the hole in the conventional floating body 12 illustrated in FIG. 3-a, a separate voltage must be applied to the substrate 10. When a separate voltage is not applied to the substrate 10, a barrier lowering occurs between the source and the substrate 10 due to the drain voltage for generating an ion collision effect. Accordingly, since the deep potential well is not formed in the floating body 12, holes are hard to accumulate.

As shown in FIG. 3-b, the floating body 135 region below the protrusion pattern 130 has a lower potential than the channel region formed in the protrusion pattern 130 when the semiconductor memory device is driven. Here, since the floating body 135 region is not affected by the gate 140 electric field by the second insulating layer 120 when the semiconductor memory device is driven, the potential of the floating body 135 may be formed to be low. Accordingly, a deeper potential well is formed in an area of the floating body 135 that is not affected by the electric field of the gate 140, so that more holes can be accumulated. In order to accumulate holes, a DRAM having a conventional FD SOI (Fully Depleted Silicon On Insulator) structure requires a separate voltage to be applied to a substrate, or an asymmetric double gate field effect transistor to separately apply a voltage to one gate. . However, in the semiconductor memory device according to the embodiment of the present invention, since the deep potential well is formed by the second insulating layer 120 formed to surround a portion of the floating body 135, the hole can be charged. Accordingly, the process of applying a voltage to the semiconductor memory device for hole accumulation may be omitted. Therefore, the semiconductor memory device has an effect of applying a positive voltage to the substrate 100, and the threshold voltage is lowered by this effect. Accordingly, the semiconductor memory device may be driven as a memory device that determines whether or not charge is stored by increasing the source current when the holes are accumulated or decreasing the source current when the holes are ejected due to the lowered threshold voltage.

4 is a graph illustrating a source current measurement of a semiconductor memory device according to an exemplary embodiment.

Referring to FIG. 4, in the semiconductor memory device, a data state ('1' or '0' state) may be determined according to a first source current 200 and a second source current 210 sensed by a source. The first source current 200 represents an increased source current due to a lowered threshold voltage when holes are accumulated in the semiconductor memory device. The second source current 210 represents a reduced source current due to an increased threshold voltage when the negative electrode is discharged by applying a negative voltage to the drain. In a general DRAM, a read state requires a refresh after reading a data state. However, in the semiconductor memory device according to the embodiment of the present invention, when the source current increased or decreased depending on the state of the hole, the data retention time for determining the state of '1' or '0' is determined up to 70 msec. maintain. In addition, nondestructive read states are possible during the data retention time, allowing capacitorless DRAM operation without additional refresh.

Therefore, the semiconductor memory device may be formed to minimize the influence of the floating body cell from the gate electric field, thereby accumulating more holes. Accordingly, the semiconductor memory device may be driven by a capacitorless DRAM without a separate voltage applied to accumulate holes.

In addition, in the semiconductor memory device, since the gate structure surrounds the protruding pattern (channel region) in three dimensions, the channel control ability of the gate can be improved. Accordingly, the short channel effect of the semiconductor memory device can be effectively reduced. In addition, the degree of integration of the semiconductor memory device may be improved.

Hereinafter, a method of manufacturing a semiconductor memory device according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

5 through 11 are views illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

In the method of manufacturing a semiconductor memory device according to an embodiment of the present invention, forming a floating body on a first insulating layer formed in a substrate, the second insulating layer having a thickness thinner than the floating body on both sides of the floating body Forming a gate structure so as to surround the top of the floating body and forming a source and a drain at both sides of the upper portion of the floating body.

[ Floating body  Forming step]

5 and 6 illustrate a step of forming a floating body of a semiconductor memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 5, the substrate 100 may be a P-type semiconductor substrate formed of silicon, silicon germanium, and any one of tensile silicon and tensile silicon germanium. The substrate 100 may be a silicon on insulator (SOI) or SOI substrate having a first insulating layer 110 formed therein. Here, the thickness of the floating body 135 may be formed by the height of the subsequent channel region is formed. Thereafter, the silicon nitride film 160 is deposited on the floating body 135.

Referring to FIG. 6, both sides of the substrate 100 are removed to expose the first insulating layer 110 using the deposited silicon nitride layer 160 as a hard mask. Here, both sides of the substrate 100 more specifically mean both sides of the floating body 135. Therefore, the floating body 135 exposed at both sides may be formed perpendicular to the substrate 100 on the first insulating layer 110. Here, the floating body 135 may be formed such that the width of the cross section from the upper region adjacent to the silicon nitride film 160 to the lower region adjacent to the first insulating layer 110 increases gradually. For example, the width of the cross section of the floating body 135 may be formed in the shape of a triangle or a trapezoid, thereby making the width of the lower region larger than the upper region of the floating body 135.

[Second Insulation layer  Forming step]

7 and 8 illustrate a step of forming a second insulating layer of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 7, the second insulating layer 120 is deposited on the first insulating layer 110 and the floating body 135 using high density plasma (HDP). Here, the second insulating layer 120 may include silicon oxide (SiO ₂ ) (Subindex).

Referring to FIG. 8, the second insulating layer 120 is removed through a chemical mechanical polishing (CMP) process so that the silicon nitride film 160 formed on the floating body 135 is exposed. Subsequently, a part of the second insulating layer 120 is removed through the wet etching process so that the upper portion of the floating body 135 is exposed by a predetermined height of the channel. Accordingly, the second insulating layer 120 having a thickness thinner than that of the floating body 135 is formed at both sides of the floating body 135. The second insulating layer 120 which is not removed on the first insulating layer 110 is formed to secure an area of the floating body 135 separated from the gate structure to be described later. Accordingly, the floating body 135 has a form in which the upper body protrudes from the second insulating layer 120.

[Step of forming gate structure]

9 and 10 illustrate a step of forming a gate structure of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 9, a gate oxide layer 170 is formed on the floating bar dice 135 protruding from the second insulating layer 120 and the second insulating layer 120. The gate oxide layer 170 is formed to thinly surround the floating body 135 protruding from the second insulating layer 120.

Referring to FIG. 10, the gate structure 140 is formed to surround the floating body 135 in which the gate oxide layer 170 is formed. The gate structure 140 may be patterned to form subsequent sources and drains on both sides of the floating body 135 protruding from the second insulating layer 120.

[ Source  And Drain  Forming step]

FIG. 11 is a diagram illustrating a semiconductor memory device in a direction orthogonal to the direction AA ′ shown in FIG. 1. More specifically, FIG. 11 is a view illustrating a step of forming a source and a drain of a semiconductor memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 11, the source 151 and the drain 152 are formed at both sides of the protruding floating body region 130. The source 151 and the drain 152 may be formed using a diffusion or ion implantation process and a subsequent heat treatment process.

As described above, those skilled in the art to which the present invention pertains will understand that the present invention may be implemented in other specific forms without changing the technical spirit or essential features. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive, and the scope of the present invention is indicated by the following claims rather than the above description, and the meaning and scope of the claims And all changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

1 and 2 illustrate a semiconductor memory device according to a preferred embodiment of the present invention.

3 is a view showing a potential well of a conventional semiconductor memory device and a semiconductor memory device according to a preferred embodiment of the present invention;

4 is a diagram showing a source current of a semiconductor memory device of the present invention.

5 through 11 illustrate a method of manufacturing a semiconductor memory device according to an exemplary embodiment of the present invention.

******** Explanation of symbols for the main parts of the drawing ********

100: substrate

110: first insulating layer

120: second insulating layer

130: protrusion pattern

135: floating body

140: gate structure

151: source

152: drain

160: silicon nitride film

170: gate oxide film

Claims (12)

A first insulating layer formed on the substrate; Second insulating layers spaced apart from each other on both sides of the first insulating layer; A floating body cell formed on the first insulating layer between the second insulating layers and having a protruding pattern protruding from a portion of the second insulating layer; A gate structure formed to surround the protruding pattern; And And a source and a drain formed at both sides of the protruding pattern. The method of claim 1, The floating body region under the protruding pattern has a lower potential than the area of the protruding pattern when the semiconductor memory device is driven. The method of claim 1, The substrate is a silicon on insulator (SOI) substrate, semiconductor memory device. The method of claim 1, The second insulating layer is formed using a high density plasma (HDP), semiconductor memory device. The method of claim 1, The width of the cross-section of the floating body increases as the closer to the first insulating layer. (a) forming a floating body on the first insulating layer formed in the substrate; (b) forming second insulating layers having a thickness thinner than that of the floating body on both sides of the floating body; (c) forming a gate structure to surround an upper portion of the floating body; And (d) forming a source and a drain on both sides of the upper part of the floating body cell. The method of claim 6, The substrate is a silicon on insulator (SOI) substrate, manufacturing method of a semiconductor memory device. The method of claim 7, wherein The floating body is formed by removing both sides of the substrate to expose the first insulating layer, the manufacturing method of a semiconductor memory device. The method of claim 6, In step (b), Depositing a second insulating layer on the substrate on which the floating body is formed; And Removing a portion of the second insulating layer to expose an upper portion of the floating body; A manufacturing method of a semiconductor memory device comprising a. The method of claim 9, The second insulating layer is formed using a high density plasma (High Density Plasma (HDP)), manufacturing method of a semiconductor memory device. The method of claim 9, And the second insulating layer is removed using a chemical mechanical polishing (CMP) process and a wet etching process. The method of claim 9, In step (c), Forming a gate oxide film on an upper surface of the exposed floating body cell; Forming a gate structure to surround an upper portion of the floating body in which the gate oxide layer is formed; And Patterning the gate structure to expose both upper portions of the floating body; A manufacturing method of a semiconductor memory device comprising a.

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