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CN101030766B - 功率减小逻辑和非破坏性锁存电路以及应用 - Google Patents

功率减小逻辑和非破坏性锁存电路以及应用 Download PDF

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Publication number
CN101030766B
CN101030766B CN2006100641152A CN200610064115A CN101030766B CN 101030766 B CN101030766 B CN 101030766B CN 2006100641152 A CN2006100641152 A CN 2006100641152A CN 200610064115 A CN200610064115 A CN 200610064115A CN 101030766 B CN101030766 B CN 101030766B
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China
Prior art keywords
latch
sleep pattern
circuit
destructive
logical circuit
Prior art date
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Expired - Fee Related
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CN2006100641152A
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English (en)
Chinese (zh)
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CN101030766A (zh
Inventor
刘汉城
S·西尔斯
R·利雅纳盖
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Intel Corp
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Intel Corp
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Publication of CN101030766A publication Critical patent/CN101030766A/zh
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Power Sources (AREA)
  • Logic Circuits (AREA)
CN2006100641152A 2005-11-10 2006-11-09 功率减小逻辑和非破坏性锁存电路以及应用 Expired - Fee Related CN101030766B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/270,912 US8421502B2 (en) 2005-11-10 2005-11-10 Power reducing logic and non-destructive latch circuits and applications
US11/270912 2005-11-10

Related Child Applications (1)

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CN201110391763.XA Division CN102497192B (zh) 2005-11-10 2006-11-09 功率减小逻辑和非破坏性锁存电路以及应用

Publications (2)

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CN101030766A CN101030766A (zh) 2007-09-05
CN101030766B true CN101030766B (zh) 2012-01-11

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CN201110391763.XA Expired - Fee Related CN102497192B (zh) 2005-11-10 2006-11-09 功率减小逻辑和非破坏性锁存电路以及应用
CN2006100641152A Expired - Fee Related CN101030766B (zh) 2005-11-10 2006-11-09 功率减小逻辑和非破坏性锁存电路以及应用

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Country Status (3)

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US (3) US8421502B2 (ja)
JP (1) JP4494390B2 (ja)
CN (2) CN102497192B (ja)

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* Cited by examiner, † Cited by third party
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US7996695B2 (en) * 2008-02-15 2011-08-09 Qualcomm Incorporated Circuits and methods for sleep state leakage current reduction
US8234554B2 (en) * 2008-07-10 2012-07-31 International Business Machines Corporation Soft error correction in sleeping processors
KR101025734B1 (ko) * 2009-07-02 2011-04-04 주식회사 하이닉스반도체 반도체 집적장치의 커맨드 제어회로
US8307226B1 (en) * 2011-12-20 2012-11-06 Intel Corporation Method, apparatus, and system for reducing leakage power consumption
KR101934433B1 (ko) * 2012-05-31 2019-01-02 에스케이하이닉스 주식회사 블럭 보호가 가능한 반도체 장치
US10338558B2 (en) * 2014-10-17 2019-07-02 21, Inc. Sequential logic circuitry with reduced dynamic power consumption
CN104635589B (zh) * 2015-02-03 2017-08-29 成都秦川物联网科技股份有限公司 一种不同电源主体间的低功耗通信系统及其方法
US10491217B2 (en) * 2018-08-09 2019-11-26 Intel Corporation Low-power clock gate circuit
TWI674754B (zh) 2018-12-28 2019-10-11 新唐科技股份有限公司 資料保持電路
CN119781597B (zh) * 2025-03-10 2025-05-06 重庆双芯科技有限公司 集成芯片中休眠芯片上电系统及休眠芯片启动方法

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US4749991A (en) * 1986-07-05 1988-06-07 Motorola, Inc. Turn off protection circuit

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US5337285A (en) * 1993-05-21 1994-08-09 Rambus, Inc. Method and apparatus for power control in devices
EP0713292A3 (en) * 1994-11-21 1997-10-01 Motorola Inc Feedback interlock circuit and its operating method
JP2000114935A (ja) * 1998-10-02 2000-04-21 Nec Corp 順序回路
JP3587299B2 (ja) * 2000-07-12 2004-11-10 沖電気工業株式会社 半導体集積回路
US6275083B1 (en) * 2000-09-05 2001-08-14 Agilent Technologies, Inc. Low operational power, low leakage power D-type flip-flop
KR100413758B1 (ko) * 2001-03-26 2003-12-31 삼성전자주식회사 지연 동기 루프를 구비하는 반도체 메모리 장치
US7058834B2 (en) * 2001-04-26 2006-06-06 Paul Richard Woods Scan-based state save and restore method and system for inactive state power reduction
US6822478B2 (en) * 2001-07-03 2004-11-23 Texas Instruments Incorporated Data-driven clock gating for a sequential data-capture device
US6882200B2 (en) * 2001-07-23 2005-04-19 Intel Corporation Controlling signal states and leakage current during a sleep mode
US6784693B2 (en) * 2002-03-08 2004-08-31 Spreadtrum Communications Corporation I/O buffer having a protection circuit for handling different voltage supply levels
US6512394B1 (en) * 2002-03-14 2003-01-28 United Memories, Inc. Technique for efficient logic power gating with data retention in integrated circuit devices
US6850103B2 (en) * 2002-09-27 2005-02-01 Texas Instruments Incorporated Low leakage single-step latch circuit
US6775180B2 (en) * 2002-12-23 2004-08-10 Intel Corporation Low power state retention
JP2005086215A (ja) 2003-09-04 2005-03-31 Sony Corp 半導体集積回路、回路設計装置および方法、記録媒体、並びにプログラム
US6965261B2 (en) * 2003-11-13 2005-11-15 Texas Instruments Incorporated Ultra low-power data retention latch
KR100539254B1 (ko) * 2004-03-13 2005-12-27 삼성전자주식회사 테스트용 스캔 체인을 이용한 반도체 장치의 슬립모드에서의 데이터 보존 회로 및 그 보존 방법
US7848718B2 (en) * 2004-05-05 2010-12-07 St-Ericsson Sa Method apparatus comprising integrated circuit and method of powering down such circuit
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US4749991A (en) * 1986-07-05 1988-06-07 Motorola, Inc. Turn off protection circuit

Also Published As

Publication number Publication date
CN102497192B (zh) 2015-01-07
US9490807B2 (en) 2016-11-08
CN102497192A (zh) 2012-06-13
US20100289528A1 (en) 2010-11-18
JP2007172587A (ja) 2007-07-05
JP4494390B2 (ja) 2010-06-30
US8305112B2 (en) 2012-11-06
US20120223741A1 (en) 2012-09-06
US8421502B2 (en) 2013-04-16
CN101030766A (zh) 2007-09-05
US20070103201A1 (en) 2007-05-10

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Granted publication date: 20120111

Termination date: 20191109