CN100594679C - A dual mode frequency divider - Google Patents

Abstract

The invention discloses a dual-mode frequency divider, comprising: the dual-mode prescaler is used for carrying out frequency division on an externally input high-frequency signal and outputting the obtained frequency division signal to the programmable counter; the programmable counter is used for counting the input frequency division signal, and generating an output counting signal at the first signal output end when the counter counts to N and outputting the output counting signal to the signal selector; when the counter counts to M, an output counting signal is generated at the second signal output end and is output to the signal selector; the signal selector is used for gating a first signal output end or a second signal output end of the programmable counter under the action of the mode control signal, and generating a selection signal which is used as a clock to be output to the trigger or the latch; and the trigger or the latch continuously overturns the state of the output end under the action of the clock and outputs a mode control signal. The invention realizes the function of programming frequency division by using one counter, improves the working speed of the circuit and simplifies the circuit structure.

Description

A dual mode frequency divider

technical field

The invention relates to the field of electronic technology, can be applied to a phase-locked frequency synthesizer in a radio frequency transceiver, and in particular relates to a frequency divider which uses a single counter to realize dual-mode frequency division.

Background technique

The phase-locked frequency synthesizer plays an important role in synchronization, frequency conversion and channel switching in the communication system, and is one of the indispensable components of modern communication. As shown in FIG. 1, FIG. 1 is a schematic structural diagram of a phase-locked frequency synthesizer. The phase-locked frequency synthesizer consists of a phase-frequency detector and a charge pump (PFD/CP), a loop filter (LPF), a voltage-controlled oscillator (VCO) and a programmable frequency divider.

Among them, the frequency and phase detector and the charge pump are a phase comparison device. It compares the phase of the input signal and the output signal of the voltage-controlled oscillator, and generates an error voltage corresponding to the phase difference of the two signals.

The function of the loop filter is to filter out the high-frequency components and noise in the error voltage, so as to ensure the performance required by the loop and increase the stability of the system.

The voltage-controlled oscillator is controlled by the control voltage, so that the frequency of the voltage-controlled oscillator is close to the frequency of the input signal until the frequency difference is eliminated and locked.

The programmable frequency divider divides the frequency of the high-frequency signal output by the VCO by N, so as to achieve the same purpose as the reference frequency when locking.

The frequency divider of the frequency synthesizer must provide a programmable frequency division ratio M, and at low frequencies, it can be realized with a programmable counter. However, when the output frequency of the frequency synthesizer is very high, the high-speed counter is difficult to implement and consumes a lot of power. The frequency divider with high power consumption shortens the standby time of the communication system.

In order to solve this problem, modern people generally adopt a dual-mode frequency division technology, as shown in FIG. 2 , which is a schematic structural diagram of a traditional dual-mode frequency divider. The traditional dual-mode frequency divider consists of a dual-mode prescaler and two counters (the count values are P and S respectively and P>S, they are all programmable). The dual-mode prescaler divides the output signal of the VCO, and its frequency division ratio can be selected between N or N+1. At the beginning, the dual-mode prescaler divides the VCO output signal by N+1, and the S and P counters count the output pulses of the dual-mode prescaler. When a predetermined S value is reached, it will The frequency division ratio of the dual-mode prescaler is changed to N. After that, the S counter stops counting, and the P counter continues to count the output pulses of the dual-mode prescaler. When its count value reaches a predetermined P value, it resets itself and the S counter, and at the same time restores the division ratio of the dual-modulus prescaler to N+1. The whole process starts all over again. The frequency division ratio of the module composed of P counter, S counter and dual-modulus prescaler is: M=(N+1)S+N(P-S)=PN+S, and the frequency division ratio can be changed by changing S. When the frequency is divided by the dual-mode prescaler and the frequency is greatly reduced, the design of the subsequent sub-frequency divider is simplified to the design of a programmable counter, which reduces the power consumption of the entire system.

In order to further reduce power consumption, the chip area occupied by the circuit is reduced. US Patent 6,035,182 further simplifies the dual-mode frequency divider shown in FIG. 2 . The simplified circuit structure is shown in FIG. 3 , which is a schematic structural diagram of the dual-mode frequency divider proposed in US Patent No. 6,035,182.

This simplified circuit structure can be described as: a single counter dual-mode frequency division device uses a programmable frequency divider 308, the input terminal 301 of this programmable frequency divider is connected to the RF input signal, and the other input terminal is connected to Mode control signal, this control signal is generated by a programmable counter. This control signal controls the frequency division ratio of the programmable frequency divider, and the frequency-divided signal is output at terminal 314 . The apparatus also includes a switch 312 having inputs 304 and 306 respectively for receiving the first and second programming indications to generate a count control signal 318 . This count control signal determines the value of the counter. The programmable counter counts the input signal to 314 and produces an output signal at the output of the divider.

Its principle is to program the counter twice in one frequency division cycle of the system, so that its count value is U or L respectively. Whether to use U or L as the count value is determined by the state of the output frequency division signal 302 . Therefore, in a frequency division cycle, the total frequency division ratio is: N=U×(P+1)+L×P.

The disadvantage of the dual-mode frequency divider proposed by US Patent 6,035,182 is that in a frequency division cycle, the counter needs to be programmed twice, so it needs to provide two control signals outside (in the communication system, this signal is usually generated by the baseband) . This complicates the design of the baseband of the communication system, and is also different from the common situation in which a control signal can realize frequency switching in modern communication systems. Moreover, after a certain signal is selected by the control switch, the counter needs to be preset, and this process has a certain time delay, which reduces the working speed of the programmable frequency divider.

Contents of the invention

(1) Technical problems to be solved

In view of this, the main purpose of the present invention is to provide a frequency divider that uses a single counter to realize dual-mode frequency division, so as to realize programming of the counter by a control signal, improve the working speed of the circuit, further simplify the circuit structure, and reduce the frequency of the circuit. Reduce power consumption and reduce chip area.

(2) Technical solution

In order to achieve the above object, the present invention provides a dual-mode frequency divider, which comprises:

A dual-modulus prescaler 100 is used to divide the frequency of the high-frequency signal input from the outside under the control of the mode control signal output from the flip-flop or latch 400, and output the obtained frequency-divided signal to Programmable counter 200;

A programmable counter 200 is used to count the frequency division signal input by the dual-mode prescaler 100, and when the counter counts to N, an output count signal is generated at the first signal output terminal and output to the signal selector 300; When the counter counts to M, an output count signal is generated at the second signal output terminal and output to the signal selector 300, wherein M and N are natural numbers, and the specific values of this pair of natural numbers are determined by the logic state of the external programmable control signal Decide;

A signal selector 300 is used to select the first signal output terminal or the second signal output terminal of the programmable counter 200 under the control of the mode control signal received from the output of the flip-flop or latch 400 to generate a selection signal output to a flip-flop or latch 400;

A flip-flop or latch 400 takes the selection signal received from the signal selector 300 as an input clock, under the action of the input clock, constantly flips the state of the output terminal, and outputs a mode control signal, which simultaneously serves as the dual The output signal of the analog divider.

In the above scheme, the dual-mode prescaler 100 includes a high-frequency signal input terminal 401, a mode control signal input terminal 412 and a frequency division signal output terminal 402; when the dual-mode frequency divider is applied to phase-locked When looping, the high-frequency signal input terminal 401 is connected to the voltage-controlled oscillator to receive the high-frequency signal generated by the voltage-controlled oscillator; the mode control signal input terminal 412 is connected to the trigger or latch 400 to receive the trigger Or the mode control signal generated by the latch 400; the frequency division signal output terminal 402 is connected to the programmable counter 200, and the frequency division signal obtained after the frequency division by the dual-mode prescaler 100 is output to the programmable counter 200.

In the above scheme, the programmable counter 200 includes a frequency division signal input terminal 403, a count control signal input terminal 404, a reset control signal input terminal 405, a first signal output terminal 406 and a second signal output terminal 407; The frequency division signal input terminal 403 is connected to the frequency division signal output terminal 402 of the dual-mode prescaler 100; the count control signal input terminal 404 is connected to an externally input programmable control signal; the reset control signal input terminal 405 connected to the selection signal output terminal 410 of the signal selector 300 .

In the above solution, the signal selector 300 is composed of the following circuit: a NOT gate with an output terminal and an input terminal, the input terminal is connected to the first signal output terminal 406 of the programmable counter 200; the first AND Gate, its first input end is connected to the output end of the NOT gate, and the second input end is connected to the output end 414 of the flip-flop or latch 400; the second AND gate, its first input end is connected to the first input end of the programmable counter 200 Two signal output terminals 407, the second input terminal contacts the output terminal 414 of the flip-flop or latch 400; an OR gate, its input terminals are respectively connected to the output terminals of the first AND gate and the second AND gate, and the signals of the output terminals are respectively As a flip-flop or latch 400, and a clock and reset signal for the programmable counter 200.

In the above solution, the signal selector 300 includes a first signal input terminal 408, a second signal input terminal 409, a signal selection control terminal 411 and a selection signal output terminal 410; the first signal input terminal 408 is connected to the programmable The first signal output terminal 406 of the counter 200; the second signal input terminal 409 is connected to the second signal output terminal 407 of the programmable counter 200; the signal selection control terminal 411 is connected to the output of the flip-flop or the latch 400 Terminal 414, which controls whether the signal selector selects the first signal or the second signal; the selection signal output terminal 410 is connected to the clock input terminal 413 of the flip-flop or latch 400.

In the above scheme, the flip-flop or latch 400 includes a clock input terminal 413 and an output terminal 414; the clock input terminal 413 is connected to the selection signal output terminal 410 of the signal selector 300; the output terminal 414 The signal selection control terminal 411 of the signal selector 300 is connected with the mode control signal input terminal 412 of the dual-mode prescaler 100 .

(3) Beneficial effects

As can be seen from the foregoing technical solutions, the present invention has the following beneficial effects:

The frequency divider using a single counter to realize dual-mode frequency division provided by the present invention can generate at least two count values under the control of one programmable signal, and fully utilizes the mode control state of the dual-mode prescaler , choose different counting values in different states, so as to achieve the purpose of dual-mode frequency division. In addition to all the advantages of US Patent 6,035,182, it still uses a control signal to program the counter, which improves the working speed of the circuit, further simplifies the circuit structure, reduces the power consumption of the circuit, and reduces the chip area.

Description of drawings

Fig. 1 is a schematic structural diagram of a phase-locked frequency synthesizer;

FIG. 2 is a schematic structural diagram of a traditional dual-mode frequency divider;

FIG. 3 is a schematic structural diagram of a dual-mode frequency divider proposed in US Patent No. 6,035,182;

Fig. 4 is the structural representation of the frequency divider that uses single counter to realize dual-mode frequency division provided by the present invention;

Fig. 5 is the timing diagram of the output port in the frequency divider that uses a single counter to realize dual-mode frequency division provided by the present invention;

The symbols are explained as follows:

In Figure 3:

301: the input port of the dual-mode prescaler;

302: the output port of the dual-mode frequency divider;

304: control signal 1;

306: control signal 2;

308: dual-mode prescaler;

312: switch;

314: an output port of a dual-mode prescaler;

In Figure 4:

100: dual-mode prescaler;

200: programmable counter;

300: signal selector;

400: flip-flop or latch;

401: high-frequency signal input terminal;

402: frequency division signal output terminal;

403: frequency division signal input terminal;

404: counting control signal input terminal;

405: reset control signal input terminal;

406: the first signal output terminal;

407: the second signal output terminal;

408: a first signal input terminal;

409: a second signal input terminal;

410: select a signal output terminal;

411: signal selection control terminal;

412: mode control signal input terminal;

413: clock input terminal;

414: the output terminal of the dual-mode frequency divider;

In Figure 5:

CLK: Indicates the input clock of the frequency divider.

Q: Indicates the waveform of the output port of the 4/5 dual-mode prescaler.

OUT1: The waveform of the first output port of the counter.

OUT2: The waveform of the second output port of the counter.

SOUT: Signal selector output port waveform.

DOUT: The output port waveform of the entire frequency divider.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

As shown in Figure 4, Figure 4 is a schematic structural diagram of a frequency divider using a single counter to realize dual-mode frequency division provided by the present invention, the dual-mode frequency divider includes a dual-mode prescaler 100, a programmable counter 200, a signal selector 300 and flip-flop or latch 400 .

Wherein, the dual-mode prescaler 100 is used to divide the frequency of the high-frequency signal input from the outside under the control of the mode control signal received from the flip-flop or the output of the latch 400, and output the obtained frequency-divided signal to Programmable counter 200.

The programmable counter 200 is used for counting the frequency division signal input by the dual-mode prescaler 100, and when the counter counts to N, an output count signal is generated at the first signal output terminal and output to the signal selector 300; When counting to M, an output count signal is generated at the second signal output terminal and output to the signal selector 300, wherein M and N are natural numbers, and the specific values of this pair of natural numbers are determined by the logic state of the external programmable control signal.

The signal selector 300 is used to select the first signal output terminal or the second signal output terminal of the programmable counter 200 under the control of the mode control signal received from the output of the flip-flop or the latch 400, and generate a selection signal output to flip-flop or latch 400 .

The flip-flop or latch 400 takes the selection signal received from the signal selector 300 as an input clock, and under the action of the input clock, constantly flips the state of the output terminal, and outputs a mode control signal, which simultaneously serves as the dual mode The output signal of the divider.

The dual-mode prescaler 100 includes a high frequency signal input terminal 401 , a mode control signal input terminal 412 and a frequency division signal output terminal 402 . When the dual-mode frequency divider is applied to a phase-locked loop, the high-frequency signal input terminal 401 is connected to a voltage-controlled oscillator to receive a high-frequency signal generated by the voltage-controlled oscillator. The mode control signal input terminal 412 is connected to the flip-flop or the latch 400 to receive the mode control signal generated by the flip-flop or the latch 400 . The frequency division signal output terminal 402 is connected to the programmable counter 200 , and the frequency division signal obtained after the frequency division by the dual-mode prescaler 100 is output to the programmable counter 200 . The input terminal of the dual-mode prescaler is usually connected to a radio frequency signal, for example, in a phase-locked frequency synthesizer, it is connected to the output terminal of a voltage-controlled oscillator. In the dual-mode prescaler, under the action of the mode control terminal signal, the frequency division ratio can be P/P+1, where P is a natural number.

The above-mentioned programmable counter 200 includes a frequency division signal input terminal 403 , a count control signal input terminal 404 , a reset control signal input terminal 405 , a first signal output terminal 406 and a second signal output terminal 407 . The frequency division signal input terminal 403 is connected to the frequency division signal output terminal 402 of the dual-mode prescaler 100 . The counting control signal input terminal 404 is connected to an externally input programmable control signal. The reset control signal input terminal 405 is connected to the selection signal output terminal 410 of the signal selector 300 .

The input terminal of the programmable counter is connected to the output terminal of the dual-mode prescaler, the count control terminal is connected to the external baseband control circuit, and the reset control terminal is connected to the output terminal of the signal selector to be mentioned later. Under the action of , its state can be set to 0 or 1. The programmable counter counts the output signal of the dual-mode prescaler. When the counter counts to N or M, a pulse signal is generated at the first or second signal output terminal respectively, wherein the values of M and N are determined by the counting Control signal control. Whether to use M or N as the count value of the counter depends on the signal selector 300 .

Above-mentioned signal selector 300 is made up of following circuit:

A NOT gate has an output terminal and an input terminal, and the input terminal is connected to the first signal output terminal 406 of the programmable counter 200;

The first AND gate, its first input terminal is connected to the output terminal of the NOT gate, and the second input terminal is connected to the output terminal 414 of the flip-flop or latch 400;

The second AND gate, its first input terminal is connected to the second signal output terminal 407 of the programmable counter 200, and the second input terminal is connected to the output terminal 414 of the flip-flop or latch 400;

An OR gate, its input terminals are respectively connected to the output terminals of the first AND gate and the second AND gate, and the signals at the output terminals are used as the clock and reset signal of the flip-flop or latch 400 and the programmable counter 200 respectively.

The above-mentioned signal selector 300 includes a first signal input terminal 408 , a second signal input terminal 409 , a signal selection control terminal 411 and a selection signal output terminal 410 . The first signal input terminal 408 is connected to the first signal output terminal 406 of the programmable counter 200 . The second signal input terminal 409 is connected to the second signal output terminal 407 of the programmable counter 200 . The signal selection control terminal 411 is connected to the output terminal 414 of the flip-flop or latch 400, and it controls whether the signal selector selects the first signal or the second signal. Which one to choose is determined by the state of the control signal. When the control signal is low, it first passes through a NOT gate to become high, and then passes through an AND gate together with the first signal, and then passes through an OR gate. A pulse is generated at the output terminal of the device 300, and the first signal is selected. When the control signal is high, it selects the second signal. The selection signal output terminal 410 is connected to the clock input terminal 413 of the flip-flop or latch 400 .

The first input terminal and the second input terminal of the signal selector are connected to the first output terminal and the second terminal output terminal of the programmable counter, and its selection control terminal is connected to the output of the flip-flop or latch to be mentioned later end. Under the action of the selection control signal, the signal selector can count up to M (or N) and generate a selection signal at its output.

The above-mentioned flip-flop or latch 400 includes a clock input terminal 413 and an output terminal 414 . The clock input terminal 413 is connected to the selection signal output terminal 410 of the signal selector 300; the output terminal 414 is connected to the signal selection control terminal 411 of the signal selector 300 and the mode control signal input terminal of the dual-mode prescaler 100 412. The output 414 of the flip-flop or latch 400 is also the output of the entire frequency divider, outputting a low frequency signal.

The frequency divider which uses a single counter to realize dual-mode frequency division provided by the present invention only uses a single counter to realize, and is no different from the traditional frequency divider (using two counters) in the frequency division control signal. There are many literatures on the application of the frequency divider in the phase-locked frequency synthesizer, in the entire wireless transceiver system, and the realization of control signals, so I won't repeat them here.

The principle of this frequency divider is briefly described below, and the output signal of the output terminal 414 of the flip-flop or latch 400 is referred to as MC, that is, the mode control signal of the dual-mode prescaler 100 . Suppose when MC=0, that is, when it is low level, the frequency division ratio of the dual-module divider (dual-module divider) is P, and the selector strobe signal N is the first signal; when MC=1, That is, when the level is high, the frequency division ratio is P+1, the selector selector selects the signal M, that is, the second signal, and sets M>N, and sets MC=1 at the beginning. So there are:

When the VCO inputs N×(P+1) pulses to the input port 401 of the dual-mode prescaler 100, it counts these input pulses, and each input P+1 pulses will be generated at its output terminal 402 One pulse, so N pulses are generated. The programmable counter counts the output pulses of the dual modulus prescaler 100, and there are two possible count values, ie N and M. When the generated N pulses are input to the input terminal of the programmable counter, it will generate an output pulse at the first signal output terminal, but since MC=1 at this moment, the signal selector will not allow this pulse to pass through (due to It is the first signal, and when MC=1, the first signal is not selected), that is, there is no output pulse at the output terminal of the signal selector. Until when the VCO inputs M×(P+1) pulses and an output pulse is generated at the output terminal of the programmable counter, there is no output pulse at the output terminal of the signal selector. This pulse makes the D flip-flop flip (MC = 0), after that, the frequency division ratio of the dual-modulus prescaler is set to P; at the same time, the programmable counter is reset and starts counting again. When the VCO outputs N×P signal periods, a pulse signal will appear again at the output terminal of the signal selector. Since MC=0 at this time, it is selected to pass, this pulse makes the D flip-flop flip again (MC=1), after that, the frequency division ratio of the dual-mode prescaler is set to P+1, programmable The counter is reset again and starts counting again. Repeatedly from this. Therefore, the total frequency division ratio is: A=M×(P+1)+N×P.

The frequency division principle of the frequency divider with this structure will be further illustrated with a specific original example below. FIG. 5 is a timing diagram of an output port in a frequency divider using a single counter to realize dual-mode frequency division provided by the present invention. The dual-mode prescaler of this frequency divider is 4/5 frequency division, when MC=1, it is 5 frequency division, and when MC=0, it is 4 frequency division. The counter is a three-bit counter whose output is set to zero when the reset signal comes.

According to the formula: A=M×(P+1)+N×P, using 4/5 frequency division, in order to realize 44 frequency division, optional M=4, N=6. Analyze the timing from the dotted line in the figure, because MC=DOUT=1, so the frequency division ratio of the dual-mode prescaler is 5,

When the clock CLK passes through M*5=4*5=20 cycles, the first output port of the counter will have a pulse output, which is the pulse (1) in the figure. Since MC=1 at this time, there is also a pulse output at the output port of the signal selector, which is the pulse (2) in the figure. Pulse (2) causes the flip-flop to toggle, MC=0. The frequency division ratio of the dual-mode prescaler becomes 4, and after the clock CLK passes through M×4=4×4=16 cycles, there will be a pulse output at the first output port of the counter, that is, the pulse (3 ). However, since MC=0 at this time, the signal selector does not select this pulse, that is, no pulse appears at the output port of the signal selector. Until the clock CLK passes through N×4=6×4=24 cycles, there will be a pulse output at the second output port of the counter, which is the pulse (4) in the figure. Since MC=0 at this time, there is also a pulse output at the output port of the signal selector, which is the pulse (5) in the figure. Pulse (5) flips the flip-flop, MC=1. Thus, the task of using a counter to realize dual-mode frequency division is repeatedly completed. The frequency of CLK in the figure is 2.2GHz. After 44 frequency division, the frequency becomes 50M, and its period is 20ns.

In summary, the present invention uses a counter to realize dual-mode frequency division without any modification to the external circuit, and can be used as a frequency divider of a phase-locked frequency synthesizer of a wireless transceiver. Obviously, this invention simplifies the circuit structure, reduces the chip area, reduces the power consumption, and has obvious practical value and economic value.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (6)

1. A dual-mode frequency divider, characterized in that the dual-mode frequency divider comprises: A dual-modulus prescaler (100), used to divide the frequency of the high-frequency signal input from the outside under the control of the mode control signal output from the flip-flop or latch (400), and divide the obtained divided The frequency signal is output to the programmable counter (200); A programmable counter (200) is used to count the frequency division signal output by the dual-mode prescaler (100), and when the counter counts to N, an output count signal is generated at the first signal output terminal and output to the signal Selector (300); When the counter counts to M, an output count signal is generated at the second signal output terminal and output to the signal selector (300), wherein M and N are natural numbers; A signal selector (300), used to gate the first signal output terminal or the second signal output of the programmable counter (200) under the control of the mode control signal output from the flip-flop or latch (400) Terminal, generate a selection signal output to the flip-flop or latch (400); A flip-flop or latch (400), taking the selection signal received from the signal selector (300) as an input clock, under the action of the input clock, constantly flips the state of the output terminal, and outputs a mode control signal, the mode control signal At the same time as the output signal of the dual-mode frequency divider. 2. The dual-mode frequency divider according to claim 1, characterized in that, the dual-mode prescaler (100) comprises a high-frequency signal input terminal (401), a mode control signal input terminal (412) And a frequency division signal output terminal (402); When the dual-mode frequency divider is applied to a phase-locked loop, the high-frequency signal input terminal (401) is connected to a voltage-controlled oscillator to receive a high-frequency signal generated by the voltage-controlled oscillator; The mode control signal input terminal (412) is connected to the flip-flop or the latch (400), and receives the mode control signal generated by the flip-flop or the latch (400); The frequency division signal output terminal (402) is connected to the programmable counter (200), and the frequency division signal obtained after the frequency division by the dual-mode prescaler (100) is output to the programmable counter (200). 3. The dual-mode frequency divider according to claim 1, wherein the programmable counter (200) includes a frequency division signal input terminal (403), a counting control signal input terminal (404), a reset A control signal input terminal (405), a first signal output terminal (406) and a second signal output terminal (407); The frequency division signal input terminal (403) is connected to the frequency division signal output terminal (402) of the dual-mode prescaler (100); The counting control signal input terminal (404) is connected to an externally input programmable control signal; The reset control signal input terminal (405) is connected to the selection signal output terminal (410) of the signal selector (300). 4. The dual-mode frequency divider according to claim 1, wherein the signal selector (300) is composed of the following circuit: A NOT gate has an output terminal and an input terminal, the input terminal is connected to the first signal output terminal (406) of the programmable counter (200); The first AND gate, its first input terminal is connected to the output terminal of the NOT gate, and the second input terminal is connected to the output terminal (414) of the flip-flop or the latch (400); A second AND gate, the first input of which is connected to the second signal output (407) of the programmable counter (200), and the second input to the output (414) of the flip-flop or latch (400); One OR gate, its input terminal is respectively connected to the output terminal of the first AND gate and the second AND gate, and the signal at its output terminal is respectively used as a flip-flop or a latch (400), and a clock and a reset signal of a programmable counter (200) . 5. The dual-mode frequency divider according to claim 1, characterized in that, the signal selector (300) comprises a first signal input terminal (408), a second signal input terminal (409), a signal selection control terminal (411) and selection signal output terminal (410); The first signal input terminal (408) is connected to the first signal output terminal (406) of the programmable counter (200); The second signal input terminal (409) is connected to the second signal output terminal (407) of the programmable counter (200); The signal selection control terminal (411) is connected to the output terminal (414) of the flip-flop or the latch (400), and it controls whether the signal selector selects the first signal or the second signal; The selection signal output terminal (410) is connected to the clock input terminal (413) of the flip-flop or the latch (400). 6. The dual-mode frequency divider according to claim 1, wherein the flip-flop or latch (400) comprises a clock input terminal (413) and an output terminal (414); The clock input terminal (413) is connected to the selection signal output terminal (410) of the signal selector (300); The output terminal (414) is connected to the signal selection control terminal (411) of the signal selector (300) and the mode control signal input terminal (412) of the dual-mode prescaler (100).

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