CN100578796C - Active element array substrate - Google Patents

Abstract

An active element array substrate comprises a substrate, a pixel array, a plurality of connecting pads, a plurality of first switch elements and a plurality of second switch elements. The pixel array is configured on the display area of the substrate. The connecting pad, the first switch element and the second switch element are all arranged on the peripheral circuit area of the substrate, and the connecting pad is electrically connected with the pixel array. The first and second switch elements are located outside the pads, and each first switch element is electrically connected to one of the pads. Each first switch element is provided with a grid electrode, a source electrode and a drain electrode, and the grid electrode is respectively and electrically connected to the source electrode and the connecting pad. Each second switch element is electrically connected to two adjacent first switch elements respectively, and each second switch element is provided with a grid electrode, a source electrode and a drain electrode. The source is electrically connected with the drain of the adjacent first switch element, and the drain is electrically connected with the source of the adjacent first switch element. The invention adopts the first switch element and the second switch element to electrically connect each connecting pad, thereby having the function of electrostatic discharge protection.

Description

Active element array substrate

technical field

The present invention relates to an array substrate, and particularly relates to an active element array substrate.

Background technique

Due to the increasing demand for displays, the industry is fully committed to the development of related displays. Among them, the cathode ray tube (cathode ray tube, CRT) has been monopolizing the display market for many years because of its excellent display quality and technological maturity. However, due to the rise of the concept of green environmental protection, the characteristics of large energy consumption and large radiation, and the limited space for product flattening, it cannot meet the market demand for light, thin, short, small, beautiful and low power consumption. market trends. Therefore, thin film transistor liquid crystal display (TFT-LCD) with superior characteristics such as high image quality, good space utilization efficiency, low power consumption, and no radiation has gradually become the mainstream of the market.

For a TFT-LCD module, it is mainly composed of a liquid crystal display panel and a backlight module. Among them, the liquid crystal display panel is usually composed of a thin film transistor array substrate (thin film transistor array substrate), a color filter substrate (color filter substrate) and a liquid crystal layer arranged between the two substrates, and the backlight module is used for Provide the surface light source required by the liquid crystal display panel, so that the liquid crystal display module can achieve the display effect.

The thin film transistor array substrate can be divided into a display region and a peripheral circuit region, where a plurality of pixel units arranged in an array are arranged on the display region, and each pixel unit includes a thin film transistor and a thin film The pixel electrode (pixelelectrode) to which the transistor is connected. In addition, a plurality of scan lines and data lines are arranged in the peripheral circuit area and the display area, wherein the thin film transistor of each pixel unit is formed by the corresponding scan lines and data lines. control.

In order to avoid the problem of electrostatic damage during the manufacturing process, an electrostatic discharge (ESD) protection circuit is usually arranged on the peripheral circuit area of the thin film transistor array substrate, wherein the electrostatic discharge protection circuit includes an outer electrostatic discharge protection ring (outer short ring, OSR) and internal electrostatic discharge protection ring (inner short ring, ISR). After the fabrication of the entire thin film transistor array substrate is completed, a cutting process is usually performed to remove the external ESD protection ring. However, the protection ability of the thin film transistor array substrate against electrostatic discharge is reduced after removing the external electrostatic discharge protection ring.

Contents of the invention

The problem to be solved by the present invention is to provide an active element array substrate to improve the electrostatic discharge protection capability.

The invention provides an active element array substrate, which includes a substrate, a pixel array, multiple pads, multiple first switch elements and multiple second switch elements. Wherein, the substrate has a peripheral circuit area and a display area, and the pixel array is arranged on the display area. The pads are arranged on the peripheral circuit area and electrically connected with the pixel array. The first switching elements are arranged on the peripheral circuit area and located outside the pads, and each first switching element is electrically connected to one of the pads. Each first switching element has a gate, a source and a drain, wherein the gate is electrically connected to the source, and the gate is electrically connected to the pad. The second switching element is disposed on the peripheral circuit area and located outside the pads. Each second switch element is respectively electrically connected to two adjacent first switch elements, and each second switch element has a gate, a source and a drain. Wherein, the source is electrically connected to the drain of the adjacent first switch element, and the drain is electrically connected to the source of the adjacent first switch element.

In the active element array substrate of the present invention, the gate of each second switching element is a floating gate.

In the active element array substrate of the present invention, the gate and source of each second switching element are electrically connected.

In the active element array substrate of the present invention, the active element array substrate further includes a connection line disposed on the peripheral circuit area and located outside the first switch element and the second switch element. The source of each second switching element is electrically connected to the connection line, and the gate of each second switching element is a floating gate.

In the active element array substrate of the present invention, these pads include data line pads or scan line pads.

The invention provides an active element array substrate, which includes a substrate, a pixel array, multiple pads, multiple first switch elements and multiple second switch elements. Wherein, the substrate has a peripheral circuit area and a display area, and the pixel array is arranged on the display area. The pads are arranged on the peripheral circuit area and electrically connected with the pixel array. The first switching elements are arranged on the peripheral circuit area and located outside the pads, and each first switching element is electrically connected to one of the pads. Each first switching element has a gate, a source and a drain, wherein the gate is electrically connected to the source, and the gate is electrically connected to the pad, and the drain is a floating drain. The second switch element is disposed on the peripheral circuit area and located outside the pad. Each second switching element is electrically connected to one of the first switching elements respectively, and each second switching element has a gate, a source and a drain, wherein the drain is electrically connected to the source of the first switching element sexual connection. Also, the source is a floating source and the gate is a floating gate.

In the active element array substrate of the present invention, these pads include data line pads or scan line pads.

The present invention provides an active device array substrate, which includes a substrate, a pixel array, a plurality of pads, a plurality of first switching elements, a plurality of second switching elements and an external electrostatic discharge protection ring. Wherein, the substrate has a peripheral circuit area and a display area, and the pixel array is arranged on the display area. The pads are arranged on the peripheral circuit area and electrically connected with the pixel array. The first switching elements are arranged on the peripheral circuit area and located outside the pads, and each first switching element is electrically connected to one of the pads. Each first switching element has a gate, a source and a drain, wherein the gate is electrically connected to the source, and the gate is electrically connected to the pad. The second switching element is disposed on the peripheral circuit area and located outside the pads. Each second switch element is respectively electrically connected to two adjacent first switch elements, and each second switch element has a gate, a source and a drain. Wherein, the source is electrically connected to the drain of the adjacent first switch element, and the drain is electrically connected to the source of the adjacent first switch element. The external electrostatic discharge protection ring is disposed on the peripheral circuit area and located outside the first switch element and the second switch element, and the gates of each second switch element are electrically connected to the external electrostatic discharge protection ring.

In the active element array substrate of the present invention, the sources of the second switching elements are electrically connected to the external electrostatic discharge protection ring.

In the active element array substrate of the present invention, the gate and source of each second switching element are electrically connected.

In the active element array substrate of the present invention, the active element array substrate further includes a connection line, which is arranged on the peripheral circuit area, and is located outside the first switching element and the second switching element and outside the outer electrostatic discharge protection ring. inside. The source of each second switching element is electrically connected to the connection line, and the gate of each second switching element is electrically connected to the external electrostatic discharge protection ring.

In the active element array substrate of the present invention, these pads include data line pads or scan line pads.

The present invention provides an active device array substrate, which includes a substrate, a pixel array, a plurality of pads, a plurality of first switching elements, a plurality of second switching elements and an external electrostatic discharge protection ring. Wherein, the substrate has a peripheral circuit area and a display area, and the pixel array is arranged on the display area. The pads are arranged on the peripheral circuit area and electrically connected with the pixel array. The first switching elements are arranged on the peripheral circuit area and located outside the pads, and each first switching element is electrically connected to one of the pads. Each first switching element has a gate, a source and a drain, wherein the gate is electrically connected to the source, and the gate is electrically connected to the pad. The second switch element is disposed on the peripheral circuit area and located outside the pad. Each second switching element is electrically connected to one of the first switching elements respectively, and each second switching element has a gate, a source and a drain, wherein the drain is electrically connected to the source of the first switching element sexual connection. The external electrostatic discharge protection ring is arranged on the peripheral circuit area, and is located outside the first switch element and the second switch element, and the gate and source of each second switch element are respectively electrically connected to the external electrostatic discharge protection ring, and each The drain of the first switch element is electrically connected to the external ESD protection ring.

In the active element array substrate of the present invention, these pads include data line pads or scan line pads.

Based on the above, the present invention adopts the first switch element and the second switch element to electrically connect each pad, so the active matrix substrate has the function of electrostatic discharge protection. In addition, the pads can also be electrically insulated to reduce mutual interference of signals.

Description of drawings

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

FIG. 1A is an equivalent circuit diagram of an active device array substrate before a dicing process according to the first embodiment of the present invention.

1B is a top view of an active device array substrate before a cutting process according to the first embodiment of the present invention, which does not show a pixel array.

FIG. 2A is an equivalent circuit diagram of an active element array substrate according to the first embodiment of the present invention.

FIG. 2B is a top view of an active device array substrate according to the first embodiment of the present invention, which does not show a pixel array.

3A is an equivalent circuit diagram of an active device array substrate before a cutting process according to the second embodiment of the present invention.

FIG. 3B is a top view of an active device array substrate before cutting process according to the second embodiment of the present invention, which does not show the pixel array.

FIG. 4A is an equivalent circuit diagram of an active element array substrate according to the second embodiment of the present invention.

FIG. 4B is a top view of an active element array substrate according to the second embodiment of the present invention, which does not show a pixel array.

FIG. 5A is an equivalent circuit diagram of an active device array substrate before cutting process according to the third embodiment of the present invention.

5B is a top view of an active device array substrate before cutting process according to the third embodiment of the present invention, which does not show the pixel array.

FIG. 6A is an equivalent circuit diagram of an active element array substrate according to the third embodiment of the present invention.

FIG. 6B is a top view of an active device array substrate according to a third embodiment of the present invention, which does not show a pixel array.

FIG. 7A is an equivalent circuit diagram of an active device array substrate before cutting process according to the fourth embodiment of the present invention.

FIG. 7B is a top view of an active element array substrate before cutting process according to the fourth embodiment of the present invention, which does not show the pixel array.

FIG. 8A is an equivalent circuit diagram of an active element array substrate according to the fourth embodiment of the present invention.

FIG. 8B is a top view of an active device array substrate according to a fourth embodiment of the present invention, which does not show a pixel array.

Detailed ways

first embodiment

FIG. 1A is an equivalent circuit diagram of an active device array substrate before a dicing process according to the first embodiment of the present invention. 1B is a top view of an active device array substrate before a cutting process according to the first embodiment of the present invention, which does not show a pixel array.

Please refer to FIG. 1A , the method for manufacturing an active device array substrate in this embodiment includes the following steps. Firstly, a substrate 110 is provided, and the substrate 110 has a peripheral circuit area 110a and a display area 110b, wherein a pixel array 120 has been formed on the display area 110b. The pixel array 120 generally includes a plurality of scan lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes, but for the sake of simplicity, the detailed structure of the pixel array 120 is not shown. In addition, a plurality of pads 130 , a plurality of first switching elements 140 , a plurality of second switching elements 150 and an outer short ring (OSR) 160 have been formed on the peripheral circuit area 110 a. The pad 130 is electrically connected to the pixel array 120 , and the pad 130 may be a data line pad, a scan line pad or other types of pads.

The first switch element 140 and the second switch element 150 are located outside the pads 130 , wherein each first switch element 140 is electrically connected to one of the pads 130 . In more detail, each first switch element 140 has a gate 140g, a source 140s and a drain 140d, wherein the gate 140g is electrically connected to the source 140s, and the gate 140g is electrically connected to the pad 130 . In other words, the first switching element 140 can be regarded as a diode. In addition, each second switch element 150 is electrically connected to two adjacent first switch elements 140 . In other words, the second switching elements 150 are electrically connected in series with the first switching elements 140, so when an electrostatic discharge occurs, the current can move along the discharge path B in FIG. Possibility of electrostatic discharge damage. Each second switch element 150 has a gate 150g, a source 150s and a drain 150d. Wherein, the source 150s is electrically connected to the drain 140d of the adjacent first switching element 140 , and the drain 150d is electrically connected to the source 140s of the adjacent first switching element 140 . In addition, the source 150s and the gate 150g of each second switching element 150 are both electrically connected to the external ESD protection ring 160 .

The detailed structure will be described in detail below, but it should be noted that the structure represented by the equivalent circuit diagram of FIG. 1A is not limited to the structure shown in FIG. 1B . Those skilled in the technical field of the present invention should be able to change other structures based on the equivalent circuit diagram of FIG. 1A .

Please refer to FIG. 1B , in order to simplify the description, the detailed structure of the pixel array 120 is not drawn. The pad 130 includes a first metal layer 132, a second metal layer 134, a transparent conductive layer 136 and a plurality of contact windows 130a, 130b, wherein the first metal layer 132 and the second metal layer 134 are respectively disposed on the substrate 110 , and the transparent conductive layer 136 is disposed above the first metal layer 132 and the second metal layer 134 . In addition, the transparent conductive layer 136 is electrically connected to the first metal layer 132 through the contact window 130a, and the transparent conductive layer 136 is electrically connected to the second metal layer 134 through the contact window 130b.

The first switch element 140 includes a gate 140g, a source 140s, a drain 140d, a plurality of contact windows 142a, 142b, a semiconductor layer 144, and a transparent conductive layer 146, wherein the gate 140g is disposed on the substrate 110, And connected to the first metal layer 132 of the pad 130 . The semiconductor layer 144 is disposed above the gate 140g, and the source 140s and the drain 140d respectively cover part of the semiconductor layer 144 . The transparent conductive layer 146 is disposed above part of the source electrode 140s and above part of the gate electrode 140g, and the transparent conductive layer 146 is electrically connected to the source electrode 140s through the contact window 142a. The transparent conductive layer 146 is electrically connected to the gate 140g through the contact window 142b. Therefore, the source 140s of the first switching element 140 is electrically connected to the gate 140g through the transparent conductive layer 146 . In addition, the drain 140d is connected to the outer ESD protection ring 160 .

The second switch element 150 includes a gate 150g, a source 150s, a drain 150d and a semiconductor layer 152 . Wherein, the gate 150g is disposed on the substrate 110, and the semiconductor layer 152 is disposed above the gate 150g. The source 150s and the drain 150d respectively cover part of the semiconductor layer 152 , wherein the drain 150d is connected to the source 140s of the first switching element 140 , and both the source 150s and the gate 150g are connected to the external ESD protection ring 160 . In addition, the source 150s is connected to the drain 140d of the adjacent first switching element 140 . Therefore, the second switching element 150 is electrically connected in series with the first switching element 140 .

The external ESD protection ring 160 includes a first metal layer 162, a second metal layer 164, a transparent conductive layer 166 and a plurality of contact windows 168a, 168b, wherein the first metal layer 162 is disposed on the substrate 110, and the second The gate 150g of the switching element 150 is connected to the first metal layer 162 . The second metal layer 164 is disposed on the substrate 110 and covers part of the first metal layer 162 . In addition, both the source 150 s of the second switching element 150 and the drain 140 d of the first switching element 140 are connected to the second metal layer 164 . The transparent conductive layer 166 covers the first metal layer 162 and the second metal layer 164, wherein the transparent conductive layer 166 is electrically connected to the first metal layer 162 through the contact window 168a, and the transparent conductive layer 166 is electrically connected to the second metal layer through the contact window 168b. Two metal layers 164 .

Please continue to refer to FIG. 1A and FIG. 1B , and then, a cutting process is performed along the cutting line A to remove the external ESD protection ring 160 . At this point, the process of the active element array substrate 100 is completed.

FIG. 2A is an equivalent circuit diagram of an active element array substrate according to the first embodiment of the present invention. FIG. 2B is a top view of an active device array substrate according to the first embodiment of the present invention, which does not show a pixel array. Please refer to FIG. 2A and FIG. 2B , after the cutting process, the gate 150g of each second switch element 150 becomes a floating gate. In other words, the gate 150g is not connected to any circuit. Since these pads 130 are electrically connected in series with the second switching element 150 via the first switching element 140, when electrostatic discharge occurs, the current can spread along the discharge path B to the entire active element array substrate 100 to reduce the occurrence of electrostatic discharge. Electrostatic discharge damage occurs. In other words, the active device array substrate 100 has the function of electrostatic discharge protection.

second embodiment

3A is an equivalent circuit diagram of an active device array substrate before a cutting process according to the second embodiment of the present invention. FIG. 3B is a top view of an active device array substrate before cutting process according to the second embodiment of the present invention, which does not show the pixel array. Please refer to FIG. 3A first. This embodiment is similar to the first embodiment, the difference is that: the gate 250g of each second switching element 250 is electrically connected to the source 250s. Therefore, the second switching element 250 can be regarded as a diode. In addition, the drain 250d of the second switching element 250 is electrically connected to the source 140s of the first switching element 140 .

The detailed structure will be described in detail below, but it should be noted that the structure represented by the equivalent circuit diagram of FIG. 3A is not limited to the structure shown in FIG. 3B . Those skilled in the technical field of the present invention should be able to change other structures based on the equivalent circuit diagram of FIG. 3A .

Please refer to FIG. 3B , in more detail, the second switch element 250 includes a gate 250g, a source 250s, a drain 250d, a semiconductor layer 252, a transparent conductive layer 254 and a plurality of contact windows 256a, 256b. Wherein, the gate 250g is disposed on the substrate 110 and connected to the first metal layer 162 of the outer ESD protection ring 160 . The semiconductor layer 252 is located over the gate 250g. The source 250s and the drain 250d respectively cover part of the semiconductor layer 252 . In addition, in this embodiment, the source 250s further spans the gate 250g, and the transparent conductive layer 254 covers part of the source 250s and the gate 250g. The transparent conductive layer 254 is electrically connected to the gate 250g through the contact window 256a, and the transparent conductive layer 254 is electrically connected to the source electrode 250s through the contact window 256b. Since the second switching elements 250 are electrically connected in series with the first switching elements 140, when electrostatic discharge occurs, the current can move along the discharge path B and spread to the entire substrate 110, so as to reduce the possibility of electrostatic discharge damage. sex.

Please continue to refer to FIG. 3A and FIG. 3B , and then, a cutting process is performed along the cutting line A to remove the outer ESD protection ring 160 . At this point, the process of the active element array substrate 200 is completed.

FIG. 4A is an equivalent circuit diagram of an active element array substrate according to the second embodiment of the present invention. FIG. 4B is a top view of an active element array substrate according to the second embodiment of the present invention, which does not show a pixel array. Please refer to FIG. 4A and FIG. 4B , after the cutting process, the gates 250g of the second switching elements 250 are cut off. In addition, the gate 250g of each second switching element 250 is electrically connected to the source 250s. In other words, in this embodiment, the second switching element 250 and the first switching element 140 can be regarded as two diodes connected in series. Since these pads 130 are electrically connected in series with the second switching element 250 via the first switching element 140, when electrostatic discharge occurs, the current can diffuse to the entire active element array substrate 200 along the discharge path B to reduce the occurrence of electrostatic discharge. Electrostatic discharge damage occurs. In other words, the active device array substrate 200 has the function of electrostatic discharge protection. Furthermore, since the cutting process only cuts off the gates 250g of the second switching elements 250, the possibility of circuit short circuit caused by the metal debris generated by the cutting process can be reduced.

third embodiment

FIG. 5A is an equivalent circuit diagram of an active device array substrate before cutting process according to the third embodiment of the present invention. 5B is a top view of an active device array substrate before cutting process according to the third embodiment of the present invention, which does not show the pixel array. Please refer to FIG. 5A first. This embodiment is similar to the first embodiment. The difference is that a connection line 370 is formed on the peripheral circuit area 110a of the substrate 110, which is arranged between the first switch element 140 and the second switch. The outer side of the element 150 , and the source 150s of each second switching element 150 is electrically connected to the connection line 370 .

The detailed structure will be described in detail below, but it should be noted that the structure represented by the equivalent circuit diagram of FIG. 5A is not limited to the structure shown in FIG. 5B . Those skilled in the technical field of the present invention should be able to change other structures based on the equivalent circuit diagram of FIG. 5A .

Please refer to FIG. 5B , in more detail, the connection wire 370 is disposed on the peripheral circuit area 110 a and located outside the first switch element 140 and the second switch element 150 . In addition, the connection line 370 crosses the gate 150g of each second switch element 150 , and the source 150s of each second switch element 150 is electrically connected to the connection line 370 . Since the second switching elements 150 are electrically connected in series with the first switching elements 140, when electrostatic discharge occurs, the current can move along the discharge path B and spread to the entire substrate 110, so as to reduce the possibility of electrostatic discharge damage. sex. In addition, the connecting wire 370 also helps to reduce the possibility of ESD damage.

Please continue to refer to FIG. 5A and FIG. 5B , and then, a cutting process is performed along the cutting line A to remove the outer ESD protection ring 160 . At this point, the process of the active element array substrate 300 is completed.

FIG. 6A is an equivalent circuit diagram of an active element array substrate according to the third embodiment of the present invention. FIG. 6B is a top view of an active device array substrate according to a third embodiment of the present invention, which does not show a pixel array. Please refer to FIG. 6A and FIG. 6B , after the cutting process, the gate 150g of each second switching element 150 becomes a floating gate. In other words, the gate 150g is not connected to any circuit.

Since these pads 130 are electrically connected in series with the second switching elements 150 via the first switching elements 140, and the sources 150s of the second switching elements 150 are further electrically connected in series via the connecting wires 370, when electrostatic discharge occurs, the current flow It can be diffused to the entire active element array substrate 300 along the discharge path B and the connection line 370 to reduce the occurrence of ESD damage. In other words, the active device array substrate 300 has a better ESD protection function. Furthermore, since the cutting process only cuts off the gates 150g of the second switching elements 150, the possibility of circuit short circuit caused by the metal debris generated by the cutting process can be reduced.

Fourth embodiment

FIG. 7A is an equivalent circuit diagram of an active device array substrate before cutting process according to the fourth embodiment of the present invention. FIG. 7B is a top view of an active element array substrate before cutting process according to the fourth embodiment of the present invention, which does not show the pixel array. Please refer to FIG. 7A first, this embodiment is similar to the first embodiment, the difference is that: the drain 140d of the first switching element 140 is directly connected to the external ESD protection ring 160, and the source of the second switching element 150 150s is also directly connected to the outer ESD protection ring 160 . In other words, compared with the first embodiment, the drain 140d of the first switching element 140 and the source 150s of the second switching element 150 in this embodiment are respectively connected to the external ESD protection ring 160 . In addition, the drain 140d of the first switching element 140 is separated from the source 150s of the second switching element 150 .

The detailed structure will be described in detail below, but it should be noted that the structure represented by the equivalent circuit diagram of FIG. 7A is not limited to the structure shown in FIG. 7B . Those skilled in the technical field of the present invention should be able to change other structures based on the equivalent circuit diagram of FIG. 7A .

Please refer to FIG. 7B. In more detail, the source 150s of the second switching element 150 covers part of the gate 150g, and the source 150s of the second switching element 150 is directly connected to the second metal layer 164 of the outer ESD protection ring 160. . In addition, the drain 140 d of the first switching element 140 is also directly connected to the second metal layer 164 of the outer ESD protection ring 160 .

Please continue to refer to FIG. 7A and FIG. 7B , and then, a cutting process is performed along the cutting line A to remove the outer ESD protection ring 160 . At this point, the process of the active element array substrate 400 is completed.

FIG. 8A is an equivalent circuit diagram of an active element array substrate according to the fourth embodiment of the present invention. FIG. 8B is a top view of an active device array substrate according to a fourth embodiment of the present invention, which does not show a pixel array. Please refer to FIG. 8A and FIG. 8B , after the cutting process, the gate 150g and the source 150s of each second switching element 150 are cut off. Therefore, the gate 150g of each second switching element 150 becomes a floating gate, and the source 150s of each second switching element 150 also becomes a floating source. In other words, neither the gate 150g nor the source 150s is connected to any circuit. In addition, the drain 140d of the first switching element 140 is also cut off, so the drain 140d of the first switching element 140 also becomes a floating drain. Likewise, the drain 140d is not connected to any wiring. Therefore, an electrical disconnection is formed between the pads 130 of the active device array substrate 400 to reduce the possibility of signal interference.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the claims.

Claims (14)

1. An active element array substrate, characterized in that, comprising: A substrate with a peripheral circuit area and a display area; a pixel array configured on the display area; A plurality of pads are arranged on the peripheral circuit area and electrically connected with the pixel array; A plurality of first switching elements are disposed on the peripheral circuit area and located outside the pads, and each of the first switching elements is electrically connected to one of the pads, wherein each of the first switching elements having a gate, a source and a drain, the gate is electrically connected to the source, and the gate is electrically connected to the pad; and A plurality of second switching elements are disposed on the peripheral circuit area and located outside the pads, and each of the second switching elements is electrically connected to two adjacent first switching elements, wherein each of the second switching elements The two switching elements have a gate, a source and a drain, and the source is electrically connected to the drain of the adjacent first switching element, and the drain is connected to the adjacent first switching element The source is electrically connected. 2. The active device array substrate as claimed in claim 1, wherein the gate of each of the second switching elements is a floating gate. 3. The active device array substrate as claimed in claim 1, wherein the gate of each of the second switching elements is electrically connected to the source. 4. The active element array substrate as claimed in claim 1, further comprising a connection line disposed on the peripheral circuit area and located outside the first switching elements and the second switching elements , and the source of each of the second switching elements is electrically connected to the connection line, and the gate of each of the second switching elements is a floating gate. 5. The active device array substrate as claimed in claim 1, wherein the pads comprise data line pads or scan line pads. 6. An active element array substrate, comprising: A substrate with a peripheral circuit area and a display area; a pixel array configured on the display area; A plurality of pads are arranged on the peripheral circuit area and electrically connected with the pixel array; A plurality of first switching elements are disposed on the peripheral circuit area and located outside the pads, and each of the first switching elements is electrically connected to one of the pads, and each of the first switching elements having a gate, a source and a drain, wherein the gate is electrically connected to the source, the gate is electrically connected to the pad, and the drain is a floating drain; and A plurality of second switching elements are disposed on the peripheral circuit area and located outside the pads, and each of the second switching elements is electrically connected to one of the first switching elements, wherein each of the second switching elements The switch element has a gate, a source and a drain, and the drain is electrically connected to the source of the first switch element, and the source is a floating source, and the gate is a floating gate. 7. The active device array substrate as claimed in claim 6, wherein the pads comprise data line pads or scan line pads. 8. An active element array substrate, comprising: A substrate with a peripheral circuit area and a display area; a pixel array configured on the display area; A plurality of pads are arranged on the peripheral circuit area and electrically connected with the pixel array; A plurality of first switching elements are disposed on the peripheral circuit area and located outside the pads, and each of the first switching elements is electrically connected to one of the pads, wherein each of the first switching elements having a gate, a source and a drain, the gate is electrically connected to the source, and the gate is electrically connected to the pad; A plurality of second switching elements are disposed on the peripheral circuit area and located outside the pads, and each of the second switching elements is electrically connected to two adjacent first switching elements, wherein each of the second switching elements The two switching elements have a gate, a source and a drain, and the source is electrically connected to the drain of the adjacent first switching element, and the drain is connected to the adjacent first switching element The source is electrically connected to; and An external electrostatic discharge protection ring is disposed on the peripheral circuit area and located outside the first switching elements and the second switching elements, the gate of each second switching element is electrically connected to the external electrostatic discharge protective ring. 9. The active device array substrate as claimed in claim 8, wherein the source of each of the second switching elements is electrically connected to the outer ESD protection ring. 10 . The active device array substrate as claimed in claim 8 , wherein the gate of each of the second switching elements is electrically connected to the source. 11 . 11. The active element array substrate according to claim 8, further comprising a connection line disposed on the peripheral circuit area and located outside the first switching elements and the second switching elements and the inner side of the outer ESD protection ring, and the source of each of the second switching elements is electrically connected to the connection line, and the gate of each of the second switching elements is electrically connected to the outer ESD protection ring . 12. The active device array substrate as claimed in claim 8, wherein the pads comprise data line pads or scan line pads. 13. An active element array substrate, characterized in that it comprises: A substrate with a peripheral circuit area and a display area; a pixel array configured on the display area; A plurality of pads are arranged on the peripheral circuit area and electrically connected with the pixel array; A plurality of first switching elements are disposed on the peripheral circuit area and located outside the pads, and each of the first switching elements is electrically connected to one of the pads, and each of the first switching elements having a gate, a source and a drain, wherein the gate is electrically connected to the source, and the gate is electrically connected to the pad; A plurality of second switching elements are disposed on the peripheral circuit area and located outside the pads, and each of the second switching elements is electrically connected to one of the first switching elements, wherein each of the second switching elements The switching element has a gate, a source and a drain, and the drain is electrically connected to the source of the first switching element; and An external electrostatic discharge protection ring is arranged on the peripheral circuit area and located outside the first switching elements and the second switching elements, and the gate and the source of each second switching element are respectively electrically connected to the outer ESD protection ring, and the drains of each of the first switching elements are electrically connected to the outer ESD protection ring. 14. The active device array substrate as claimed in claim 13, wherein the pads comprise data line pads or scan line pads.

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