CN100573916C - Thin-film transistor and manufacture method thereof and display base plate with this thin-film transistor - Google Patents

Abstract

A kind of thin-film transistor comprises: be arranged on the semiconductor pattern on the substrate and have conduction or the semiconductor pattern part of dielectric features and be used to the non-proliferation part that prevents that metal ion from partly spreading along semiconductor pattern in semiconductor pattern part one side.First insulating barrier covers semiconductor pattern and has first contact hole that exposes semiconductor pattern part first area and second contact hole that exposes semiconductor pattern part second area.Grid is arranged on first insulating barrier.The second insulating barrier cover gate also has the 3rd contact hole that exposes the first area and the 4th contact hole that exposes second area.Source electrode is formed on second insulating barrier and is connected to the first area, and drain electrode is formed on second insulating barrier and connects second area.

Description

Thin film transistor, manufacturing method thereof, and display substrate having the same

This application claims the benefit of Korean Patent Application No. 43247/2006 filed on May 15, 2006 and Korean Patent Application No. 88989/2006 filed on September 14, 2006, the entire contents of which are incorporated herein by reference.

technical field

The invention relates to a thin film transistor, its manufacturing method and a display substrate with the thin film transistor.

Background technique

With the development of semiconductor devices such as thin film transistors (TFTs), information processing devices that can process more data in a short time have also been developed. Display devices for displaying processed data are also developing rapidly.

Examples of display devices include liquid crystal display devices (LCDs), organic light emitting devices (OLEDs), and plasma display panels (PDPs).

Typically display devices include TFTs to display full color images. In particular, display devices having low temperature polysilicon (LTPS) TFTs have recently been introduced.

In the LTP technology, a channel layer of a TFT used for an active matrix display device is formed of polysilicon having higher electron mobility than amorphous silicon. Also, since the driving circuit for controlling the display device can be directly formed on the display substrate, there is no need to arrange separate driving integrated circuits around the display panel. Therefore, the number of components is reduced compared to a display device using amorphous silicon. LTP's manufacturing technology can provide display devices featuring high durability, thin profile, high brightness and low power consumption.

In LTPS TFTs, polysilicon patterns are formed directly on the display panel, and gate electrodes are formed on the polysilicon patterns. Source and drain electrodes are formed on the polysilicon pattern. Contact holes are formed on the insulating layer between the polysilicon pattern and the gate. The source and drain are electrically connected to the polysilicon pattern through the contact holes.

However, the metal ions of the source and the drain diffuse from the source and the drain to the polysilicon pattern. In particular, after the passivation layer is formed on the substrate, an annealing process is performed on the passivation layer for removing hydrogen in the passivation layer. In this process, since the temperature of the annealing process is about 200° C. to 400° C., metal ions or atoms of the source and drain electrodes diffuse from the source and drain electrodes to the polysilicon pattern. Thus, the length of the polysilicon pattern is gradually reduced by the diffusion of metal ions. In this case, the performance of the TFT is drastically degraded and also reduces the display quality produced by the display device.

Contents of the invention

According to one embodiment of the present invention, as described herein with specificity and broadness, there is provided a thin film transistor comprising a semiconductor pattern disposed on a substrate. The semiconductor pattern includes a semiconductor pattern portion having conductive or insulating features, and an anti-diffusion portion close to one side of the semiconductor pattern portion and used to prevent metal ions from diffusing along the semiconductor pattern portion. The first insulating layer covers the semiconductor pattern and has a first contact hole exposing a first region of a portion of the semiconductor pattern. The second contact hole exposes a second region of the semiconductor pattern portion. The gate is on the first insulating layer and the second insulating layer covers the gate. The second insulating layer has a third contact hole exposing the first region and a fourth contact hole exposing the second region. The source is stacked on the second insulating layer and connected to the first region, and the drain is stacked on the second insulating layer and connected to the second region.

According to another aspect of the present invention, the present invention provides a method for manufacturing a thin film transistor, including forming a semiconductor layer on a substrate and patterning the semiconductor layer to form a semiconductor pattern. The semiconductor pattern includes a semiconductor pattern portion having conductive or insulating characteristics in which a diffusion preventing portion is formed to prevent metal ions from diffusing through the semiconductor pattern portion. A first insulating layer is formed to cover the semiconductor pattern and a gate is formed on the first insulating layer and spaced apart from the semiconductor pattern. A second insulating layer is formed to cover the gate. The first and second insulating layers are patterned to form a first insulating layer pattern and a second insulating layer pattern having contact holes exposing first and second regions of the semiconductor pattern portion. A source and a drain are formed on the second insulating layer pattern, wherein the source contacts the first region and the drain contacts the second region.

According to still another aspect of the present invention, the present invention provides a display substrate comprising a first substrate and a thin film transistor on the first substrate. The thin film transistor includes a semiconductor pattern portion having conductive or insulating features, and a gate electrode separated from the semiconductor pattern portion. The source is in electrical contact with the first region of the semiconductor pattern portion, and the drain is in electrical contact with the second region of the semiconductor pattern portion. The diffusion preventing portion protrudes from one side of the semiconductor pattern portion along the substrate, and is configured to prevent metal ions from diffusing from the source and the drain toward the center of the semiconductor pattern portion.

According to still another aspect of the present invention, the present invention provides a thin film transistor including a semiconductor pattern disposed on a substrate and having a source region and a drain region separated by a channel region. The anti-diffusion structure is adjacent to the semiconductor pattern. The gate is spaced apart from the channel region and separated by a first insulating layer. The second insulating layer covers the gate, and the source is stacked on the second insulating layer and is in contact with the source region. The drain is stacked on the second insulating layer and is in contact with the drain region. The diffusion prevention structure is configured to direct metal ions diffused from the source and drain away from the channel region.

It is to be understood that both the foregoing general description and the following detailed description of the present invention are schematic and explanatory and are intended to provide further explanation of the invention as claimed.

Description of drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate specific embodiments of the invention and together with the description explain the principle of the invention. In the attached picture:

1 is a plan view of a TFT according to an embodiment of the present invention;

Fig. 2 is a sectional view extracted along line I-I ' in Fig. 1;

3A is a plan view showing metal ion diffusion paths in the semiconductor pattern portion in FIG. 2 according to an embodiment;

3B is a plan view showing metal ion diffusion paths in the semiconductor pattern portion in FIG. 2 according to another embodiment;

4 is a plan view of a semiconductor layer formed by a method of manufacturing a TFT according to an embodiment of the present invention;

Fig. 5 is a sectional view taken along line II-II' in Fig. 4;

6 is a plan view illustrating a patterned polysilicon layer;

Fig. 7 is a sectional view taken along line III-III' in Fig. 6;

8 is a cross-sectional view of a first insulating layer covering the semiconductor pattern in FIG. 7;

9 is a cross-sectional view of a second insulating layer and an interlayer insulating layer covering the semiconductor pattern in FIG. 8;

10 is a cross-sectional view of an insulating interlayer pattern, a second insulating layer pattern, and a first insulating layer pattern formed by patterning an insulating interlayer, a second insulating layer, and a first insulating layer;

11 is a cross-sectional view of source and drain electrodes formed on the interlayer insulating layer pattern of FIG. 10;

12 is a cross-sectional view of a display device according to an embodiment of the present invention; and

FIG. 13 is a cross-sectional view of a display device according to another embodiment of the present invention.

In the drawings, the thicknesses of semiconductor patterns, first insulating layers, gates, second insulating layers, sources, drains, and other structures are exaggerated for clarity.

Detailed ways

As used herein, when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. When the semiconductor pattern, first insulating layer, gate, second insulating layer, source, drain and other structures are referred to as "first", "second", "third" and/or "fourth", They should not be understood as limitations on these members, but are used to distinguish semiconductor patterns, first insulating layers, gate electrodes, second insulating layers, source electrodes, drain electrodes, and other structures. Therefore, the terms "first", "second", "third" and "fourth" are interchangeable with respect to semiconductor patterns, first insulating layers, gates, second insulating layers, sources, drains and other structures. alternatively or interchangeably.

thin film transistor

1 is a plan view of a TFT according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line I-I' in FIG. 1 .

1 and 2, the TFT TR includes a semiconductor pattern SP formed on a substrate S, a first insulating layer pattern FILP, a gate GE, a second insulating layer SILP, a source SE and a drain DE.

The semiconductor pattern SP is disposed on the substrate S. As shown in FIG. In this embodiment, the semiconductor pattern SP includes polysilicon. Generally, the semiconductor pattern SP may have a sub-bell shape in a plan view.

For example, the sub-bell-shaped semiconductor pattern SP includes a semiconductor pattern part SPP and an anti-diffusion part EP.

In this embodiment, the semiconductor pattern part SPP has conductive or insulating properties according to the application/cut-off of the external voltage. In particular, the semiconductor pattern part SPP includes a first region FR, a second region SR, and a channel part CP. The first region FR and the second region SR correspond to the source SE and the drain DE, respectively.

In a plan view, the first region FR is disposed at a first end of the semiconductor pattern part SPP and the second region SR is disposed at a second end opposite to the first end. N-type or P-type impurities are doped into the first region FR and the second region SR of the semiconductor pattern portion SPP, thereby providing conductive characteristics.

In addition, the channel portion CP is sandwiched between the first region FR and the second region SR. The channel part CP has conductive or insulating properties according to application/cutoff of an external voltage.

The diffusion prevention part EP protrudes or extends from the semiconductor pattern part SPP. The diffusion prevention part EP prevents diffusion of metal ions from the source SE and the drain DE to the channel part CP of the semiconductor pattern part SPP. The source SE and the drain DE are electrically connected to the first region FR and the second region SR of the semiconductor pattern part SPP.

FIG. 3A is a plan view illustrating metal ion diffusion paths in the semiconductor pattern portion of FIG. 2 according to an embodiment.

Referring to FIG. 3A , the first regions FR of the semiconductor pattern part SPP correspond to the source SE and the drain DE, respectively.

When the first region FR and the second region SR are respectively connected to the source SE and the drain DE, metal ions from the source SE and the drain DE are mainly diffused from the first region FR and the second region SR to the channel portion CP . At this point, since the first region FR and the second region SR have conductive characteristics, even if metal ions diffuse from the source electrode SE and the drain electrode DE to the first and second regions FR and SR, it will not affect the first and second regions FR and SR. Electrical properties of two regions FR and SR. That is, the first and second regions FR and SR continuously maintain their conductive properties.

On the other hand, when metal ions from the source SE and the drain DE pass through the first region FR and the second region SR and then diffuse to the channel portion CP, the length of the channel portion CP decreases. Also, the channel portion CP may lose semiconductor characteristics due to the diffusion of metal ions from the source SE and the drain DE.

According to another technical solution of the present invention, the metal ions moving to the channel portion CP can be reduced by diffusing some metal ions to the anti-diffusion portion EP. For this purpose, the diffusion prevention part EP may be formed to protrude or extend along the side of the semiconductor pattern part SPP. Therefore, the diffusion prevention part EP is configured for conducting at least a part of the metal objects diffused from the source and the drain away from the channel part CP.

As shown in FIG. 3A, the diffusion preventing part EP may have a needle shape. In addition, the two needle-shaped diffusion preventing portions EP may be arranged parallel to each other like teeth of a fork.

In this way, when the diffusion prevention part EP is formed in the semiconductor pattern part SPP, the metal ions diffused to the channel part CP among the metal ions from the source SE and the drain DE diffuse to the diffusion prevention part EP. Accordingly, the diffusion directions of metal ions from the source SE and the drain DE are dispersed.

By dispersing the diffusion direction of metal ions from the source SE and the drain DE, the short circuit of the source SE and the drain DE, which is generated when the length of the channel part CP is reduced and/or the channel part CP is conductive, can be prevented.

Although the anti-diffusion part EP is shown here as a needle shape, according to other embodiments, the anti-diffusion part EP may have various shapes. For example, the anti-diffusion portion EP may be polygonal as shown in FIG. 3B. In the particular embodiment shown in FIG. 3B , the width W _EP of the anti-diffusion portion EP is greater than the corresponding width W _CP of the channel portion.

The diffusion preventing portion EP only close to the source SE may be selectively formed. Likewise, it is also possible to selectively form the anti-diffusion portion EP only close to the drain DE. In addition, the diffusion preventing portion EP may be formed close to both the source SE and the drain DE.

The diffusion prevention part EP may protrude in a direction parallel to the longitudinal direction of the rectangular semiconductor pattern part SPP so that metal ions may be diffused more efficiently. In addition, the diffusion prevention part EP may be formed in a radial direction with respect to the semiconductor pattern part SPP.

Referring to FIGS. 1 and 2 again, the first insulating layer pattern FILP is formed on the substrate S to cover the semiconductor pattern SP. The first insulating layer pattern FILP includes a first contact hole FCT exposing the first region FR and a second contact hole SCT exposing the second region SR. In this embodiment, since the first region FR and the second region SR are separated from each other by a predetermined distance, the first contact hole FCT and the second contact hole SCT are also separated from each other by a predetermined distance.

The gate electrode GE is formed on the first insulating layer pattern FILP. For example, the gate GE is disposed between the first contact hole FCT and the second contact hole SCT. The gate can be formed from aluminum, aluminum alloys, and aluminum-neodymium alloys.

The second insulating layer pattern SILP is formed on the first insulating layer pattern FILP such that the gate electrode GE is covered by the second insulating layer pattern SILP. The second insulating layer pattern SILP insulates the gate GE from the external conductor. In this embodiment, the second insulating layer pattern SILP has a third contact hole TCT exposing the first region FR and a fourth contact hole FOCT exposing the second region SR. The insulating interlayer pattern ILDP is formed on the second insulating layer pattern SILP.

The source SE is electrically connected to the first region FR through first and third contact holes FCT and TCT formed on the first and second insulating layer patterns FILP and SILP.

The drain DE is electrically connected to the second region SR through second and fourth contact holes SCT and FOCT formed on the first and second insulating layer patterns FILP and SILP, respectively.

Method of Manufacturing TFT

4 is a plan view of a semiconductor layer formed by a method of manufacturing a TFT according to an embodiment of the present invention. Fig. 5 is a sectional view taken along line II-II' in Fig. 4 .

Referring to FIGS. 4 and 5 , a polysilicon layer PL is formed on a substrate S. Referring to FIGS.

The formation of the polysilicon layer PL may include depositing an amorphous silicon layer on the substrate S and crystallizing the deposited amorphous silicon layer. The amorphous silicon layer can be formed using a chemical vapor deposition (CVD) process, and can be crystallized using a high-energy laser such as a YAG laser.

FIG. 6 is a plan view showing the patterned polysilicon layer, and FIG. 7 is a cross-sectional view taken along line III-III' in FIG. 6 .

6 and 7, after the polysilicon layer PL is formed on the substrate S, a photoresist pattern (not shown) is formed on the polysilicon layer PL.

In this embodiment, forming the photoresist pattern may include forming a photoresist film on the polysilicon layer PL, exposing the photoresist film using a pattern mask, and developing the exposed photoresist film. In addition, a photoresist pattern may be formed by disposing a photoresist substance on the polysilicon layer PL using an inkjet method.

Referring to FIGS. 6 and 7 , the polysilicon layer PL is etched using a photolithographic pattern as an etch mask, thereby forming a semiconductor pattern SP. Specifically, the polysilicon layer PL is patterned to form the semiconductor part SP having the semiconductor pattern part SPP and the diffusion prevention part EP. The semiconductor pattern part SPP has a first region FR, a second region SR, and a channel part CP.

In a plan view, the first region FR is formed at a first end of the semiconductor pattern SP, and the second region SR is formed at a second end opposite to the first end. The channel portion CP is sandwiched between the first region FR and the second region SR.

The anti-diffusion portion EP protrudes or extends from the semiconductor pattern SP along the substrate S opposite the first region FR and/or the second region SR.

In this embodiment, the diffusion preventing portion EP is needle-shaped and extends along the substrate S from the second region SR of the semiconductor pattern SP. At least one needle-shaped diffusion preventing portion EP is formed. The anti-diffusion parts EP may be arranged in parallel.

The diffusion prevention part EP extends from the side of the rectangular semiconductor pattern SP. For example, at least one anti-diffusion portion EP may extend in a direction parallel to a direction in which the semiconductor pattern SP is drawn. In addition, the diffusion preventing portion EP may be formed in a radial direction from a side of the semiconductor pattern SP with respect to the first and second regions FR and SR.

The diffusion prevention part EP may be formed on the semiconductor pattern SP opposite the first and second regions FR and SR. Likewise, the diffusion preventing part EP may be selectively formed on the semiconductor pattern part SPP with respect to the first region FR. In addition, the diffusion prevention part EP may be selectively formed at the semiconductor pattern part SPP with respect to the second region SR.

In FIG. 6, the diffusion prevention part EP is selectively formed in the second region SR electrically connected to the drain DE.

FIG. 8 is a cross-sectional view of a first insulating layer covering the semiconductor pattern in FIG. 7 .

Referring to FIG. 8 , after the semiconductor pattern SP having the semiconductor pattern part SPP and the diffusion prevention part EP is formed on the substrate S, a first insulating layer FIL is formed to cover the semiconductor pattern SP. The first insulating layer FIL may be formed of an organic layer, an oxide layer, or a nitride layer.

FIG. 9 is a cross-sectional view of a second insulating layer and an interlayer insulating layer covering the semiconductor pattern in FIG. 8 .

Referring to FIG. 9 , after the first insulating layer FIL is formed on the substrate S, the gate electrode GE and the storage electrode StE are formed on the first insulating layer FIL. The gate GE may be formed separately from the semiconductor pattern part SPP.

Then, n-type and p-type conductive impurities are doped into the semiconductor pattern SP by using the gate GE as a mask. The n-type or p-type conductive impurities are doped using an ion implantation process. Conductive impurities are doped into the first region FR and the second region SR not covered by the gate GE in the semiconductor pattern SP. Thus, portions opposite to the first region FR and the second region SR have conductive characteristics.

Then, a second insulating layer SILD is formed on the first insulating layer FIL to cover the gate GE. Likewise, an insulating interlayer ILP is formed on the second insulating layer SILD.

10 is a cross-sectional view of an interlayer insulating layer pattern, a second insulating layer pattern, and a first insulating layer pattern formed by patterning an interlayer insulating layer, a second insulating layer, and a first insulating layer.

Referring to FIG. 10, after the second insulating layer SILD and the interlayer insulating layer ILP are formed on the first insulating layer FIL, the interlayer insulating layer ILP, the second insulating layer SILD, and the first insulating layer FIL are patterned to form the first insulating layer. The layer pattern FILP, the second insulating layer pattern SILP, and the interlayer insulating layer pattern ILPP. The insulating layers FILP, SILP, and ILPP have a pair of contact holes CT1 and CT2 exposing the first and second regions FR and SR of the semiconductor pattern SP. In this embodiment, contact holes CT1 and CT2 are formed on both sides of the gate GE.

FIG. 11 is a cross-sectional view of source and drain electrodes formed on the insulating interlayer pattern of FIG. 10 .

Referring to FIG. 11 , a source/drain metal layer (not shown) is formed on the patterned interlayer insulating layer pattern ILPP. The source/drain electrodes may be formed of aluminum, aluminum alloy, chromium or chromium alloy.

Then, the source/drain metal layer is patterned using a photolithography process, thereby forming the source SE and the drain DE on the insulating interlayer pattern ILPP.

The source SE and the drain DE are electrically connected to the first region FR and the second region SR of the semiconductor pattern SP through the contact holes CT1 and CT2.

A large amount of metal ions from the source SE and the drain DE are supplied to the first region FR and the second region SR. However, the diffusion prevention part EP prevents metal ions from diffusing to the semiconductor pattern part SPP sandwiched between the first region FR and the second region SR. Therefore, it is possible to prevent the semiconductor pattern part SPP from being reduced in length, or to prevent the semiconductor pattern part SPP from being conductive.

display substrate

FIG. 12 is a cross-sectional view of a display device according to an embodiment of the present invention.

Referring to FIG. 12 , the display substrate includes a substrate S, TFTs, and pixels P. Referring to FIG.

The substrate S may be a transparent substrate having light transmittance similar to a glass plate.

TFTs are provided on the substrate S for transmitting signals to the pixels P for a predetermined time.

The TFT includes a semiconductor pattern SP, a first insulating layer pattern FILP, a gate GE, a second insulating layer pattern SILP, a source SE and a drain DE.

The semiconductor pattern SP formed of polysilicon has a rectangular sub-bell shape in a plan view, and the semiconductor pattern SP includes a semiconductor pattern part SPP and an anti-diffusion part EP protruding from the semiconductor pattern part SPP.

The semiconductor pattern part SPP has conductive or insulating properties according to application/disconnection of an external voltage. The semiconductor pattern part SPP includes a first region FR formed at a first end of the semiconductor pattern part SPP, a second region SR formed at a second end opposite to the first end, and a region sandwiched between the first region FR and the second region SR. Between the channel portion CP. In this embodiment, n-type or p-type impurities are doped in the first region FR and the second region SR. Accordingly, the semiconductor pattern part SPP has a conductive property with respect to the first region FR and the second region SR.

Meanwhile, the channel portion CP has semiconductor characteristics according to application/disconnection of an external voltage.

The diffusion prevention part EP protrudes from the semiconductor pattern part SPP by a predetermined length along the substrate S. As shown in FIG. The diffusion prevention part EP prevents metal ions from diffusing from the source SE and the drain DE to the channel part CP. The source SE and the drain DE are electrically connected to the first region FR and the second region SR of the semiconductor pattern part SPP, respectively.

The diffusion prevention part EP may protrude or extend from a side of the semiconductor pattern part SPP along the substrate S. Referring to FIG. Also, the anti-diffusion part EP may have a needle shape. In addition, at least two needle-shaped diffusion preventing portions EP are arranged in a fork shape.

The diffusion prevention part EP may be formed in the source SE and the drain DE. Likewise, the diffusion preventing portion EP only in the source electrode SE may be selectively formed. In addition, it is also possible to selectively form the diffusion preventing portion EP only in the drain DE.

In FIG. 12, the diffusion prevention part EP protrudes from the second region SR of the semiconductor pattern part SPP connected to the drain electrode DE.

The diffusion prevention part EP may protrude in a direction parallel to the direction in which the semiconductor pattern part SPP having a rectangular shape is drawn, so that metal ions may be more effectively diffused. In addition, the diffusion prevention part EP may be formed in a radial direction with respect to the semiconductor pattern part SPP.

Referring again to FIG. 12 , the first insulating layer pattern FILP is formed on the substrate S to cover the semiconductor pattern SP. The gate electrode GE and the storage electrode StE are formed on the first insulating layer pattern FILP.

The second insulating layer pattern SILP is formed on the first insulating layer pattern FILP to cover the gate GE. The insulating interlayer pattern ILDP is formed on the second insulating layer pattern SILP, and the passivation layer PL is formed on the insulating interlayer pattern ILDP.

The source SE is electrically connected to the first region FR through the third contact hole TCT and the first contact hole FCT, respectively. The drain DE is electrically connected to the second region SR through the fourth and second contact holes FOCT and SCT, respectively.

The pixel P is electrically connected to the drain DE. The pixel P may include a first electrode M1 connected to the drain DE. For example, the first electrode M1 serving as the pixel P may be a transparent electrode. The first electrode M1 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), or amorphous indium tin oxide (a-ITO).

The pixel P may further include an organic light emitting layer OL on the first electrode M1 and a second electrode M2. The organic light emitting layer OL emits light using current supplied from the first electrode M1 and the second electrode M2. In this embodiment, the second electrode M2 may be formed of a metal having a low work function, for example, aluminum or an aluminum alloy.

FIG. 13 is a cross-sectional view of a display device according to another embodiment of the present invention. In the illustrated embodiment, the pixel P includes a first electrode FE connected to the drain DE on the lower substrate S, a second electrode CE formed on the upper substrate S facing the lower substrate, so that the second electrode is connected to the first electrode CE. One electrode is opposite. The red color filter R, the black matrix B, and the green color filter layer G are located on the second substrate between the second electrode CE and the substrate. Although not shown in the figure, a blue color filter is also located on the upper substrate. A liquid crystal layer (not shown) is sandwiched between the first electrode and the second electrode. The first electrode and the second electrode located on both sides of the liquid crystal layer may be transparent electrodes.

In the embodiment of FIG. 13, except for the pixel structure, the structure on the lower substrate is similar to the structure of the substrate shown in FIG. 12 and described above. The TFT includes a semiconductor pattern SP, a first insulating layer pattern FILP, a gate GE, a second insulating layer pattern SILP, a source SE and a drain DE.

The semiconductor pattern SP includes a semiconductor pattern part SPP and an anti-diffusion part EP extending from the semiconductor pattern part SPP. The semiconductor pattern part SPP includes a first region FR formed at a first end of the semiconductor pattern part SPP, a second region SR formed at a second end opposite to the first end, and a region sandwiched between the first region FR and the second region SR. The channel portion CP. N-type or p-type impurities are doped into the first region FR and the second region SR. Accordingly, the semiconductor pattern portion SPP corresponding to the first region FR and the second region SR has a conductive property.

The first insulating layer pattern FILP is located on the substrate S and covers the semiconductor pattern SP. The gate electrode GE is formed on the first insulating layer pattern FILP. The second insulating layer pattern SILP is formed on the first insulating layer pattern FILP to cover the gate GE.

The insulating interlayer pattern ILDP is stacked on the second insulating layer SILP. The insulating interlayer pattern ILDP, the second insulating layer SILP, and the first insulating layer pattern FILP include contact holes FOCT and SCT exposing the second region SR, respectively. The insulating interlayer pattern ILDP, the second insulating layer SILP, and the first insulating layer pattern FILP further include contact holes TCT and FCT exposing the first region FR, respectively. The source electrode SE is electrically connected to the first region FR of the semiconductor pattern SP through the contact holes TCT and FCT. The drain DE is electrically connected to the second region SR of the semiconductor pattern SP through the contact holes FOCT and SCT.

The diffusion prevention part EP protrudes or extends from the second region SR of the semiconductor pattern part SPP, wherein the second region SR is connected to the drain DE. The structure and function of the anti-diffusion part EP are similar to those of the above-mentioned anti-diffusion part EP.

By forming the diffusion prevention part EP at the boundary of the semiconductor pattern, metal ions from electrodes electrically connected to the semiconductor pattern can be prevented from diffusing to the semiconductor pattern. Therefore, the present invention can prevent performance degradation of TFTs.

Obviously, those skilled in the art can make various modifications and improvements to the present invention without departing from the spirit or scope of the present invention. Thus, it is intended that the present invention cover all the modifications and improvements of this invention that come within the scope of the appended claims and their equivalents.

Claims (28)

1. A thin film transistor, comprising: a semiconductor pattern on a substrate, the semiconductor pattern including a source region, a drain region, a channel region and an anti-diffusion portion; a first insulating layer stacked on the semiconductor pattern; a gate stacked on the semiconductor pattern; a second insulating layer overlying the gate; and a source and a drain overlying the second insulating layer and connected to the source region and the drain region respectively, wherein the anti-diffusion part is used to reduce the diffusion of metal objects from the source or the drain to the channel region, wherein the anti-diffusion portion extends from the semiconductor pattern along a side of the substrate away from the semiconductor pattern, wherein the metal matter diffused to the channel region among the metal matter from the source electrode and the drain electrode diffuses toward the diffusion preventing portion, wherein the diffusion directions of the metal species from the source and the drain are dispersed, Wherein the metal substance contains one or both of metal ions or metal atoms. 2. The thin film transistor according to claim 1, wherein the semiconductor pattern further comprises conductive impurities doped in the source region and the drain region. 3. The thin film transistor according to claim 1, wherein the anti-diffusion portion comprises a structure having at least one elongated portion. 4. The thin film transistor according to claim 1, wherein the semiconductor pattern has a rectangular structure, and the diffusion preventing portion extends in a direction parallel to a longitudinal direction of the semiconductor pattern. 5. The thin film transistor according to claim 1, wherein the anti-diffusion portion comprises a structure close to the source. 6. The thin film transistor according to claim 1, wherein the anti-diffusion portion comprises a structure close to the drain. 7. The thin film transistor according to claim 1, wherein the anti-diffusion portion comprises a structure close to the source and the drain. 8. The thin film transistor according to claim 1, wherein the diffusion preventing portion includes a structure having a width greater than that of the channel region. 9. A method of manufacturing a thin film transistor, comprising: forming a semiconductor layer on the substrate; patterning the semiconductor layer to form a semiconductor pattern, the semiconductor pattern including a channel region and an anti-diffusion portion; forming a first insulating layer stacked on the semiconductor pattern; forming a gate stacked on the first insulating layer; forming a second insulating layer stacked on the gate; patterning the first insulating layer and the second insulating layer to form contact holes exposing first and second regions of the semiconductor pattern; and forming a source electrode and a drain electrode stacked on the second insulating layer; wherein the source is in contact with the first region and the drain is in contact with the second region, and wherein the anti-diffusion portion reduces diffusion of metal species from the source or the drain to the channel region, wherein the anti-diffusion portion extends from the semiconductor pattern along a side of the substrate away from the semiconductor pattern, wherein the metal matter diffused to the channel region among the metal matter from the source electrode and the drain electrode diffuses toward the diffusion preventing portion, wherein the diffusion directions of the metal species from the source and the drain are dispersed, Wherein the metal substance contains one or both of metal ions or metal atoms. 10. The method according to claim 9, further comprising implanting impurities into the first region and the second region of the semiconductor pattern. 11. The method according to claim 9, wherein the step of forming the semiconductor pattern with the anti-diffusion portion comprises forming at least one longitudinal structure. 12. The method according to claim 9, wherein the step of forming a semiconductor pattern comprises forming a structure having a rectangular shape in a plan view, and wherein the anti-diffusion portion is aligned with the longitudinal direction of the semiconductor pattern formed in parallel directions. 13. The method of claim 9, wherein the step of forming the semiconductor pattern with a diffusion preventing portion comprises forming the diffusion preventing portion close to the source. 14. The method of claim 9, wherein the step of forming the semiconductor pattern having a diffusion preventing portion comprises forming the diffusion preventing portion close to the drain. 15. The method according to claim 9, wherein the step of forming the semiconductor pattern having a diffusion preventing portion comprises forming the diffusion preventing portion close to the source and the drain. 16. The method of claim 9, wherein the step of forming a semiconductor pattern having a diffusion preventing portion comprises forming a structure having a width greater than that of the channel region. 17. A display substrate, comprising: first substrate; a thin film transistor stacked on the first substrate, the thin film transistor has a semiconductor pattern, a gate separated from the channel region of the semiconductor pattern, a source electrically connected to the first region of the semiconductor pattern, and a drain electrically connected to the second region of the semiconductor pattern; and an anti-diffusion portion of the semiconductor pattern extending along the first substrate and configured to reduce metal diffusion from the source or the drain to the channel region, wherein the metal matter diffused to the channel region among the metal matter from the source electrode and the drain electrode diffuses toward the diffusion preventing portion, wherein the diffusion directions of the metal species from the source and the drain are dispersed, Wherein the metal substance contains one or both of metal ions or metal atoms. 18. The display substrate according to claim 17, wherein the anti-diffusion portion comprises a structure having at least one elongated region. 19. The display substrate according to claim 17, wherein the anti-diffusion portion comprises a structure close to the source. 20. The display substrate according to claim 17, wherein the anti-diffusion portion comprises a structure close to the drain. 21. The display substrate according to claim 17, wherein the anti-diffusion portion comprises a structure close to the source and the drain. 22. The display substrate according to claim 17, wherein the anti-diffusion portion comprises a structure having a width greater than that of the channel region. 23. The display substrate according to claim 17, further comprising a pixel structure having a first electrode contacting one of the drain electrode or the source electrode and comprising a transparent and conductive material. 24. The display substrate according to claim 23, wherein the pixel structure further comprises: an organic light emitting layer on the first electrode; and A second electrode on the organic light emitting layer. 25. The display substrate according to claim 17, further comprising a second substrate facing the first substrate, wherein the second substrate comprises: a first electrode connected to the drain of the first substrate; a second electrode on the second substrate; and A liquid crystal layer sandwiched between the first substrate and the second substrate. 26. The display substrate according to claim 25, wherein the second substrate further comprises a color filter layer and a black matrix. 27. A thin film transistor comprising: a semiconductor pattern stacked on a substrate, the semiconductor pattern having a source region and a drain region separated by a channel region and an anti-diffusion structure; gates spaced apart from the channel region and separated from each other by a first insulating layer; a second insulating layer stacked on the gate; a source overlying the second insulating layer and in contact with the source region; and a drain overlying the second insulating layer and in contact with the drain region, wherein the anti-diffusion structure extends from the semiconductor pattern along a side of the substrate away from the semiconductor pattern, wherein the diffusion prevention structure is configured to direct at least a portion of metal diffused from the source and the drain away from the channel region, wherein the diffusion directions of the metal species from the source and the drain are dispersed, Wherein the metal substance contains one or both of metal ions or metal atoms. 28. The thin film transistor according to claim 27, wherein the diffusion prevention structure comprises an elongated structure having a plurality of regions extending in parallel.

Images