CN100492618C - Semiconductor element and manufacturing method thereof - Google Patents

Abstract

The present invention provides a semiconductor element and a method for manufacturing the same. The method mainly forms a thin film transistor structure with a lightly doped region of symmetrical length by isotropically etching a doped mask, thereby helping to improve the reliability and electrical performance of the element during operation. In addition, the method for manufacturing the semiconductor element uses the same mask process to form gate patterns of different thin film transistors, thereby effectively avoiding mask alignment errors that may occur when the above-mentioned element is manufactured using different mask processes, helping to improve the process yield and reducing the manufacturing cost.

Description

Semiconductor element and manufacturing method thereof

technical field

The present invention relates to a semiconductor device (device) and a manufacturing method thereof, and in particular to a structure of a thin film transistor applicable to a liquid crystal display panel and a manufacturing method thereof.

Background technique

Compared with amorphous silicon thin film transistors, polysilicon thin film transistors have the advantages of low power consumption and high electron mobility, so low temperature polysilicon thin film transistors have been widely used in large-sized liquid crystal displays.

Please refer to FIG. 1 , which is a schematic cross-sectional view of a low temperature polysilicon thin film transistor in the prior art. As shown in Figure 1, a buffer layer (buffer layer) 102 is formed on the substrate 100, and a polysilicon layer 110 is formed on the buffer layer 102, and a source region 112 is formed in the polysilicon layer 110 through a doping process , a drain region 114 and a channel region 116 , wherein the channel region 116 is located between the source region 112 and the drain region 114 .

Referring to FIG. 1 again, the gate insulating layer 120 covers the polysilicon layer 110 and the buffer layer 102 , and the gate 130 is disposed on the gate insulating layer 120 above the channel region 116 . The dielectric layer 140 covers the gate 130 and the gate insulating layer 120 , and contact openings 112 a and 114 a are formed in the dielectric layer 140 and the gate insulating layer 120 . In addition, the source metal layer 152 and the drain metal layer 154 are disposed on the dielectric layer 140, and the source metal layer 152 and the drain metal layer 154 are respectively connected to the source region 112 and the drain through the contact openings 112a and 114a. Region 114 is electrically connected.

It is worth mentioning that in order to reduce the lateral electric field during transistor operation to increase the reliability of device operation and reduce leakage current, a lightly doped drain is usually formed between the source region 112, the drain region 114 and the channel region 116. Pole (lightly doped drain, LDD) region 118 . In the prior art, when manufacturing a polysilicon thin film transistor with a lightly doped drain region 118, it usually needs to go through more than two mask (mask) processes (manufacturing), and perform more than two doping processes to form a doped drain region 118. Source region 112 /drain region 114 and lightly doped drain region 118 with different concentrations. However, the above method of fabricating the lightly doped drain region is not only complicated in process, but also easily causes difficulty in aligning the mask pattern, which makes the electrical performance of the manufactured thin film transistors inconsistent, which in turn affects the reliability of the product. .

Contents of the invention

The invention relates to a manufacturing method of a semiconductor element, which can reduce the number of masks in the process to reduce the cost and improve the yield of the process.

The present invention also relates to a semiconductor device with high reliability, which can provide better electrical performance.

In order to specifically describe the content of the present invention, a method for manufacturing a semiconductor element is proposed here. First, a substrate is provided, and a first semiconductor pattern and a second semiconductor pattern are formed on the substrate. Next, a gate insulating layer and a gate metal layer are sequentially formed on the substrate and cover the first semiconductor pattern and the second semiconductor pattern. Then, a first mask pattern and a second mask pattern are formed on the gate metal layer, wherein the first mask pattern is located above the first semiconductor pattern and correspondingly exposes a first source/electrode of the first semiconductor pattern. The drain region, and the second mask pattern is located above the second semiconductor pattern and correspondingly exposes a second source/drain region of the second semiconductor pattern. Then, the gate metal layer is patterned by using the first mask pattern and the second mask pattern as masks to form a first gate pattern and a second gate pattern respectively. Afterwards, the first source/drain region and the second source/drain region are subjected to the first mask pattern using the first mask pattern, the first gate pattern, the second mask pattern and the second gate pattern. Type ion doping makes the first source/drain region and the second source/drain region have the first conductivity type. Then, an etching process is performed on the first mask pattern and the second mask pattern to remove part of the outer walls of the first mask pattern and the second mask pattern, thereby exposing part of the first gate pattern and the second gate pattern. grid pattern. Next, etching the first gate pattern and the second gate pattern by using the first mask pattern and the second mask pattern after removing part of the outer wall as a mask to form a first gate pattern and a second gate pattern , and correspondingly expose a first lightly doped region inside the first source/drain region in the first semiconductor pattern and a second lightly doped region inside the second source/drain region in the second semiconductor pattern . Then, the first lightly doped region and the second lightly doped region are lightly doped with first-type ions using the first gate and the second gate as masks, so that the first lightly doped region and the second lightly doped region The region has a first conductivity type. Next, the first mask pattern and the second mask pattern are removed, and then a patterned mask layer is formed on the substrate, and the patterned mask layer corresponds to the exposed part of the second semiconductor pattern. Then, the second source/drain region and the second lightly doped region are counter-doped with second-type ions through the patterned mask layer, so that the second source/drain region and the second lightly doped region are counter-doped. The ion form of the second lightly doped region changes from the first conductivity type to the second conductivity type. Afterwards, the patterned mask layer is removed.

In an embodiment of the present invention, after removing the patterned mask layer, the above-mentioned manufacturing method of the semiconductor device further includes forming a dielectric layer on the gate insulating layer so as to cover the first gate and the second gate . Next, a plurality of first contact holes are formed in the dielectric layer and the gate insulating layer, and these first contact holes expose the first source/drain regions of the first semiconductor pattern and the second source/drain regions of the second semiconductor pattern. drain area. Then, respectively form a first source/drain contact metal and a second source/drain contact metal in the first contact window, wherein the first source/drain contact metal and the second source/drain contact The contact metals are respectively electrically connected to the corresponding first source/drain region and the second source/drain region.

In the present invention, after the above steps, a flat layer can be formed on the dielectric layer to cover the first source/drain contact metal and the second source/drain contact metal. Next, a second contact window is formed in the flat layer, and the second contact window exposes the first source/drain contact metal. Then, an electrode pattern is formed on the planar layer, wherein the electrode pattern is connected to the first source/drain contact metal through the second contact window.

In the present invention, after the above steps, a third mask pattern can be formed on the gate metal layer simultaneously when the first mask pattern and the second mask pattern are formed. Afterwards, when patterning the gate metal layer using the first mask pattern and the second mask pattern as a mask, simultaneously patterning the gate metal layer using the third mask pattern as a mask to form a lower layer pad. In addition, the present invention can further cover the underlying pads when the dielectric layer is formed. Next, when forming the first contact window, a third contact window is also formed in the dielectric layer to expose the underlying pad. Then, when forming the first source/drain contact metal and the second source/drain contact metal, an upper layer pad is formed in the third contact window, wherein the upper layer pad is connected to the lower layer pad. Furthermore, in the present invention, when the planar layer is formed, it can also make it cover the upper layer pads. Afterwards, when forming the second contact window, a fourth contact window is also formed in the planar layer, wherein the fourth contact window exposes the upper layer contact pad. Moreover, when forming the electrode pattern on the planar layer, a pad pattern is also formed in the fourth contact window, so that the pad pattern is connected to the upper pad.

The invention also proposes another manufacturing method of the semiconductor element. First, a substrate is provided, and a first semiconductor pattern and a second semiconductor pattern are formed on the substrate. Next, a second source/drain region of the second semiconductor pattern is doped with second type ions to make it have a second conductivity type. Then, a gate insulating layer is formed on the substrate to cover the first semiconductor pattern and the second semiconductor pattern. Next, a gate metal layer is formed on the gate insulating layer, and a first mask pattern and a second mask pattern are formed on the gate metal layer, wherein the first mask pattern is located above the first semiconductor pattern and corresponds to A first source/drain region of the first semiconductor pattern is exposed, and the second mask pattern is located above the second semiconductor pattern and correspondingly exposes a portion of the second source/drain region of the second semiconductor pattern. Then, the gate metal layer is patterned by using the first mask pattern and the second mask pattern as masks to form a first gate pattern and a second gate pattern respectively. Afterwards, the first source/drain region is doped with first-type ions using the first mask pattern and the first gate pattern as a mask, so that the first source/drain region has the first conductivity type , while the second source/drain region maintains the second conductivity type. Next, an etching process is performed on the first mask pattern and the second mask pattern to remove part of the thickness of the outer wall of the first mask pattern and the second mask pattern, thereby exposing part of the first gate pattern and the second mask pattern. second gate pattern. Then, using the first mask pattern and the second mask pattern as masks to etch the first gate pattern and the second gate pattern to form a first gate and a second gate, wherein the first gate The electrodes correspond to expose a lightly doped region inside the first source/drain region in the first semiconductor pattern, and the second gate covers a channel region and part of the second source/drain region of the second semiconductor pattern . Next, the lightly doped region is lightly doped with the first type of ions using the first gate as a mask, so that the lightly doped region has the first conductivity type, while the second source/drain region still maintains the second conductivity type. Afterwards, the first mask pattern and the second mask pattern are removed.

In an embodiment of the present invention, the above-mentioned manufacturing method of the semiconductor device further includes forming a dielectric layer on the gate insulating layer so as to cover the first gate and the second gate. Next, a plurality of first contact windows are formed in the dielectric layer and the gate insulating layer, and these first contact windows expose the first source/drain region and the second source/drain region. Then, respectively form a first source/drain contact metal and a second source/drain contact metal in the first contact window, wherein the first source/drain contact metal and the second source/drain contact The contact metals are respectively connected to the corresponding first source/drain regions and the second source/drain regions.

In the present invention, after the above steps, a flat layer can also be formed on the dielectric layer to cover the source/drain contact metal. Next, a second contact window is formed in the flat layer, and the second contact window exposes the first source/drain contact metal. Then, an electrode pattern is formed on the planar layer, wherein the electrode pattern is connected to the first source/drain contact metal through the second contact window.

In an embodiment of the present invention, in the above-mentioned manufacturing method of the semiconductor device, when forming the first mask pattern and the second mask pattern, a third mask pattern can be formed on the gate metal layer at the same time. Moreover, when patterning the gate metal layer using the first mask pattern and the second mask pattern as a mask, the gate metal layer is patterned using the third mask pattern as a mask at the same time, so as to form a lower layer pad.

In addition, in the present invention, when the above-mentioned dielectric layer is formed, it can also cover the underlying pads. Next, when forming the first contact window, a third contact window is also formed in the dielectric layer to expose the underlying pad. After that, while forming the first source/drain contact metal and the second source/drain contact metal, an upper layer pad is formed in the third contact window so that the upper layer pad is connected to the lower layer pad.

In addition, in the present invention, when the above flat layer is formed, it can also cover the upper layer pads. Moreover, when forming the second contact window, a fourth contact window is also formed in the planar layer, and the fourth contact window exposes the upper layer contact pad. Next, when forming the electrode pattern on the planar layer, a pad pattern is also formed in the fourth contact window, so that the pad pattern is connected to the pad of the upper layer.

In an embodiment of the present invention, the step of doping the first source/drain region with first-type ions further includes performing first-type ion doping on part of the second source/drain region, and The part of the second source/drain region still needs to maintain the second conductivity type. In addition, when lightly doping the lightly doped region with first-type ions, part of the second source/drain region can also be lightly doped with first-type ions at the same time, and this part of the second source/drain region The drain region still needs to maintain the second conductivity type.

In an embodiment of the present invention, the above-mentioned manufacturing method of the semiconductor device further includes forming a third semiconductor pattern on the substrate at the same time when forming the first semiconductor pattern and the second semiconductor pattern. Next, when the second source/drain region is doped with the second type of ions, the third semiconductor pattern is also doped with the second type of ions so that it also has the second conductivity type.

In addition, when forming the first mask pattern and the second mask pattern, a fourth mask pattern can also be formed on the gate metal layer at the same time, wherein the fourth mask pattern passes above the above-mentioned third semiconductor pattern. Next, when the gate metal layer is patterned by using the first mask pattern and the second mask pattern as a mask, the gate metal layer is patterned by using the fourth mask pattern as a mask at the same time to form a metal common layer. electrodes, wherein the metal common electrode passes above the third semiconductor pattern. In addition, when forming the dielectric layer, it also covers the metal common electrode, and when forming the first contact window, a fifth contact window is also formed in the dielectric layer to expose part of the third semiconductor pattern. Then, when forming the first source/drain contact metal, the first source/drain contact metal is also connected to the third semiconductor pattern through the fifth contact window.

The etching process used in the above-mentioned embodiments is, for example, a dry etching process. In more detail, the etching process is, for example, etching the first mask pattern and the second mask pattern by oxygen plasma (plasma).

In addition, the substrate used in the above-mentioned embodiments is, for example, a glass substrate, and the material of the first semiconductor pattern or the second semiconductor pattern is, for example, polysilicon. In addition, the above-mentioned first-type ions are, for example, N-type ions, and the second-type ions are, for example, P-type ions. In addition, the material of the first mask pattern, the second mask pattern or the patterned mask layer is, for example, photoresist.

The present invention further provides a semiconductor device, which mainly includes a substrate, a first semiconductor pattern, a second semiconductor pattern, a gate insulating layer, a first gate and a second gate. The first semiconductor pattern is disposed on the substrate, and has a first channel area, a first source/drain area located on both sides of the first channel area, and a first source/drain area located between the first channel area and the first source/drain area A lightly doped region is spaced and symmetrical to each other, wherein the first source/drain region and the lightly doped region have a first conductivity type. In addition, the second semiconductor pattern is disposed on the substrate, and the second semiconductor pattern has a second channel region and a second source/drain region located on both sides of the second channel region, wherein the second source/drain region Has a second conductivity type. The gate insulating layer is disposed on the substrate and covers the first semiconductor pattern and the second semiconductor pattern. In addition, the first gate is configured on the gate insulating layer, and the first gate is located above the first semiconductor pattern and correspondingly exposes the first source/drain region and the lightly doped region. The second gate is disposed on the gate insulating layer, and the second gate is located above the second semiconductor pattern and covers the second channel region and part of the second source/drain region.

In an embodiment of the present invention, the above semiconductor device further includes a dielectric layer, a first source/drain contact metal and a second source/drain contact metal. The dielectric layer is disposed on the gate insulating layer and covers the first gate and the second gate, and the dielectric layer has a plurality of first source/drain regions and second source/drain regions exposed. One touches the window. In addition, the first source/drain contact metal and the second source/drain contact metal are disposed in the first contact window and electrically connected to the corresponding first source/drain region and the second source respectively. electrode/drain region.

The above-mentioned semiconductor device may further include a planar layer and an electrode pattern. The planar layer is disposed on the dielectric layer and covers the first source/drain contact metal and the second source/drain contact metal, and has a second contact window in the planar layer to expose the first source/drain Extreme contact with metal. In addition, the electrode pattern is disposed on the planar layer and coupled to the first source/drain contact metal via the second contact window.

In an embodiment of the present invention, the above-mentioned semiconductor device further includes a lower layer pad disposed on the gate insulating layer. In addition, the above-mentioned dielectric layer may also have a third contact window for exposing the underlying pad.

In an embodiment of the present invention, the above-mentioned semiconductor device further includes an upper layer pad disposed in the third contact window and connected to the lower layer pad. In addition, the above-mentioned planar layer may also have a fourth contact window for exposing the upper layer contact pads. A pad pattern can also be formed in the fourth contact window to connect the upper layer pads.

In an embodiment of the present invention, the above-mentioned semiconductor device further includes a third semiconductor pattern disposed on the substrate and covered by the gate insulating layer, and the third semiconductor pattern has the second conductivity type. In addition, the third semiconductor pattern is coupled to the first source/drain region, for example.

In addition, the semiconductor device of the present invention may further include a metal common electrode, which is disposed on the gate insulating layer and passes above the above-mentioned third semiconductor pattern.

The aforementioned substrate is, for example, a glass substrate, and the material of the first semiconductor pattern or the second semiconductor pattern is, for example, polysilicon. In addition, the first conductivity type is, for example, N type, and the second conductivity type is, for example, P type.

Based on the above, the lightly doped region in the thin film transistor structure formed by the present invention has a symmetrical length, thus helping to improve the reliability and electrical performance of the device during operation. In addition, since the present invention uses the same masking process to form gate patterns of different thin film transistors, metal common electrodes, lower layer pads and other components, it can effectively avoid the problems that may occur when the above-mentioned components are manufactured with different masking processes in the prior art. Mask alignment errors help to improve process yield and reduce manufacturing costs.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a low temperature polysilicon thin film transistor in the prior art.

2A-2O illustrate a manufacturing method of a semiconductor device according to an embodiment of the present invention.

FIG. 3A illustrates the peripheral circuit layout of the prior art liquid crystal display panel.

FIG. 3B illustrates a peripheral circuit layout of the present invention.

4A-4J illustrate a manufacturing method of a semiconductor device according to another embodiment of the present invention.

Figure number:

100: substrate 102: buffer layer

110: polysilicon layer 112: source region

112a: Contact window opening 114: Drain region

114a: Contact window opening 116: Passage area

118: Lightly doped drain region 120: Gate insulating layer

130: Grid 140: Dielectric layer

152: Source metal layer 154: Drain metal layer

202: Substrate 212: The first semiconductor pattern

212a: first source/drain region 212b: first lightly doped region

212c: the first channel area 214: the second semiconductor pattern

214a: second source/drain region 214b: second lightly doped region

214c: Second channel region 220: Gate insulating layer

230: Gate metal layer 232: First gate pattern

232a: the first grid 234: the second grid pattern

234a: second grid 236: lower pad

242: The first mask pattern 244: The second mask pattern

246: The third mask pattern 250: Patterned mask layer

260: Dielectric layer 262: First contact window

264: Third contact window 272: First source/drain contact metal

274: Second source/drain contact metal 276: Upper pad

280: flat layer 282: second contact window

284: The fourth contact window 290: Electrode pattern

292: Pad Pattern L1: Length

300: Inverter 310: PTFT

320: NTFT 330a, 330b, 332: Gate metal pattern

402: Substrate 404: Photoresist layer

412: first semiconductor pattern 412a: first source/drain region

412b: lightly doped region 412c: first channel region

414: second semiconductor pattern 414a: second source/drain region

414c: the second channel area 418: the third semiconductor pattern

420: Gate insulation layer 430: Gate metal layer

432: The first grid pattern 432a: The first grid

434: Second grid pattern 434a: Second grid

436: Lower pad 438: Metal common electrode

442: The first mask pattern 444: The second mask pattern

446: The third mask pattern 448: The fourth mask pattern

460: dielectric layer 462: first contact window

464: The third contact window 466: The fifth contact window

472: First source/drain contact metal 474: Second source/drain contact metal

476: Upper pad 480: Flat layer

482: Second contact window 484: Fourth contact window

490: electrode pattern 492: pad pattern

L2: length

Detailed ways

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows.

The manufacturing method of the semiconductor element of the present invention can be used in a liquid crystal display panel to manufacture a polysilicon thin film transistor as an active element in a pixel, and based on its process characteristics, it can simultaneously integrate the production of related components around the panel and external pads . The following embodiments will be described by fabricating at least a P-type thin film transistor (PTFT), an N-type thin film transistor (NTFT), and external pads or storage capacitors simultaneously on the panel. However, it is only for example and not intended to limit the scope of application of the present invention. For example, similar device structures and processes in the field of semiconductors can adopt the technology proposed by the present invention to obtain better process effects and product quality.

Please refer to FIGS. 2A˜2O , which illustrate a manufacturing method of a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 2A , a substrate 202 is provided, and a first semiconductor pattern 212 and a second semiconductor pattern 214 are formed on the substrate 202 . In this embodiment, the substrate 202 can be a glass substrate, a quartz substrate, a plastic substrate or other applicable transparent substrates, and the first semiconductor pattern 212 and the second semiconductor pattern 214 formed thereon are, for example, formed on the substrate 202 first. A layer of amorphous silicon layer, and perform laser annealing (laser annealing) process to make the amorphous silicon layer into a polysilicon layer, and then pattern the polysilicon layer to form. The laser light source applicable to the laser annealing process here may be an excimer laser, a solid-state laser, or a diode-pumped solid state laser (DPSS) and the like.

It is worth mentioning that, the present invention can form a buffer layer on the substrate 202 first, to improve the adhesion between the substrate 202 and the subsequently formed polysilicon layer, and can avoid the metal in the substrate 200 Ions (such as sodium) diffuse to contaminate the polysilicon layer. In addition, before the laser annealing process, the amorphous silicon layer can be dehydrogenated to avoid hydrogen explosion caused by the hydrogen contained in the amorphous silicon layer being heated during the laser annealing process. . Those skilled in the art should be able to understand the above content based on the existing technical level, and this embodiment will not disclose it in detail.

Next, as shown in FIG. 2B, a gate insulating layer 220 and a gate metal layer 230 are sequentially formed on the substrate 202, so that the gate insulating layer 220 and the gate metal layer 230 cover the first semiconductor pattern 212 and the second semiconductor pattern. 214. The method for forming the gate insulating layer 220 is, for example, chemical vapor deposition (CVD), and the material of the gate insulating layer 220 is, for example, silicon nitride (SiN) or silicon oxide (SiO). In addition, the material of the gate metal layer 230 is, for example, chromium (Cr), aluminum (Al), copper (Cu), molybdenum (Mo) or other low-resistance metals, which are formed by sputtering or other thin film deposition processes, for example. .

Then, as shown in FIG. 2C, a first mask pattern 242 and a second mask pattern 244 are formed on the gate metal layer 230, wherein the first mask pattern 242 is located above the first semiconductor pattern 212 and correspondingly exposed. A first source/drain region 212a on both sides of the first semiconductor pattern 212, and the second mask pattern 244 is located above the second semiconductor pattern 214 and correspondingly exposes a second source on both sides of the second semiconductor pattern 214 /drain region 214a. The method of forming the first mask pattern 242 and the second mask pattern 244 is, for example, performing photolithography processes such as photoresist coating, exposure, and development on the gate metal layer 230 . It is worth mentioning that this embodiment discloses a double-gate thin film transistor structure to avoid problems such as entanglement effects and leakage currents. Therefore, the formed first mask pattern 242 can have two parts, both of which are located above the first semiconductor pattern 212 . In addition, if external pads are to be formed on the substrate 202 , in this embodiment, a third mask pattern 246 can be formed on the gate metal layer 230 at the same time in this step.

Next, as shown in FIG. 2D , the gate metal layer 230 is patterned by using the first mask pattern 242 , the second mask pattern 244 and the third mask pattern 246 as masks to form a metal layer on the gate insulating layer 220 respectively. A first gate pattern 232 , a second gate pattern 234 and a lower pad 236 . The patterning here is achieved, for example, by performing a dry or wet etching process.

Then, as shown in FIG. 2E , using the first mask pattern 242 and its corresponding first gate pattern 232 , the second mask pattern 244 and its corresponding second gate pattern 234 as a mask to pair the first source/drain The electrode region 212a and the second source/drain region 214a are doped with first-type ions, so that the first source/drain region 212a and the second source/drain region 214a have the first conductivity type. The first-type ion doping performed here is, for example, N-type ion doping to implant N-type dopants, such as phosphorus ions, into the first source/drain region 212 a and the second source/drain region 214 a. Meanwhile, a first channel region 212c and a second channel region 214c may be defined in the first semiconductor pattern 212 and the second semiconductor pattern 214 under the first gate pattern 232 and the second gate pattern 234 respectively.

Afterwards, as shown in FIG. 2F , an etching process is performed on the first mask pattern 242 and the second mask pattern 244 to remove part of the outer walls of the first mask pattern 242 and the second mask pattern 244, thereby exposing Part of the first gate pattern 232 and the second gate pattern 234 . In addition, if the third mask pattern 246 is formed simultaneously in the aforementioned steps, the third mask pattern 246 will also be etched together. The etching process performed in this step is, for example, a dry etching process. In more detail, it can etch the first mask pattern 242 and the second mask pattern 244 by plasma (such as oxygen plasma). And the third mask pattern 246, also known as photoresist ashing (ashing) process, is characterized in that the first mask pattern 242, the second mask pattern 244 and the third mask pattern 246 can be processed etc. to etch. For example, after the first mask pattern 242 is etched, in addition to the thickness reduction, both sides of the first mask pattern 242 are also reduced by the same amount of length L1.

Next, as shown in FIG. 2G , the first gate pattern 232 and the second gate pattern 234 are etched using the first mask pattern 242 and the second mask pattern 244 as masks to form a first gate pattern 232 a and a first gate pattern 232 a. A second gate 234a, and correspondingly exposes a first lightly doped region 212b inside the first source/drain region 212a in the first semiconductor pattern 212 and a second source/drain in the second semiconductor pattern 214 A second lightly doped region 214b inside the region 214a. In addition, if the third mask pattern 246 is formed and etched simultaneously in the preceding step, this step further includes etching part of the underlying pad 236 using the third mask pattern 246 as a mask. It is worth noting that since the first mask pattern 242, the second mask pattern 244 and the third mask pattern 246 are etched isotropically, the left and right sides thereof are reduced symmetrically to the inside, so the exposed first mask pattern 242 The first lightly doped region 212b and the second lightly doped region 214b also have symmetrical lengths.

Then, as shown in FIG. 2H , the first lightly doped region 212b and the second lightly doped region 214b are lightly doped with the first type of ions by using the first gate 232a and the second gate 234a as masks, so that the first lightly doped region 212b and the second lightly doped region 214b A lightly doped region 212b and a second lightly doped region 214b have the first conductivity type. Corresponding to the above-mentioned first-type ion doping is N-type ion doping, the first-type ion light doping performed here is also N-type ion doping, the difference is that the N-type dopant with a lower concentration is used, For example phosphorus ions.

In this embodiment, the first lightly doped region 212b with a symmetrical length is manufactured through the steps of FIGS. electrical performance.

Next, as shown in FIG. 2I , the first mask pattern and the second mask pattern are removed, and another patterned mask layer 250 is formed on the substrate 202 . The patterned mask layer 250 correspondingly exposes the second semiconductor pattern 214 . The method of forming the patterned mask layer 250 is, for example, performing photolithography processes such as photoresist coating, exposure, and development on the gate insulating layer 220 .

And, as shown in FIG. 2J , the second source/drain region 214a and the second lightly doped region 214b in the second semiconductor pattern 214 are oppositely doped with second-type ions via the patterned mask layer 250 ( counter-doping), so that the ion form of the second source/drain region 214a and the second lightly doped region 214b changes from the first conductivity type to the second conductivity type. Compared with the above-mentioned first conductivity type being N-type, the second conductivity type here is P-type, so the second-type ion doping performed is, for example, P-type ion doping, so that the second source P-type dopants, such as boron ions, are implanted into the drain region 214a and the second lightly doped region 214b. It is worth mentioning that, according to the experimental results, in order to obtain a better opposite doping effect and successfully transform the second source/drain region 214a and the second lightly doped region 214b into the second conductivity type, the first The ion implantation depth of the second-type ion doping should be similar to that of the aforementioned first-type ion doping.

Afterwards, the patterned mask layer 250 is removed to obtain the structure of the semiconductor device as shown in FIG. 2K . The first source/drain region 212a, the first lightly doped region 212b, the first channel region 212c and the first gate 232a can form an NTFT structure, while the second source/drain region 214a, the second lightly doped The impurity region 214b, the second channel region 214c and the second gate 234a can form a PTFT structure. Wherein, the first lightly doped region 212b has a symmetrical length, which helps to improve the reliability and electrical performance of the device during operation.

On the other hand, the present invention uses the same mask process to form the first gate pattern 232, the second gate pattern 234 and the lower layer pad 236, and then uses the opposite doping technology to form different types of thin film transistors, such as PTFT Compared with the NTFT, it has the advantages of simple process, low cost and high yield rate compared with the prior art. For more details, please refer to FIG. 3A which shows the peripheral circuit layout of the liquid crystal display panel in the prior art. What is shown here is, for example, a CMOS structure inverter (Inverter) 300. Since the prior art manufactures the inverter 300, two different mask processes are used to manufacture the PTFT 310 and the NTFT 320 respectively, so in The gate metal patterns 330a and 330b defined in the two masking processes may not be connected due to the alignment error of the masks, which affects the process yield and increases the complexity of the process. Furthermore, due to the consideration of the alignment error of the mask, part of the layoutable area must be sacrificed in order to provide a reasonable process margin when designing the layout of the front-end components. On the contrary, referring to a peripheral circuit layout of the present invention shown in FIG. 3B, if the manufacturing method of the above-mentioned embodiment of the present invention is adopted, the gate metal pattern 332 of the PTFT 310 and the NTFT 320 can be defined simultaneously through the same mask process. Therefore, the above-mentioned problems can be overcome, and the number of masks required for the process can be reduced, the cost can be reduced, and the yield rate of the process can be improved.

Following the steps shown in FIG. 2K , in this embodiment, subsequent steps can be performed to form components such as source/drain contact metals, pixel electrodes, and upper layer pads.

Please refer to FIG. 2L, after removing the patterned mask layer 250, a dielectric layer 260 can be formed on the gate insulating layer 220 to cover the first gate 232a, the second gate 234a and the aforementioned optional formation. The lower layer pads 236 . Moreover, a plurality of first contact holes 262 and third contact holes 264 are formed in the dielectric layer 260 and the gate insulating layer 220 . The first contact window 262 exposes the first source/drain region 212a of the first semiconductor pattern 212 and the second source/drain region 214a of the second semiconductor pattern 214, and the third contact window 264 exposes the underlying pad. 236. The method of forming the first contact hole 262 and the third contact hole 264 is, for example, performing a photolithography process and a subsequent etching process on the dielectric layer 260 .

After that, as shown in FIG. 2M, a first source/drain contact metal 272 and a second source/drain contact metal 274 are formed in the first contact window 262, so that the first source/drain contacts The metal 272 and the second source/drain contact metal 274 are electrically connected to the corresponding first source/drain region 212a and the second source/drain region 214a respectively. Moreover, an upper layer pad 276 can be optionally formed in the third contact window 264 corresponding to the lower layer pad 236 at the same time, so that the upper layer pad 276 and the lower layer pad 236 are connected to each other. The method of forming the first source/drain contact metal 272, the second source/drain contact metal 274 and the upper layer contact pad 276 is, for example, to first form a source/drain metal layer (not shown) on the dielectric layer 260. shown), and then the source/drain metal layer is formed by photolithography and etching processes. In addition, the source/drain metal layer can also be made of chromium (Cr), aluminum (Al), copper (Cu), molybdenum (Mo) or other low-resistance metals, such as through sputtering or other thin film deposition processes to form.

Next, as shown in FIG. 2N, a flat layer 280 is formed on the dielectric layer 260 to cover the first source/drain contact metal 272, the second source/drain contact metal 274, and optionally formed upper layers. Pad 276. And, a second contact window 282 and a fourth contact window 284 are formed in the flat layer 280, wherein the second contact window 282 exposes the first source/drain contact metal 272, and the fourth contact window 284 exposes the upper layer Pad 276. The method of forming the second contact hole 282 and the fourth contact hole 284 is, for example, performing a photolithography process and a subsequent etching process on the dielectric layer 280 .

After that, as shown in FIG. 2O, an electrode pattern 290 and a pad pattern 292 are formed on the planar layer 280, wherein the electrode pattern 290 is connected to the first source/drain contact metal 272 through the second contact window 282, as a A pixel electrode (pixel electrode), and the pad pattern 292 is connected to the upper layer pad 276 through the fourth contact window 284 to serve as an external pad. The method for forming the electrode pattern 290 and the pad pattern 292 here is, for example, firstly forming a conductive material layer (not shown) on the planar layer 280 , and then performing an etching process on the conductive material layer. The conductive material layer can be made of transparent conductive materials such as indium tin oxide (Indium Tin Oxide, ITO) and indium zinc oxide (Indium Zinc Oxide, IZO), which are formed, for example, by sputtering or other thin film deposition processes. form.

So far, the present invention has roughly completed a semiconductor element structure applicable to a liquid crystal display panel including a pixel region and a peripheral circuit region. The content of the present invention will be described with other embodiments below. Please refer to FIGS. 4A-4J , which illustrate a manufacturing method of a semiconductor device according to another embodiment of the present invention. It is worth mentioning that the detailed implementation of some processes in the following embodiments is similar to that disclosed in the foregoing embodiments, so please refer to the foregoing embodiments for related descriptions, and will not be repeated hereafter.

First, as shown in FIG. 4A, a substrate 402 is provided, a first semiconductor pattern 412 and a second semiconductor pattern 414 are formed on the substrate 402, and a second source/drain region 414a of the second semiconductor pattern 414 is provided. The second type ion doping is performed to make it have the second conductivity type. In this embodiment, the substrate 402 can also be a glass substrate, a quartz substrate, a plastic substrate, or other applicable transparent substrates, and the first semiconductor pattern 412 and the second semiconductor pattern 414 are, for example, formed by a laser annealing process to form a polysilicon layer, and then obtained by performing the patterning step. In addition, the step of doping the second source/drain region 414 a with the second type of ions is achieved, for example, by using a photoresist layer 404 as a mask. In addition, this manufacturing method can also selectively form storage capacitors and external pads on the substrate 402, so in this step, a third semiconductor pattern 418 can be additionally formed on the substrate 402, and the third semiconductor pattern 418 can be formed simultaneously. The second type ion doping is performed to make it have the second conductivity type. The second-type ion doping performed here is, for example, P-type ion doping, so as to implant P-type dopants, such as boron ions, into the second source/drain region 414 a and the third semiconductor pattern 418 . Meanwhile, a second channel region 414 c can be defined in the second semiconductor pattern 414 .

Next, as shown in FIG. 4B , a gate insulating layer 420 is formed on the substrate 402 to cover the first semiconductor pattern 412 , the second semiconductor pattern 414 and the third semiconductor pattern 418 . Furthermore, a gate metal layer 430 is formed on the gate insulating layer 420 . The method of forming the gate insulating layer 420 is, for example, chemical vapor deposition (CVD), and the material of the gate insulating layer 420 is, for example, silicon nitride (SiN) or silicon oxide (SiO). In addition, the material of the gate metal layer 430 is, for example, chromium (Cr), aluminum (Al), copper (Cu), molybdenum (Mo) or other low-resistance metals, which are formed by sputtering or other thin film deposition processes, for example. .

After that, as shown in FIG. 4C, a first mask pattern 442 and a second mask pattern 444 are formed on the gate metal layer 430, wherein the first mask pattern 442 is located above the first semiconductor pattern 412 and correspondingly exposed. A first source/drain region 412a of the first semiconductor pattern 412 is exposed, and the second mask pattern 444 is located above the second semiconductor pattern 414 and correspondingly exposes a portion of the second source/drain of the second semiconductor pattern 414. polar region 414a. In addition, if the storage capacitor and the external pads are selected to be formed as mentioned above, a third mask pattern 446 and a fourth mask pattern 448 can be additionally formed on the gate metal layer 430 in this step, wherein the fourth mask pattern Pattern 448 passes over third semiconductor pattern 418 . The method of forming the first mask pattern 442 and the second mask pattern 444 is, for example, performing photolithography processes such as photoresist coating, exposure, and development on the gate metal layer 430 .

Next, as shown in FIG. 4D , the gate metal layer 430 is patterned by using the first mask pattern 442 , the second mask pattern 444 , the third mask pattern 446 and the fourth mask pattern 448 as masks, respectively. A first gate pattern 432 , a second gate pattern 434 , a lower layer pad 436 and a metal common electrode 438 passing through the third semiconductor pattern 418 are formed. Afterwards, the first source/drain region 412a is doped with first type ions by using the first mask pattern 442 and the first gate pattern 432 as a mask, so that the first source/drain region 412a has The first conductivity type, while the second source/drain region 414a maintains the second conductivity type. The patterning action here is achieved, for example, by performing a dry or wet etching process, and the first-type ion doping is, for example, N-type ion doping, so that the first source/drain region N-type dopants, such as phosphorous ions, are implanted into 412a. It should be noted that since the second source/drain region 414a must still maintain the original second conductivity type after this step, the concentration of the P-type dopant in the aforementioned second-type ion doping should be It is greater than the N-type dopant concentration of the first-type ion doping here. Meanwhile, a first channel region 412 c can be defined in the first semiconductor pattern 412 under the first gate pattern 432 .

Then, as shown in FIG. 4E , an etching process is performed on the first mask pattern 442 and the second mask pattern 444 to remove part of the thickness of the outer wall of the first mask pattern 442 and the second mask pattern 444 , and then Parts of the first gate pattern 432 and the second gate pattern 434 are exposed. After that, the first gate pattern 432 and the second gate pattern 434 are etched by using the first mask pattern 442 and the second mask pattern 444 after removing part of the outer wall as a mask to form a first gate pattern. 432a and a second gate 434a, wherein the first gate 432a correspondingly exposes a lightly doped region 412b inside the first source/drain region 412a in the first semiconductor pattern 412, and the second gate 434a covers the first A channel region 414c of the second semiconductor pattern 414 and a part of the second source/drain region 414b. In addition, if the third mask pattern 446 and the fourth mask pattern 448 are formed simultaneously in the aforementioned steps, the third mask pattern 446 and the fourth mask pattern 448 will also be etched together. The etching process performed in this step is, for example, a dry etching process. More specifically, it can etch the first mask pattern 442 and the second mask pattern 444 by plasma (such as oxygen plasma). , the third mask pattern 446 and the fourth mask pattern 448, also known as the photoresist ashing (ashing) process, which is characterized in that the first mask pattern 442, the second mask pattern 444, the second mask pattern The third mask pattern 446 and the fourth mask pattern 448 are etched isotropically. For example, after the first mask pattern 442 is etched, in addition to the thickness reduction, both sides of the first mask pattern 442 are also reduced by an equal amount of length L2. In addition, the etching step also includes using the third mask pattern 446 and the fourth mask pattern 448 as masks to etch part of the lower layer pad 436 and part of the metal common electrode 438 . It should be noted that since the first mask pattern 442 is etched isotropically, the left and right sides of the first mask pattern 442 are reduced symmetrically to the inside, so the exposed lightly doped region 412b also has a symmetrical length.

Next, as shown in FIG. 4F , the lightly doped region 412b is lightly doped with first-type ions by using the first mask pattern 442 and the corresponding first gate 432a as a mask, so that the lightly doped region 412b has first conductivity type. The first-type light doping performed here is, for example, also N-type ion doping, except that a lower concentration of N-type dopant, such as phosphorous ions, is used. As mentioned above, the second source/drain region 414a still needs to maintain the second conductivity type after this step. It is worth mentioning that after the second mask pattern 444 and the second gate pattern 434 below it are formed (as shown in FIG. 4C ), they still have to go through a subsequent etching process (as shown in FIG. 4E ). , and the thickness and lateral length of the etched part. Therefore, in order to ensure that the second channel region 434c below the second gate pattern 434 will not be doped with the first type of ions in this step, the second mask pattern 444, the second gate pattern must be designed in the design of the film pattern. The electrode pattern 434 and the subsequently formed second gate 434a maintain the state of covering the second channel region 434c in the aforementioned process.

In this way, the first source/drain region 412a, the lightly doped region 412b, the first channel region 412c and the first gate 432a can form an NTFT structure, while the second source/drain region 414a, the second channel The region 414c and the second gate 434a can form a PTFT structure.

Then, as shown in FIG. 4G , the first mask pattern 442 and the second mask pattern 444 , the third mask pattern 446 and the fourth mask pattern 448 are removed to form a dielectric layer 460 on the gate insulating layer 420 , so that it covers the first gate 432a, the second gate 434b, and the optionally formed lower pad 436 and the metal common electrode 438 described above. Furthermore, a plurality of first contact holes 462 , a third contact hole 464 and a fifth contact hole 466 are formed in the dielectric layer 460 and the gate insulating layer 420 . The first contact window 462 exposes the first source/drain region 412a of the first semiconductor pattern 412 and the second source/drain region 414a of the second semiconductor pattern 414, and the third contact window 464 exposes the underlying pad 436 , and the fifth contact window 466 exposes part of the third semiconductor pattern 418 . Wherein, the method of forming the first contact window 462 , the third contact window 464 and the fifth contact window 466 is, for example, performing a photolithography process and a subsequent etching process on the dielectric layer 460 .

After that, as shown in FIG. 4H, a first source/drain contact metal 472, a second source/drain contact metal 474 are formed in the first contact window 462, and an upper layer contact pad 476 is formed in the second In the three-contact window 464, the first source/drain contact metal 472 and the second source/drain contact metal 474 are electrically connected to the corresponding first source/drain region 412a and the second source respectively. /drain region 414 a , and the upper layer pad 476 is connected to the lower layer pad 436 through the third contact window 464 . In addition, the first source/drain contact metal 472 is also connected to the third semiconductor pattern 418 through the fifth contact window 466 to make the first source/drain region 412a and the third semiconductor pattern 418 conduct with each other. In this way, when the display signal is introduced into the third semiconductor pattern 418 from the first source/drain region 412a, a storage capacitor will be formed between the third semiconductor pattern 418 and the metal common electrode 438 above it. The method for forming the first source/drain contact metal 472, the second source/drain contact metal 474 and the upper layer contact pad 476 is, for example, to first form a source/drain metal layer (not shown) on the dielectric layer 460. shown), and then the source/drain metal layer is formed by photolithography and etching processes. In addition, the source/drain metal layer can also be made of chromium (Cr), aluminum (Al), copper (Cu), molybdenum (Mo) or other low-resistance metals, such as through sputtering or other thin film deposition processes to form.

Next, as shown in FIG. 4I, a flat layer 480 is formed on the dielectric layer 460 to cover the first source/drain contact metal 472, the second source/drain contact metal 474, and optionally formed upper layers. Pad 476. Moreover, a second contact window 482 and a fourth contact window 484 are formed in the flat layer 480, wherein the second contact window 482 exposes the first source/drain contact metal 472, and the fourth contact window 484 exposes the upper layer Pad 476. The method of forming the second contact hole 482 and the fourth contact hole 484 is, for example, performing a photolithography process on the dielectric layer 480 .

Afterwards, as shown in FIG. 4J , an electrode pattern 490 and a pad pattern 492 are formed on the planar layer 480, wherein the electrode pattern 490 is connected to the first source/drain contact metal 472 through the second contact window 482 as a A pixel electrode (pixel electrode), and the pad pattern 492 is connected to the upper layer pad 476 through the fourth contact window 484 to serve as an external pad. Here, the method of forming the electrode pattern 490 and the pad pattern 492 is, for example, firstly forming a conductive material layer (not shown) on the planar layer 480 , and then performing an etching process on the conductive material layer. The conductive material layer can be made of transparent conductive materials such as indium tin oxide (Indium Tin Oxide, ITO) and indium zinc oxide (Indium Zinc Oxide, IZO), which are formed, for example, by sputtering or other thin film deposition processes. form.

The lightly doped regions in the thin film transistor structure formed in the above embodiments also have symmetrical lengths, thus helping to improve the reliability and electrical performance of the device during operation. In addition, since the above embodiment also uses the same mask process to form the gate patterns of different thin film transistors, metal common electrodes, lower layer pads and other components, it can effectively avoid the possibility of making the above components with different mask processes in the prior art. The generated mask alignment error helps to improve the yield rate of the process, and can save the layout area of the substrate that must be sacrificed in the layout design of the front-end components in the prior art, thereby reducing the production cost.

On the other hand, the above-mentioned embodiment can integrate the production of the storage capacitor. When the first semiconductor pattern and the second semiconductor pattern are formed, the third semiconductor pattern that can be used as the lower electrode of the storage capacitor is formed together, and the third semiconductor pattern is processed. Ion doping makes it conductive. Therefore, the semiconductor element formed in this embodiment can be matched with a good storage capacitor, and when applied to a liquid crystal display panel, it will help to improve the display quality of the liquid crystal display panel.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (28)

1. the manufacture method of a semiconductor element is characterized in that, this method comprises:

One substrate is provided;

Form one first semiconductor pattern and one second semiconductor pattern on this substrate;

One second source/drain regions to this second semiconductor pattern carries out the second type ion doping, makes it have second conductivity;

Form a gate insulation layer on described substrate, make it cover described first semiconductor pattern and second semiconductor pattern;

Form a gate metal layer on described gate insulation layer;

Form one first mask pattern and one second mask pattern on described gate metal layer, wherein this first mask pattern is positioned at described first semiconductor pattern top and corresponding one first source/drain regions that exposes this first semiconductor pattern, and described second mask pattern is positioned at described second semiconductor pattern top and corresponding second source/drain regions that exposes the part of described second semiconductor pattern;

With described first mask pattern and second mask pattern is that mask comes the described gate metal layer of patterning, and forms a first grid pattern and a second grid pattern respectively;

With described first mask pattern and described first grid pattern is that mask comes described first source/drain regions is carried out the first type ion doping, make described first source/drain regions have first conductivity, and described second source/drain regions is kept second conductivity;

Described first mask pattern and second mask pattern are carried out an etching technics,, and then expose the described first grid pattern and the second grid pattern of part with the outer wall of the segment thickness that removes described first mask pattern and second mask pattern;

With described first mask pattern and second mask pattern is that mask comes described first grid pattern of etching and second grid pattern, to form a first grid and a second grid, wherein said first grid correspondence exposes a light doping section of the first source/drain regions inboard described in described first semiconductor pattern, and described second grid covers a channel region of described second semiconductor pattern and described second source/drain regions of part;

With described first grid is that mask comes described light doping section is carried out the first type ion light dope, make this light doping section have first conductivity, and described second source/drain regions is still kept second conductivity; And

Remove described first mask pattern and second mask pattern;

Wherein, described etching technics is a dry etch process.

2. the manufacture method of semiconductor element as claimed in claim 1 is characterized in that, this method also comprises:

Form a dielectric layer on described gate insulation layer, make it cover described first grid and second grid;

Form a plurality of first contact holes in described dielectric layer and described gate insulation layer, described first contact hole exposes described first source/drain regions and second source/drain regions; And

Form one first source/drain contacting metal and one second source/drain contacting metal in described first contact hole, this first source/drain contacting metal and the described second source/drain contacting metal are connected respectively to pairing first source/drain regions and second source/drain regions.

3. the manufacture method of semiconductor element as claimed in claim 2 is characterized in that, this method also comprises:

Form a flatness layer on described dielectric layer, make it cover described source/drain contacting metal;

Form one second contact hole in described flatness layer, this second contact hole exposes the described first source/drain contacting metal; And

Form an electrode pattern on described flatness layer, wherein this electrode pattern is connected to the described first source/drain contacting metal via described second contact hole.

4. the manufacture method of semiconductor element as claimed in claim 3 is characterized in that, this method also comprises:

When forming described first mask pattern and second mask pattern, form one the 3rd mask pattern simultaneously on described gate metal layer; And

Being mask when coming the described gate metal layer of patterning, be that mask comes the described gate metal layer of patterning with described the 3rd mask pattern simultaneously, with described first mask pattern and second mask pattern to form lower floor's connection pad.

5. the manufacture method of semiconductor element as claimed in claim 4 is characterized in that, this method also comprises:

When forming described dielectric layer, make it cover described lower floor connection pad;

When forming described first contact hole, in described dielectric layer, form one the 3rd contact hole, to expose described lower floor connection pad; And

When forming the described first source/drain contacting metal and the second source/drain contacting metal, form a upper strata connection pad in described the 3rd contact hole, this upper strata connection pad connects described lower floor connection pad.

6. the manufacture method of semiconductor element as claimed in claim 5 is characterized in that, this method also comprises:

When forming described flatness layer, make it cover described upper strata connection pad;

When forming described second contact hole, form one the 4th contact hole in described flatness layer, the 4th contact hole exposes described upper strata connection pad; And when forming described electrode pattern, forming a connection pad pattern in described the 4th contact hole in described flatness layer, this connection pad pattern connects described upper strata connection pad.

7. the manufacture method of semiconductor element as claimed in claim 1, it is characterized in that the step that described first source/drain regions is carried out the first type ion doping also comprises second source/drain regions that described second source/drain regions to part carries out the first type ion doping and described part still must keep second conductivity.

8. the manufacture method of semiconductor element as claimed in claim 1, it is characterized in that, described light doping section is carried out described second source/drain regions that the lightly doped step of the first type ion also comprises part carry out the first type ion light dope, and second source/drain regions of this part still must be kept second conductivity.

9. the manufacture method of semiconductor element as claimed in claim 1 is characterized in that, this method also comprises:

When forming described first semiconductor pattern and second semiconductor pattern, form one the 3rd semiconductor pattern simultaneously on described substrate;

When described second source/drain regions is carried out the second type ion doping, simultaneously described the 3rd semiconductor pattern is carried out the second type ion doping, make it have second conductivity equally;

When forming described first mask pattern and second mask pattern, form one the 4th mask pattern simultaneously on described gate metal layer, wherein the 4th mask pattern is by described the 3rd semiconductor pattern top;

Be that mask is when coming the described gate metal layer of patterning with described first mask pattern and second mask pattern, be that mask comes this gate metal layer of patterning with described the 4th mask pattern simultaneously, to form a metal common electrode, wherein this metal common electrode is by described the 3rd semiconductor pattern top;

When forming described dielectric layer, make it cover described metal common electrode;

When forming described first contact hole, in described dielectric layer, form one the 5th contact hole, to expose described metal common electrode; And

When forming the described first source/drain contacting metal, make the described first source/drain contacting metal connect described the 3rd semiconductor pattern via described the 5th contact hole.

10. the manufacture method of semiconductor element as claimed in claim 1 is characterized in that, described etching technics is to come described first mask pattern of etching and second mask pattern by oxygen plasma.

11. the manufacture method of semiconductor element as claimed in claim 1 is characterized in that, described substrate comprises glass substrate.

12. the manufacture method of semiconductor element as claimed in claim 1 is characterized in that, the material of described first semiconductor pattern or second semiconductor pattern comprises polysilicon.

13. the manufacture method of semiconductor element as claimed in claim 1 is characterized in that, the described first type ion comprises N type ion, and the described second type ion comprises P type ion.

14. the manufacture method of semiconductor element as claimed in claim 1 is characterized in that, the material of described first mask pattern or second mask pattern comprises photoresistance.

15. a semiconductor element is characterized in that, described element comprises:

One substrate;

One first semiconductor pattern, be disposed on this substrate, and this first semiconductor pattern has a first passage district, at one first source/drain regions of both sides, described first passage district and between this first passage district and this first source/drain regions and a symmetrical light doping section, wherein this first source/drain regions and described light doping section have first conductivity;

One second semiconductor pattern is disposed on the described substrate, and this second semiconductor pattern has a second channel district and be positioned at one second source/drain regions of both sides, described second channel district, and wherein this second source/drain regions has second conductivity;

One gate insulation layer is disposed on the described substrate, and covers described first semiconductor pattern and second semiconductor pattern;

One first grid is disposed on the described gate insulation layer, and wherein this first grid is positioned at described first semiconductor pattern top and correspondence exposes described first source/drain regions and light doping section; And

One second grid is disposed on the described gate insulation layer, and wherein this second grid is positioned at described second semiconductor pattern top and covers described second channel district and described second source/drain regions of part.

16. semiconductor element as claimed in claim 15 is characterized in that, described element also comprises:

One dielectric layer, it is disposed on the described gate insulation layer and covers described first grid and second grid, and has a plurality of first contact holes that expose described first source/drain regions and second source/drain regions in the described dielectric layer; And

One first source/drain contacting metal and one second source/drain contacting metal, it is disposed in described first contact hole, and is electrically connected to pairing described first source/drain regions and second source/drain regions respectively.

17. semiconductor element as claimed in claim 16 is characterized in that, described element also comprises:

One flatness layer, it is disposed on the described dielectric layer and covers the described first source/drain contacting metal and the described second source/drain contacting metal, and has one second contact hole in this flatness layer, to expose the described first source/drain contacting metal; And

One electrode pattern, it is disposed on the described flatness layer and via described second contact hole and is couple to the described first source/drain contacting metal.

18. semiconductor element as claimed in claim 17 is characterized in that, described element also comprises lower floor's connection pad, and it is disposed on the described gate insulation layer.

19. semiconductor element as claimed in claim 18 is characterized in that, also has one the 3rd contact hole in the described dielectric layer, in order to expose described lower floor connection pad.

20. semiconductor element as claimed in claim 19 is characterized in that, described element also comprises a upper strata connection pad, and it is disposed in described the 3rd contact hole, and connects described lower floor connection pad.

21. semiconductor element as claimed in claim 20 is characterized in that, also has one the 4th contact hole in the described flatness layer, in order to expose described upper strata connection pad.

22. semiconductor element as claimed in claim 21 is characterized in that, described element also comprises a connection pad pattern, and it is disposed in described the 4th contact hole, and connects described upper strata connection pad.

23. semiconductor element as claimed in claim 15, it is characterized in that, described element also comprises one the 3rd semiconductor pattern, and it is disposed on the described substrate and by described gate insulation layer and covers, and described the 3rd semiconductor pattern has second conductivity.

24. semiconductor element as claimed in claim 23 is characterized in that, described the 3rd semiconductor pattern is coupled to described first source/drain regions.

25. semiconductor element as claimed in claim 24 is characterized in that, described element also comprises a metal common electrode, and it is disposed on the described gate insulation layer and passes through described the 3rd semiconductor pattern top.

26. semiconductor element as claimed in claim 15 is characterized in that, described substrate comprises glass substrate.

27. semiconductor element as claimed in claim 15 is characterized in that, the material of described first semiconductor pattern or described second semiconductor pattern comprises polysilicon.

28. semiconductor element as claimed in claim 15 is characterized in that, described first conductivity comprises the N type, and described second conductivity comprises the P type.

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