CN100565803C - Method that is used for producing the semiconductor devices and epitaxial growth device - Google Patents

Abstract

The method for manufacturing a semiconductor device includes the steps of: forming a trench (4) on a main surface of a silicon substrate (1); forming a first epitaxial film (20) on the main surface and in the trench (4); and A second epitaxial film (21) is formed on the first epitaxial film (20). The step of forming the first epitaxial film (20) has a first process condition of a first growth rate of the first epitaxial film (20). The step of forming the second epitaxial film (21) has a second process condition of a second growth rate of the second epitaxial film (21). The second growth rate is greater than the first growth rate.

Description

Method for manufacturing semiconductor device and epitaxial growth apparatus

field of invention

The invention relates to a method for manufacturing a semiconductor device and an epitaxial growth device.

Background of the invention

A MOS transistor (SJ-MOS transistor) of a super junction structure (SJ-MOS transistor) is known as an element for realizing a low on-resistance compared to an existing MOS transistor (for example, disclosed in JP-A-H09-266311 up). This SJ-MOS transistor is characterized by a repeating pn column structure in the drift layer region. Various methods have been proposed to form this pn column. Among these methods, a method of epitaxially growing the inside of the trench by LP-CVD after forming the trench in the substrate is known as a method capable of making the concentration distribution uniform in the depth direction.

In trench filling using normal LP-CVD, the growth rate is greater in the opening than in the bottom. Therefore, voids are easily formed in the groove by blocking the opening portion. The trench opening portion can be limited to be previously blocked by simultaneously flowing a silane-based gas and an etching gas (for example, disclosed in JP-A-2004-273742).

However, the step difference caused by the trench is formed after the trench-fill epitaxial process. Therefore, epitaxial growth for planarization and polishing must be performed.

Also, regarding trenches etched in a halide gas atmosphere in formation of a p/n column structure by trench-fill epitaxial growth, it has been proposed that the opening portion of the trench can be prevented from being damaged by using a mixed growth system of etching gas and silane-based gas. Block early.

Thus, blocking of the trench opening portion can be suppressed by the action of the etching gas, but causes a decrease in the growth rate. Therefore, there is a need for a technique for increasing the growth rate without relying on the blocking that suppresses the opening portion of the trench described above.

Contents of the invention

In view of the above problems, an object of the present disclosure is to provide a method for manufacturing a semiconductor device. Another object of the present disclosure is to provide an epitaxial growth apparatus.

According to a first aspect of the present disclosure, a method for manufacturing a semiconductor device includes the steps of: forming a trench on a main surface of a silicon substrate; forming a first epitaxial film on the surface and in the trench, thereby filling the trench with the first epitaxial film; and forming a second epitaxial film on the first epitaxial film by using another process condition. The step of forming the first epitaxial film has a first process condition of growing the first epitaxial film on the main surface of the silicon substrate at a first growth rate. The step of forming the second epitaxial film has a second process condition of growing the second epitaxial film on the main surface of the silicon substrate at a second growth rate. The second growth rate of the second epitaxial film is greater than the first growth rate of the first epitaxial film.

In the above method, since the halide gas is used to form the first epitaxial film, the first epitaxial film in the trench has substantially no voids. Also, since the second growth rate of the second epitaxial film is greater than the first growth rate of the first epitaxial film, the complete production time of the device, that is, the manufacturing time is improved. Therefore, the surface of the device is simply planarized.

According to a second aspect of the present disclosure, a method of manufacturing a semiconductor device includes the steps of: forming a trench on a main surface of a silicon substrate; and forming an epitaxial film in the trench by using a mixed gas of a silicon source gas and a halide gas , thereby filling the trench with the epitaxial film. In the step of forming the epitaxial film, the epitaxial film is not formed on the main surface of the silicon substrate, and the step of forming the epitaxial film is completed when the top surface of the epitaxial film in the trench and the main surface of the silicon substrate are on the same plane.

In the above method, since the halide gas is used to form the epitaxial film, the epitaxial film in the trench has substantially no voids. Also, the surface of the device is simply planarized.

According to a third aspect of the present disclosure, a method of manufacturing a semiconductor device includes the steps of: forming a mask for a trench on a main surface of a silicon substrate; etching the main surface of the silicon substrate through an opening passing through the mask forming a groove on the main surface of the silicon substrate; forming an epitaxial film in the groove of the silicon substrate with a mask by using a mixed gas of a silicon source gas and a halide gas, thereby filling the groove with the epitaxial film; and This mask is removed after the step of forming an epitaxial film. In the step of forming the epitaxial film, the epitaxial film is not formed on the mask, and the step of forming the epitaxial film is completed when the top surface of the epitaxial film in the trench and the main surface of the silicon substrate are on the same plane.

In the above method, since the halide gas is used to form the epitaxial film, the epitaxial film in the trench has substantially no voids. Also, the surface of the device is simply planarized.

According to a fourth aspect of the present disclosure, a method for manufacturing a semiconductor device includes the steps of: forming a mask for a trench on a main surface of a silicon substrate; etching the main surface of the silicon substrate by opening through the mask Grooves are formed on the main surface of the silicon substrate; an epitaxial film is formed in the groove of the silicon substrate with a mask by using a mixed gas of a silicon source gas and a halide gas, thereby filling the trench with the epitaxial film, wherein the epitaxial film Not formed on the mask, and when the top surface of the epitaxial film in the trench is higher than the main surface of the silicon substrate, the step of forming the epitaxial film is completed; the main surface side of the silicon substrate is polished by using the mask as a polishing stop layer the surface of the epitaxial film on the surface of the epitaxial film, thereby flattening the main surface side of the silicon substrate; and removing the mask after the step of polishing the surface of the epitaxial film.

In the above method, since the halide gas is used to form the epitaxial film, the epitaxial film in the trench has substantially no voids. Also, the surface of the device is simply planarized.

According to a fifth aspect of the present disclosure, a method for manufacturing a semiconductor device includes the steps of: forming a mask for a trench on a main surface of a silicon substrate; etching the main surface of the silicon substrate by opening through the mask Forming a trench on the main surface of a silicon substrate; forming an epitaxial film on a mask and in the trench by using a mixture of silicon source gas and halide gas, thereby filling the trench with the epitaxial film; by using a mask as a polishing stop layer to polish the surface of the epitaxial film on the main surface side of the silicon substrate, thereby planarizing the main surface side of the silicon substrate; and removing the mask after the step of polishing the surface of the epitaxial film.

In the above method, since the halide gas is used to form the epitaxial film, the epitaxial film in the trench has substantially no voids. Also, the surface of the device is simply planarized.

According to a sixth aspect of the present disclosure, an epitaxial growth apparatus includes: a chamber; a chuck provided in the chamber and holding a silicon substrate having a main surface on which grooves are provided; a first gas flow controller for a gas flow rate of a source gas, wherein a silicon source gas is introduced into the chamber to form an epitaxial film on a silicon substrate; a second gas flow controller for controlling a gas flow rate of a halide source gas, wherein Introduction of halide gas into the chamber; temperature controller for controlling the process temperature in the chamber; pressure controller for controlling the process pressure in the chamber; high temperature for monitoring the surface temperature of the epitaxial film on the silicon substrate in the chamber and a master controller for controlling at least one of the first airflow controller, the second airflow controller, the temperature controller and the pressure controller based on the output signal of the pyrometer. The main controller switches at least one of the gas flow rate of the silicon source gas, the gas flow rate of the halide source gas, the process temperature, and the process pressure to increase the epitaxial film when the output signal of the pyrometer becomes substantially constant at a predetermined monitored surface temperature. growth rate.

By using the above apparatus, an epitaxial film is formed in the trench substantially without voids. Also, the surface of the device is simply planarized.

According to a seventh aspect of the present disclosure, a method for manufacturing a semiconductor device includes the steps of: forming a first epitaxial film of a first conductivity type on a silicon substrate of a first conductivity type; forming a plurality of epitaxial films in the first epitaxial film trenches, wherein the first epitaxial film between adjacent two trenches has a width greater than the width of the trenches; a second epitaxial film of the second conductivity type is formed on the first epitaxial film and in the trenches, thereby The trench is filled with a second epitaxial film having a higher impurity concentration than the first epitaxial film. The step of forming the second epitaxial film includes a final step in which a mixed gas of a silicon source gas and a halide gas is used to form the second epitaxial film.

In the above method, the opening of the trench is not covered with the second epitaxial film before the trench is filled with the second epitaxial film. Also, since the first epitaxial film has a width greater than the width of the trenches between adjacent two trenches, the growth rate of the second epitaxial film is increased.

Description of drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description made with reference to the accompanying drawings. In the attached picture:

1 is a cross-sectional view showing a vertical type trench gate MOSFET;

2A to 2C are cross-sectional views illustrating a method for manufacturing the MOSFET shown in FIG. 1;

3A to 3C are cross-sectional views illustrating a method for manufacturing the MOSFET shown in FIG. 1;

4 is a schematic diagram showing an epitaxial growth device;

Figure 5 is a graph showing the relationship between process temperature and growth rate ratio;

FIG. 6 is a timing diagram showing a MOSFET manufacturing process;

FIG. 7A is a plan view showing a wafer, and FIG. 7B is a cross-sectional view showing the wafer shown in FIG. 7A;

FIG. 8A is a plan view showing another wafer, and FIG. 8B is a cross-sectional view showing the wafer shown in FIG. 8A;

9 is a cross-sectional view illustrating movement of atoms during an epitaxial growth process;

10 is a graph showing the presence or absence of voids in the epitaxial film considering the relationship between the HCl standard flow rate and the epitaxial film growth rate in the case of an aspect ratio of 5;

11 is a graph showing the presence or absence of voids in the epitaxial film considering the relationship between the HCl standard flow rate and the epitaxial film growth rate in the case of an aspect ratio of 15;

12 is a graph showing the presence or absence of voids in the epitaxial film considering the relationship between the HCl standard flow rate and the epitaxial film growth rate in the case of an aspect ratio of 25;

FIG. 13 is another timing diagram showing the MOSFET manufacturing process;

14 is yet another timing diagram illustrating the MOSFET manufacturing process;

15A and 15B are cross-sectional views illustrating an epitaxial growth process;

16A to 16E are cross-sectional views illustrating another method of manufacturing a MOSFET;

FIG. 17 is a timing chart showing a manufacturing process of the MOSFET shown in FIGS. 16A to 16E;

18A to 18F are cross-sectional views illustrating still another method of manufacturing a MOSFET;

FIG. 19 is a timing chart of the MOSFET manufacturing process shown in FIGS. 18A to 18F;

20A to 20F are cross-sectional views illustrating still another method of manufacturing a MOSFET;

FIG. 21 is a timing chart showing a manufacturing process of the MOSFET shown in FIGS. 20A to 20F;

22A to 22E are cross-sectional views illustrating still another method of manufacturing a MOSFET;

23A to 23E are cross-sectional views illustrating still another method of manufacturing a MOSFET;

24A to 24F are, for comparison, cross-sectional views illustrating a method of manufacturing a MOSFET;

FIG. 25 is a timing chart showing a manufacturing process of the MOSFET shown in FIGS. 24A to 24F;

26 is a cross-sectional view showing another vertical type trench gate MOSFET;

FIG. 27 is a partially enlarged cross-sectional view showing the MOSFET shown in FIG. 26;

28A to 28D are cross-sectional views illustrating a method of manufacturing the MOSFET shown in FIG. 26;

29A to 29D are cross-sectional views illustrating a method of manufacturing the MOSFET shown in FIG. 26;

30A to 30C are cross-sectional views of a semiconductor substrate illustrating a method of manufacturing the MOSFET shown in FIG. 26;

31A and 31B are cross-sectional views showing different shapes of grooves;

32A is a cross-sectional view showing a substrate, and FIG. 32B is a graph showing the relationship between process time and growth thickness; and

33A to 33C are cross-sectional views showing an epitaxial film in a trench.

Detailed ways

(first embodiment)

Next, a first embodiment embodying the present invention will be described based on the drawings.

FIG. 1 shows a cross-sectional view of a vertical type trench gate MOSFET in this embodiment mode.

In FIG. 1 , an epitaxial film 2 serving as a drain region is formed on an n ⁺ silicon substrate 1 , and an epitaxial film 3 is formed on this epitaxial film 2 . The trenches 4 are provided in parallel in the epitaxial film 2 on the lower side. Trenches 4 pass through epitaxial film 2 and reach n ⁺ silicon substrate 1 . Epitaxial film 5 is filled in trench 4 . The conductivity type of epitaxial film 5 in trench 4 is p-type, and the conductivity type of lateral region 6 of trench 4 is n-type. Thereby, p-type regions 5 and n-type regions 6 are arranged alternately in the lateral direction. Thus, a so-called super junction structure in which the drift layer of the MOSFET has a p/n column structure is formed.

In the above-mentioned epitaxial film 3 on the upper side, a p layer 7 is formed in its surface layer portion. Trenches 8 for gate electrodes are provided in parallel in epitaxial film 3 and reach epitaxial film 2 . Gate oxide film 9 is formed on the inner surface of trench 8 . Polysilicon gate electrode 10 is provided in the inner direction of gate oxide film 9 . n ⁺ source region 11 is formed in the surface layer portion in the portion adjacent to trench 8 on the upper face of epitaxial film 3 . Also, p ⁺ source contact region 12 is formed in a surface layer portion on the upper surface of p type epitaxial film 3 .

An unillustrated drain electrode is formed on the lower surface of n ⁺ silicon substrate 1 and is electrically connected to n ⁺ silicon substrate 1 . Also, an unshown source electrode is formed on the upper surface of epitaxial film 3 and is electrically connected to n ⁺ source region 11 and p ⁺ source contact region 12 .

In the case where the source voltage is set to the ground potential and the drain voltage is set to the positive potential, the transistor is turned on by applying a predetermined positive voltage as the gate potential. When the transistor is turned on, an inverting layer is formed in a portion adjacent to gate oxide film 9 in p layer 7 . The flow of electrons between source and drain through this inversion layer (from n ⁺ source region 11, p layer 7, n-type region 6 to n ⁺ silicon substrate 1). At reverse bias application time (in a case where the source voltage is set to ground potential and the drain voltage is set to positive potential), the depletion layer spreads from the pn junction portion of p-type region 5 and n-type region 6 . The p-type region 5 and n-type region 6 are depleted and a high breakdown voltage is obtained.

Next, a method of manufacturing a vertical type trench gate MOSFET in this embodiment mode is explained by using FIGS. 2A to 2C and 3A to 3C.

First, the epitaxial growth equipment used in this manufacturing process will be explained. Fig. 4 is a schematic structural view of an epitaxial growth device.

In FIG. 4 , a base 31 for holding a substrate (wafer) 32 is provided in a chamber 30 . In the substrate (wafer) 32, grooves are formed on the main surface. A silicon substrate (wafer) 32 can be heated by a lamp 33 . An exhaust pump 34 is connected to the chamber 30 . A silicon source gas such as SiH ₂ Cl ₂ (dichlorosilane: DCS) or the like, a halide gas such as hydrogen chloride gas (HCl) or the like, and hydrogen gas may be introduced into the chamber 30 . Also, a thermometer 35 is provided, and the surface of the epitaxial film at the time of epitaxial growth can be observed by this thermometer 35 . That is, the surface temperature at the time of epitaxial film formation in the silicon substrate 32 fixed to the chuck base 31 in the chamber 30 can be monitored. The flow rate of the silicon source gas supplied into the chamber 30 for epitaxial growth can be adjusted by the valve 36a as the first gas flow rate adjusting means. The flow rate of the halide gas supplied into the chamber 30 at the epitaxial growth time can be adjusted by the valve 36b as the second gas flow rate adjusting means. The flow rate of hydrogen can be adjusted by valve 36c. The growth temperature in the chamber 30 can be adjusted through the lamp 33 by a temperature controller 37 as a temperature adjustment means. The growth pressure in the chamber 30 can be adjusted by a pump 34 as growth pressure adjustment means. A thermometer 35, valves 36a, 36b, and 36c, a temperature controller 37, and an exhaust pump 34 are connected to a controller 38 as a switching device. A signal from the thermometer 35 is input to the controller 38 , and the controller 38 controls the operations of the valves 36 a , 36 b , 36 c , the temperature controller 37 and the exhaust pump 34 .

FIG. 6 shows a timing chart when epitaxial growth is performed by using the epitaxial growth apparatus of FIG. 4 . 6 shows changes in growth speed (speed on the main surface of the silicon substrate), growth temperature, halide gas flow rate, silicon source gas flow rate, growth pressure, hydrogen flow rate, and thermometer output during the epitaxial growth process.

First, as shown in FIG. 2A , n ⁺ silicon substrate 1 is prepared, and n type epitaxial film 2 is formed on this n ⁺ silicon substrate 1 . Furthermore, the upper surface of the epitaxial film 2 is planarized.

Subsequently, as shown in FIG. 2B, the n-type epitaxial film 2 is subjected to anisotropic etching (RIE) or wet etching using an alkaline anisotropic etchant (KOH, TMAH, etc.) by using a mask, and formed to reach Trenches 4 of silicon substrate 1 . Thus, trench 4 is formed on main surface 2 a of the silicon substrate composed of n ⁺ silicon substrate 1 and epitaxial film 2 . For example, trench 4 has a width of approximately 0.8 μm and a depth of 13 μm.

Here, reference is made to the substrate used. As shown in FIGS. 7A and 7B , a Si(110) substrate was used as a single crystal substrate, and a structure in which an epitaxial film 40 was formed on the Si(110) substrate was used. Thus, the bottom surface of the trench is the (110) plane, and the (111) plane is included on the side surfaces of the trench 41 . By using this orientation, the filling shape becomes the most excellent in trench-fill epitaxy using LP-CVD, and trench-fill epitaxy growth without voids and improved throughput can be performed. Also, by providing a Si (100) substrate and a (111)-oriented trench in this way, wet processing of TMAH, KOH, etc. can be applied to the trench. Therefore, damage to the groove surface can be reduced in the case of using dry etching.

In addition, as shown in FIGS. 8A and 8B , a Si(100) substrate was used as a single crystal substrate, and a structure in which an epitaxial film 50 was formed on the Si(100) substrate was used. Thus, the bottom surface of the trench is the (100) plane, and the (100) plane is included on the side surfaces of the trench 51 . The most excellent (100) orientation trench in terms of device characteristics is Si(100), and by setting the orientation of trench sides of p/n columns to Si(100), all orientations become Si(100). Thus, in performing trench-fill epitaxial growth, orientation dependence is removed in the trench.

As shown in FIG. 2c , epitaxial film 20 is then formed on epitaxial film 2 including the inside of trench 4 (on main surface 2 a ), and the inside of trench 4 is filled with this epitaxial film 20 . At this time, in FIG. 6, growth starts at time t1. Specifically, the temperature in the chamber was raised, and a required amount of halide gas was flowed, and a required amount of silicon source gas was flowed. Furthermore, the pressure-reduced environment was set to the film formation pressure in the chamber, and hydrogen gas was flowed. For example, using SiH ₂ Cl ₂ (dichlorosilane: DCS) as a silicon source gas, and a gas mixed with hydrogen chloride (HCl) as a halide gas, the inside of trench 4 is filled by low-pressure epitaxial growth. In this case, as shown in FIG. 9 , as elements (chlorine atoms 61 and silicon atoms 62 ) with respect to the behavior of trenches formed in the epitaxial film 60, chlorine atoms (Cl atoms) 61 adhere to on the silicon surface in the opening portion of the trench. Thus, silicon grows from the trench bottom portion.

In Fig. 6, as a typical growth condition for filling epitaxy, the growth temperature is 960°C, the growth pressure is set to 40 Torr, and the flow rate of DCS is 0.1 slm, the flow rate of hydrogen (H ₂ ) is 30 slm, and the flow rate of hydrogen chloride gas (HCl) is 0.1 slm. The flow rate is 0.5 slm. The growth rate on the groove surface (substrate main surface) under this condition is about several tens to 100 nm/min.

In the process of filling the inside of this trench 4 with the epitaxial film 20 , a mixed gas of a silicon source gas and a halide gas is used as a gas supplied to the silicon substrate so that the epitaxial film 20 is formed. Specifically, one of monosilane (SiH ₄ ), disilane (Si ₂ H ₆ ), dichlorosilane (SiH ₂ Cl ₂ ), trichlorosilane (SiHCl ₃ ) and silicon tetrachloride (SiCl ₄ ) Used as silicon source gas. In particular, one of monosilane, disilane, dichlorosilane, and trichlorosilane is preferably used as the silicon source gas. One of hydrogen chloride (HCl), chlorine (Cl ₂ ), fluorine (F ₂ ), chlorine trifluoride (ClF ₃ ), hydrogen fluoride (HF), and hydrogen bromide (HBr) is used as the halide gas.

On the other hand, when forming epitaxial film 20 in FIG. 2C (when epitaxial growth is performed), the following are set according to the aspect ratio of the trench.

When the aspect ratio of the trench is less than 10 and the standard flow rate of the halide gas is set to X [slm] and the growth rate to Y [μm/min], the following relationship is satisfied.

Y＜0.2X+0.1 (F1)

When the aspect ratio of the trench is 10 or more and less than 20, and the standard flow rate of the halide gas is set to X [slm] and the growth rate to Y [μm/min], the following relationship is satisfied.

Y＜0.2X+0.05 (F2)

When the aspect ratio of the trench is 20 or more, and the standard flow rate of the halide gas is set to X [slm] and the growth rate to Y [μm/min], the following relationship is satisfied.

Y＜0.2X (F3)

Thus, it is preferable from the viewpoint of effectively filling the trenches with the epitaxial film while suppressing generation of voids.

The experimental results on which this is based are shown in FIGS. 10 , 11 and 12 . In FIGS. 10 , 11 and 12 , the standard flow rate X [slm] of hydrogen chloride is set on the axis of abscissas, and the growth rate Y [μm/min] is set on the axis of ordinates. FIG. 10 shows a case where the aspect ratio is "5". FIG. 11 shows a case where the aspect ratio is "15". FIG. 12 shows a case where the aspect ratio is "25". In Figures 10, 11 and 12, black circles show the presence of pores, while white circles show the absence of pores. In each of these figures, it is known that if the standard flow rate of hydrogen chloride is increased, no voids will be generated even when the growth rate of the epitaxial film is high. Furthermore, it is also known that, at the same standard flow rate of hydrogen chloride, if the growth rate of the epitaxial film is not lowered as the aspect ratio increases, the generation of voids may not be prevented. In each of these figures, the formulas showing the boundaries of the existence of porosity generation are Y=0.2X+0.1 in FIG. 10 and Y=0.2X+0.05 in FIG. 11 , and Y=0.2X in FIG. 12 . If it is the area under each formula, no porosity will be created. As shown in FIG. 2B , the aspect ratio of the trench is B/A, ie depth of trench/width of trench.

Also, the epitaxial film 20 is formed under the reaction rate determining conditions. In particular, when monosilane or disilane is used as the silicon source gas, the upper limit of the film formation temperature is set to 950°C. When dichlorosilane is used as the silicon source gas, the upper limit of the film formation temperature is set to 1100°C. When trichlorosilane is used as the silicon source gas, the upper limit of the film formation temperature is set to 1150°C. When silicon tetrachloride is used as the silicon source gas, the upper limit of the film formation temperature is set to 1200°C. Thus, it was experimentally confirmed that epitaxial growth can be performed without generating crystal defects.

When the filling of epitaxial film 20 in trench 4 is thus completed, as shown in FIG. 3A , epitaxial film 21 is then formed on epitaxial film 20 by performing epitaxial growth for planarization. That is, when filling epitaxial growth is performed from the bottom portion of the trench by using a silicon source gas and a halide gas, the trench-induced step difference is formed. In consideration of the polishing process, it is desirable to planarize the main surface of the substrate to reduce the amount of polishing, and to perform epitaxial growth for planarization after trench-fill epitaxy. In this planarization epitaxy, film formation is performed under growth at a growth rate faster than that of the epitaxial film 20 on the substrate main surface 2 a in trench-fill epitaxy. Specifically, in FIG. 6 , the film formation conditions of at least one of (VIA) to (VIAD) were changed.

(VIA) The growth temperature is increased compared to the growth temperature at the fill epitaxy time.

(VIB) The halide gas is not flowing, or the flow rate of the halide gas is reduced compared to the filling epitaxial growth time.

(VIC) increases the flow rate of the silicon source gas compared to the fill epitaxial growth time.

(VID) increases the growth pressure compared to the fill-epitaxial growth time.

Thus, as shown in (VIE) of FIG. 6 , it can be set under the condition in which the growth rate of silicon on the main surface (plane) 2 a of the silicon substrate 1 , 2 is fast in terms of planarization epitaxy .

Here, film formation can be performed under conditions in which the growth rate of epitaxial film 20 on main surface 2 a of silicon substrate 1 , 2 is faster than in the planarization epitaxial process. Therefore, when switching to planarization epitaxial growth after filling epitaxial growth is terminated, at least two or more of the corresponding parameters among the flow rate of the halide gas, the flow rate of the silicon source gas, the growth temperature, and the growth pressure Simultaneous switching is also possible in order to obtain high growth rate conditions.

Also, completion of trench filling is detected as described below.

When the output of the thermometer is monitored and the trench is filled during epitaxial growth, the output value of the thermometer does not change, as shown at time t2 in FIG. 6 . The controller 38 of FIG. 4 detects the completion of trench filling at this time t2, and performs switching to the condition for increasing the growth rate. That is, at a point in time when the surface temperature of the epitaxial film filled in the trench is monitored in the thermometer 35 from the main surface side of the silicon substrate 32 and does not change the output signal level of the thermometer 35 at a predetermined measurement temperature, the controller 38 acts as The switching device is controlled by at least one of valve 36a (first gas flow rate regulator), valve 36b (second gas flow rate regulator), temperature controller 37 (temperature regulator) and pump 34 (growth pressure regulator). At least one of the flow rate of the silicon source gas, the flow rate of the halide gas, the growth temperature, and the growth pressure, and switching to conditions for increasing the growth rate is performed.

Fig. 5 shows the measurement results related to the epitaxial growth rate. In FIG. 5 , the temperature is set on the horizontal axis, and the growth rate ratio is set on the vertical axis. FIG. 5 shows the case of only dichlorosilane, and the case of growth by using a mixed gas of dichlorosilane and hydrogen chloride. It can be understood from this FIG. 5 that the growth rate in the case of growth by using only dichlorosilane is faster than that in the case of growth by using a mixed gas of dichlorosilane and hydrogen chloride. Also, it will be appreciated that growth is enhanced at higher temperatures.

In planarized epitaxy, the typical growth rate is a few μm/min when the growth temperature is changed from 960°C to 990°C and the pressure in the chamber is changed from 40 Torr to 80 Torr. Therefore, when the thickness of the epitaxial film for planarization is set to 3 μm, when using epitaxy (hybrid epitaxy using HCl) similar to the above-mentioned trench filling conditions to obtain the growth rate of several tens to 100 nm/min, It takes 30 minutes (=3[μm]/0.1[μm/min]). However, this time can be shortened to 3 minutes (=3[μm]/1[μm]/min]). Therefore, the throughput of the epitaxial process can be improved.

When the planarization epitaxial growth is terminated, planarization polishing is performed from the upper side of the epitaxial film 21 in FIG. 3A . That is, the epitaxial films 21, 20 of the substrate main surface 2a are polished. As shown in FIG. 3B , epitaxial film (n-type silicon layer) 2 is exposed by this polishing. Thereby, p-type regions 5 and n-type regions 6 are arranged alternately in the lateral direction. Polishing can be done as needed.

As shown in FIG. 3C , p ^- -type epitaxial film 3 is then formed on epitaxial film 2 . Furthermore, as shown in FIG. 1, p well layer 7, trench 8, gate oxide film 9, polysilicon gate electrode 10, n ⁺ source region 11 and p ⁺ source contact region 12 are formed. Also, electrodes and wiring are formed.

Next, in this manufacturing process, the epitaxial film formation process shown in FIGS. 2C and 3A will be described in detail.

24A to 24F show manufacturing process diagrams for a comparative example replacing FIGS. 2A to 2C and FIGS. 3A to 3C . FIG. 25 is a timing chart for a comparative example in place of FIG. 6 .

As shown in FIG. 24A , an n type epitaxial film 101 is formed on an n ⁺ silicon substrate 100 . As shown in FIG. 24B , trench 102 is formed by etching n-type epitaxial film 101 . As shown in FIGS. 24C and 24D , the epitaxial film 104 is formed by performing trench-fill epitaxy using a silicon source gas and a halide gas. As shown in FIG. 24E , an epitaxial film 105 is formed by performing planarization epitaxy. As shown in FIG. 24F, the epitaxial films 104, 105 are then polished. Thus, selective growth can be performed from the bottom portion of the trench by simultaneously flowing a silicon source gas such as DCS and a halide gas such as HCl so as to realize trench-fill epitaxy without voids. Since the halide gas is used, selective growth from the bottom portion of the trench becomes a major factor, since silicon growth on the main surface of the substrate and in the opening portion of the trench can be particularly suppressed.

In this substrate manufacturing process, film formation is performed under reaction rate-determining conditions at low temperature for void-free trench-fill epitaxy. Also, selective epitaxy using a halide gas such as HCl or the like is used. When planarization epitaxy is performed by using this trench filling condition, the growth rate is slow, so that the throughput becomes poor. Also, since selective growth using silicon source gas and halide gas is used, the growth rate is small by the attachment effect due to the halogen group element on the main surface of the substrate as shown in FIG. 9 . Also, it is necessary to increase the throughput of the non-polishing process or the polishing process by reducing the amount of polishing.

In contrast to this, the following structures are set in this embodiment mode.

Unlike trench-fill epitaxy, selectivity is required in planarized epitaxy. Therefore, film formation conditions such as film formation under diffusion-limited conditions due to lowering of the film-forming temperature and silicon growth limitation in trench opening portions due to halide gas are not required. Therefore, as planarization epitaxy conditions, for example, the supply of HCl gas is stopped and the film formation conditions are switched from diffusion-limited conditions to supply-limited conditions, and the like. Thereby, the film formation time required in the planarization epitaxy is shortened, and the throughput of the trench epitaxy process can be improved.

According to the above-described embodiment modes, the following effects can be obtained.

(1) As a manufacturing method of a semiconductor substrate, a first process, a second process, and a third process are provided. In the first process, trench 4 is formed on main surface 2 a of silicon substrate 1 , 2 . In the second process, epitaxial film 20 is formed on the main surfaces of silicon substrates 1, 2 including the inside of trench 4 by epitaxial growth caused by supply of a mixed gas of silicon source gas and halide gas, and the trench The inside of 4 is filled with epitaxial film 20 . In the third process, the epitaxial film 21 is formed on the epitaxial film 20 used for filling in the second process so that the growth rate of the epitaxial film 20 on the main surface 2a of the silicon substrate 1, 2 is higher than that in the second process. Planarization under fast conditions. Thus, in the second process, epitaxial film 20 is formed on main surface 2a of silicon substrate 1, 2, including the inside of trench 4, by epitaxial growth caused by supplying a mixed gas of silicon source gas and halide gas. Then, the inside of trench 4 is filled with epitaxial film 20 . In this method, trench filling of pores in epitaxy is suppressed by supplying a halide gas. Also, in the third process, the epitaxial film 20 used for the filling in the second process is formed under the condition that the growth rate of the epitaxial film 20 on the main surface 2a of the silicon substrate 1, 2 is faster than that in the second process. The epitaxial film 21 is formed on it, thereby improving the throughput. Also, polishing can be set to be unnecessary. The substrate can thereby be easily planarized after filling the trenches with the epitaxial film, while suppressing the trench filling of voids in the epitaxy.

(2) In the third process, after the epitaxial film 21 is formed under the condition that the growth rate of the epitaxial film 20 on the main surface 2a of the silicon substrate 1, 2 is faster than that in the second process, the silicon substrate 1, 2 The epitaxial films 20, 21 on the main surface 2a side are polished. Thereby, further planarization can be performed.

(3) In the third process, one of the following is performed so that epitaxial film 21 is formed under conditions faster than the growth rate of epitaxial film 20 on main surface 2a of silicon substrate 1, 2 in the second process.

(A) The flow rate of the halide gas is reduced at the time of epitaxial growth in the third process compared to the time of epitaxial growth in the second process.

(B) The halide gas is set not to flow during the epitaxial growth time in the third process.

(C) The flow rate of the silicon source gas is increased at the epitaxial growth time in the third process compared to the epitaxial growth time in the second process.

(D) Compared with the epitaxial growth time in the second process, the growth temperature is increased in the epitaxial growth time in the third process.

(E) The growth pressure is increased in the epitaxial growth time in the third process compared with the epitaxial growth time in the second process.

(4) Efficiency is good when both the epitaxial growth of the second process and the third process are performed in pressure-reducing CVD.

(5) In the third process, the epitaxial film 21 is formed under the condition that the growth rate of the epitaxial film 20 on the main surface 2a of the silicon substrate 1, 2 is faster than that in the second process. Therefore, when switching to the epitaxial growth in the third process after the epitaxial growth in the second process is terminated, the flow rate of the halide gas, the flow rate of the silicon source gas, the growth temperature and the growth pressure among the corresponding parameters are simultaneously switched. At least two or more in order to obtain high growth rate conditions. Thereby, throughput can be further improved.

(6) In the second process, the surface temperature of the epitaxial film 20 for filling into the trench 4 from the main surface 2 a side of the silicon substrate 1 , 2 is monitored by the thermometer 35 . At the point of time when the output signal level of the thermometer 35 at the predetermined measurement temperature does not change, it is switched to the condition for increasing the growth rate in the third process. Thus, the completion of the fill epitaxy can be reliably detected.

(7) The chuck base 31, the first gas flow rate adjusting device 36a, the second gas flow rate adjusting device 36b, the temperature adjusting device 37, the pressure adjusting device 34, the thermometer 35 and the switching device 38 are set as an epitaxial growth device. A chuck base 31 is provided in the chamber 30, and holds a silicon substrate 32 in which grooves are formed on the main surface. The first flow rate adjusting means 36a adjusts the flow rate of silicon source gas supplied into the chamber 30 for epitaxial growth. The second gas flow rate adjusting means 37 adjusts the flow rate of the halide gas supplied into the chamber 30 at the time of epitaxial growth. The temperature adjustment device 37 adjusts the growth temperature in the chamber 30 . The pressure adjustment device 34 adjusts the growth pressure in the chamber 30 . A thermometer 35 monitors the surface temperature at the time of epitaxial film formation in the silicon substrate 32 fixed to the chuck base 31 in the chamber 30 . In the switching device 38 , the surface temperature of the epitaxial film filled in the trench is monitored by the thermometer 35 from the main surface side of the silicon substrate 32 . At the time point t2 at which the output signal level of the thermometer 35 does not change at the predetermined measurement temperature, the switch device 38 passes through the first gas flow rate adjustment device 36a, the second gas flow rate adjustment device 36b, the temperature adjustment device 37 and the pressure adjustment device 34. At least one is used to control at least one of the flow rate of the silicon source gas, the flow rate of the halide gas, the growth temperature and the growth pressure. The switching device 38 then performs a switchover to conditions for increasing the growth rate.

Thus, filling epitaxy and subsequent planarizing epitaxy can be automatically controlled.

The epitaxial growth in the second process can be performed by a reduced pressure CVD growth method, and the epitaxial growth in the third process can also be performed by a normal pressure CVD growth method.

Moreover, at least one of the corresponding parameters in the flow rate of the halide gas, the flow rate of the silicon source gas, the growth temperature and the growth pressure can also be gradually and continuously adjusted during the epitaxial growth of the filling (during the epitaxial growth of the second process), so as to obtain the following: The high growth rate condition shown in FIG. 13 can alternatively be adjusted in a step shape to obtain the high growth rate condition as shown in FIG. 14 . Among these growth parameters, one parameter can also be changed, or a plurality of parameters can be combined.

Thus, when the aspect ratio at the initial stage of trench filling is high as shown in FIG. 15A, the growth rate of the filling epitaxy is lowered (high selectivity film formation condition). When the aspect ratio is small, as shown in Fig. 15B, the growth rate increases. Thereby, the time required for filling can be shortened. That is, in the trench fill epitaxy time, the throughput of the entire trench epitaxy process can also be improved by changing the film formation conditions in accordance with the change of the aspect ratio in the trench fill epitaxy process.

(second embodiment mode)

Next, the second embodiment mode will be explained mainly by points of difference from the first embodiment mode.

16A to 16E show manufacturing process diagrams in this embodiment mode in place of FIGS. 2A to 2C and 3A to 3C. FIG. 17 is a timing chart of this embodiment mode in place of FIG. 6 .

As shown in FIG. 16A, an epitaxial film 71 is formed on a silicon substrate 70, and is set as a silicon substrate. As shown in FIG. 16B, trenches 72 are formed on main surfaces 71a of silicon substrates 70, 71 (first process).

After that, as shown in FIG. 16C, by epitaxial growth caused by supplying a mixed gas of a silicon source gas and a halide gas, an epitaxial film 73 is formed only inside the trench 72, not on the main surfaces of the silicon substrates 70, 71. The epitaxial film is grown on 71a. At this time, as shown in FIG. 17 , high-selectivity epitaxy conditions in trench-fill epitaxy can be set by increasing the flow rate of the halide gas or lowering the growth temperature compared with the comparative example of FIG. 25 . The epitaxial film 73 is grown only inside the trench 72 without growing the epitaxial film on the main surface 71 a of the silicon substrate 70 , 71 . In particular, the growth takes place from the bottom of the trench. As shown in FIGS. 16D and 16E , the trench 72 is filled with the epitaxial film 73 until the epitaxial film 73 has the same face as the main surface 71 a of the silicon substrate 70 , 71 (second process).

Thus, in the second process, the epitaxial film 73 is grown only inside the trench 72 and not on the main surfaces 71a of the silicon substrates 70, 71 by the epitaxial growth caused by supplying the mixed gas of the silicon source gas and the halide gas. grow the epitaxial film. Furthermore, the trench 72 is filled with the epitaxial film 73 until the epitaxial film 73 has the same surface as the main surface 71 a of the silicon substrate 70 , 71 . In this filling, trench filling of voids in the epitaxial layer can be suppressed by supplying a halide gas. Therefore, since no film is formed on the main surface 71a, the polishing process can be omitted (polishing can be made unnecessary). Thereby, the substrate can be easily planarized after filling the trenches with the epitaxial film, while suppressing the filling of voids in the epitaxial layer by the trenches.

(third embodiment mode)

Next, the third embodiment mode will be explained mainly by points of difference from the first embodiment mode.

18A to 18F show manufacturing process diagrams in this embodiment mode replacing FIGS. 2A to 2C and FIGS. 3A to 3C. FIG. 19 is a timing chart in this embodiment mode replacing FIG. 6 .

As shown in FIG. 18A , a silicon substrate is constructed by forming an epitaxial film 81 on a silicon substrate 80 . As shown in FIG. 18B , a mask 82 for forming trenches is then provided on the main surfaces 81 a of the silicon substrates 80 , 81 . The trench 83 is formed by etching the silicon substrate 81 from the mask opening portion 82a for trench formation in the mask 82 (third process). A silicon oxide film is used as the mask 82 .

After that, as shown in FIGS. 18C and 18D , by low-pressure epitaxial growth caused by supplying a mixed gas of a silicon source gas and a halide gas in a state where the mask 82 remains, an epitaxial film 84 is grown only inside the trench 83 . Furthermore, as shown in FIG. 1SE, the trench 83 is filled with the epitaxial film 84 until the epitaxial film 84 has the same face as the main surface 81a of the silicon substrate 80, 81 (second process). That is, as shown in FIG. 19 , film formation is performed on the main surface of the substrate in the case of FIG. 25 . However, in this embodiment mode, by utilizing the selectivity of silicon (Si) and the silicon oxide film (SiO ₂ ) with respect to film formation conditions, filling is performed in the trench 83 and not on the substrate main surface 81a (the oxide film above) to grow. In this filling, the trench is suppressed from filling voids in the epitaxial layer by supplying a halide gas.

As shown in FIG. 18F, the mask 82 is removed (third process).

Thus, in this embodiment mode, since a film is not formed on the main surface 81a, the polishing process can be omitted (polishing can be made unnecessary). Thereby, the substrate can be easily planarized after filling the trenches with the epitaxial film, while suppressing the filling of voids in the epitaxial layer by the trenches.

(Fourth embodiment mode)

Next, the fourth embodiment mode will be explained mainly by points of difference from the first embodiment mode.

20A to 20F show manufacturing process diagrams in this embodiment mode replacing FIGS. 2A to 2C and 3A to 3C. FIG. 21 is a timing chart in this embodiment mode instead of FIG. 6 .

As shown in FIG. 20A, an epitaxial film 91 is formed on a silicon substrate 90, and constitutes the silicon substrate. As shown in FIG. 20B , a mask 92 for forming trenches is then provided on the main surfaces 91 a of the silicon substrates 90 , 91 . The trench 93 is then formed by etching the silicon substrate 91 from the mask opening portion 92a used to form the trench in the mask 92 (first process). A silicon oxide film is used as the mask 92 .

After that, as shown in FIG. 20C , in the state where the mask 92 remains, an epitaxial film 94 is grown only inside the trench 93 by low-pressure epitaxial growth caused by supplying a mixed gas of a silicon source gas and a halide gas. . Also, as shown in FIG. 20D , trench 93 is filled with epitaxial film 94 until epitaxial film 94 becomes higher than the surface of mask 92 for trench formation (second process). That is, as shown in FIG. 21, growth is not performed on the mask 92 by utilizing selective epitaxial conditions using silicon source gas and halide gas. In this filling, the trench is suppressed from filling voids in the epitaxial layer by supplying a halide gas.

Furthermore, as shown in FIG. 20E, the epitaxial film 94 on the main surface 91a side of the silicon substrate 90, 91 is polished by using the mask 92 as a stopper, and the main surface 91a side of the silicon substrate 90, 91 is planarized ( third process). At this time, polishing is performed using the mask (oxide film) 92 as an end point. In this case, the polished area is only the epitaxially filled area, in contrast to the case where the entire silicon facet is polished. Therefore, throughput can be increased since the amount of polishing is reduced. Furthermore, since the polishing dispersion is determined by the film thickness dispersion of the mask (oxide film) 92, the film thickness uniformity characteristic of the p/n column layer in the plane can also be improved.

Subsequently, the mask 92 is removed (fourth process). As shown in FIG. 20F, the main surface 91a side of the silicon substrate 90, 91 is oxidized as a sacrificial layer, and the sacrificial oxide film is removed so as to be better planarized. Oxidation of the sacrificial layer and removal of the sacrificial oxide film may be performed as needed.

Thus, in this embodiment mode, the amount of polishing can be reduced and the substrate can be easily planarized by using a mask as a stopper after filling the trenches with the epitaxial film, while suppressing the filling of pores in the epitaxial layer by the trenches .

(fifth embodiment mode)

Next, the fifth embodiment mode will be explained mainly by points of difference from the fourth embodiment mode.

22A to 22E show manufacturing process diagrams in this embodiment mode.

As shown in the aforementioned FIG. 20A , an epitaxial film 91 is formed on a silicon substrate 90 . As shown in FIG. 20B , a mask 92 for forming trenches is provided on the main surfaces 91 a of the silicon substrates 90 , 91 . The trench 93 is formed by etching the silicon substrate 91 from the mask opening portion 92a used to form the trench in the mask 92 (first process).

As shown in FIGS. 22A, 22B, and 22C, in a state where the mask 92 remains, epitaxial growth is performed on the mask 92 including the inside of the trench 4 by supplying a mixed gas of a silicon source gas and a halide gas. Film formation is performed, and trench 93 is filled with epitaxial film 95 (second process). In this method, trench filling of voids in the epitaxial layer is suppressed by supplying a halide gas. At this time, the films on the upper face of the mask 92 may be a film formed as a single crystal (single crystal film) 96 and a film formed as a polycrystal (polycrystalline film) 97, as shown in FIG. 23C. That is, when the film thickness of the trench-fill epitaxial growth is increased, the final structure differs depending on the selectivity, that is, the ratio of the halide gas to the silicon source gas. When the selectivity is high (when the flow rate of the halide gas is increased), a single crystal grows on the mask (oxide film) 92 . In contrast, when the selectivity is low (when HCl is small), polysilicon grows on the entire surface or a part of the mask (oxide film) 92 . Thus, in the second process, by epitaxial growth caused by supplying a mixed gas of a silicon source gas and a halide gas, a single-crystal film 96 can be formed on the mask, and a polycrystalline film 97 can also be formed on the mask. mask on.

After that, as shown in FIGS. 22D and 23D , the films on the upper side of the mask 92 (films 95 , 96 of FIG. 22C and films 95 , 97 of FIG. 23C ) are polished using the mask 92 as a stopper. The main surface 91a side of the silicon substrates 90, 91 is then planarized (third process).

Subsequently, as shown in FIG. 22E, the mask 92 is removed (fourth process). After that, the main surface 91a side of the silicon substrate 90, 91 is oxidized as a sacrificial layer, and the sacrificial oxide film is removed so as to be better planarized. Removal of the sacrificial oxide layer and the sacrificial oxide film may be performed as needed.

Thus, in this embodiment mode, the substrate can be easily planarized by using the mask as a stopper after filling the trenches with the epitaxial film while suppressing the filling of the trenches in the voids in the epitaxial layer. In the second to fifth embodiment modes, as explained in the first embodiment mode, it is preferable to satisfy Y<0.2X+0.1, Y<0.2X+0.05 according to the trench aspect ratio at the trench-fill epitaxy time and Y<0.2X. Also, one of hydrogen chloride, chlorine, fluorine, chlorine trifluoride, hydrogen fluoride, and hydrogen bromide is preferably used in the halide gas, and monosilane, disilane, dichlorosilane, and trichlorosilane are preferably used in the silicon source gas. One of the silanes. Also, in the trench, the bottom surface is the (110) plane, and the (111) plane is included on the side surfaces. Otherwise, in the trench, it is preferable that the bottom surface is a (100) plane and that the (100) plane is included on the side faces.

In the description made so far, an n-type epitaxial film is formed in an n ⁺ substrate, and a groove is formed on its main surface (upper surface), and this n-type epitaxial film is used as a silicon substrate. However, the invention is also applicable to the case where the trench is formed directly in the bulk substrate.

(sixth embodiment mode)

Fig. 26 shows a cross-sectional view of a vertical type trench gate MOSFET in this embodiment mode. FIG. 27 is an enlarged view of a main part of the element portion in FIG. 26. FIG.

In FIG. 27 , epitaxial film 2 is formed as a source region on n ⁺ silicon substrate 1 , and epitaxial film 3 is formed on this epitaxial film 2 . Trenches 4 are provided in parallel in epitaxial film 2 on the bottom side. Trenches 4 pass through epitaxial film 2 and reach n ⁺ silicon substrate 1 . Epitaxial film 5 is filled in trench 4 . The conductivity type of epitaxial film 5 in trench 4 is p type, and the conductivity type of lateral region 6 of trench 4 is n type. Thereby, p-type regions 5 and n-type regions 6 are arranged alternately in the lateral direction. Thus, a so-called super junction structure in which the drift layer of the MOSFET has a p/n column structure is formed.

In the above epitaxial film 3 on the upper side, a p well layer 7 is formed in its surface layer portion. Trenches 8 for gate electrodes are provided in parallel in epitaxial film 3 and formed deeper than p-well layer 7 . Gate oxide film 9 is formed on the inner face of trench 8 . Polysilicon gate electrode 10 is provided in the inner direction of gate oxide film 9 . n ⁺ source region 11 is formed in a surface layer portion in a portion adjacent to trench 8 on the upper surface of epitaxial film 3 . Also, p ⁺ source contact region 12 is formed in a surface layer portion on the upper surface of p type epitaxial film 3 . Each trench 8 forms an n ^- buffer area 13 between the p-well layer 7 in the epitaxial film 3 and the epitaxial film 2 (drift layer) above. The n ^- buffer area 13 includes the bottom portion of the trench 8 and adjoins the n-type region 6 in the drift layer and also adjoins the p-well layer 7 . Furthermore, p ^- regions 14 are formed between the n ^- buffer regions 13 of each trench 8 .

A drain electrode not shown is formed on the underside of n ⁺ silicon substrate 1 and is electrically connected to n ⁺ silicon substrate 1 . Also, an unshown source electrode is formed on the upper face of epitaxial film 3 , and is electrically connected to n ⁺ source region 11 and p ⁺ source contact region 12 .

In a state where the source voltage is set to the ground potential and the drain voltage is set to the positive potential, the transistor is turned on by applying a predetermined positive voltage as the gate potential. When the transistor is turned on, an inversion layer is formed in a portion adjacent to gate oxide film 9 in p well layer 7 . Electrons are made to flow between source and drain through this reverse layer (from n ⁺ source region 11, p well layer 7, n ⁻ buffer zone 13, n type region 6 to n ⁺ silicon substrate 1). At the reverse bias application time (in a state where the source voltage is set to ground potential and the drain voltage is set to positive potential), the depletion layer is released from the pn junction portion of p-type region 5 and n-type region 6, n ^- buffer The pn junction portion of region 13 and p ^- region 14 and the pn junction portion of n ^- buffer layer 13 and p-well layer 7 extend. The p-type region 5 and n-type region 6 are depleted, and a high withstand voltage is obtained.

On the other hand, in FIG. 26 , n-type regions 6 and p-type regions 5 are also alternately arranged in the lateral direction in the terminal portion around the element portion. Furthermore, a LOCOS oxide film 15 is formed from the element portion on the upper surface of the epitaxial film 3 on the peripheral side.

Next, a method of manufacturing the vertical type trench gate MOSFET in this embodiment mode will be explained.

First, as shown in FIG. 28A , n ⁺ silicon substrate 1 is prepared, and n type epitaxial film 2 is formed on this n ⁺ silicon substrate 1 . Then a plurality of trenches 220 are formed in the epitaxial film 2 in the chip peripheral portion, and the silicon oxide film 221 is filled in the trenches 220 . Furthermore, the upper surface of the epitaxial film 2 is planarized.

Subsequently, as shown in FIG. 28B , silicon oxide film 222 is formed on n-type epitaxial film 2 and patterned into a predetermined shape so that a predetermined groove is obtained for this silicon oxide film 222 . Using the silicon oxide film 222 as a mask, perform anisotropic etching (RIE) or wet etching using an alkaline anisotropic etching solution (KOH, TMAH, etc.) on the n-type epitaxial film 2, and form Groove 4. At this time, a plurality of trenches 4 are formed such that the interval Lt between adjacent trenches is larger than the trench width Wt.

The grooves may have a stripe pattern and a dot-like (square, hexagonal, etc.) pattern, and it is sufficient that the grooves have periodic characteristics.

Subsequently, as shown in FIG. 28C, the silicon oxide film 222 used as a mask is removed. Also, hydrogen annealing is preferably performed after removing the oxide film 222 as a mask. As shown in FIG. 28D , a p-type epitaxial film 223 having an impurity concentration higher than that of the n-type epitaxial film 2 is formed on the n-type epitaxial film 2 including the inner surface of the trench 4, through which the epitaxial film 223 is filled. inside of trench 4. In the process of filling the inside of this trench 4 with the epitaxial film 223 , a mixed gas of a silicon source gas and a halide gas is used as a gas supplied to the silicon substrate to form the epitaxial film 223 . Forward tapered growth from the bottom portion of the trench is performed by using this hybrid epitaxy. Specifically, one of monosilane (SiH ₄ ), disilane (Si ₂ H ₆ ), dichlorosilane (SiH ₂ Cl ₂ ), trichlorosilane (SiHCl ₃ ) and silicon tetrachloride (SiCl ₄ ) Used as silicon source gas. In particular, one of dichlorosilane (SiH ₂ Cl ₂ ), trichlorosilane (SiHCl ₃ ), and silicon tetrachloride (SiCl ₄ ) is preferably used as the silicon source gas. One of hydrogen chloride (HCl), chlorine (Cl ₂ ), fluorine (F ₂ ), chlorine trifluoride (ClF ₃ ), hydrogen fluoride (HF), and hydrogen bromide (HBr) is used as the halide gas.

Also, the epitaxial film 223 is formed under reaction rate determining conditions. In particular, when monosilane or disilane is used as the silicon source gas, the upper limit of the film formation temperature is set to 950°C. When dichlorosilane is used as the silicon source gas, the upper limit of the film formation temperature is set to 1100°C. When trichlorosilane is used as the silicon source gas, the upper limit of the film formation temperature is set to 1150°C. When silicon tetrachloride is used as the silicon source gas, the upper limit of the film formation temperature is set to 1200°C. Also, when the film-forming vacuum degree is set to range from normal pressure to 100 Pa, the lower limit of the film-forming temperature is set to 800°C. When the film-forming vacuum degree is set to range from 100 Pa to 1×10 ^-5 Pa, the lower limit of the film-forming temperature is set to 600°C. Thus, it was experimentally confirmed that epitaxial growth can be performed without generating crystal defects.

Moreover, Ne2×Wt=Ne1×Lt is set, as the width Wt of the trench 4, the interval Lt between adjacent trenches, the impurity concentration Ne1 of the n-type epitaxial film 2, and the impurity concentration Ne2 of the p-type epitaxial film 223 are to satisfy Relationship.

After that, planarization and polishing are performed from the upper surface of the epitaxial film 223, and the epitaxial film (n-type silicon layer) 2 is exposed, as shown in FIG. 29A. Thereby, p-type regions 5 and n-type regions 6 are alternately arranged in the lateral direction. Also, the silicon oxide film 221 in the trench 220 in the peripheral portion of the chip is removed (see FIG. 28D).

As shown in FIG. 29B , a p ^- -type epitaxial film 224 is then formed on the epitaxial film 2 . Furthermore, as shown in FIG. 29C, n ^- buffer area 13 is formed in a portion adjacent to n-type region 6 in p ^- type epitaxial film 224 by ion implantation. At this time, a depression 225 is formed on the upper surface of the epitaxial film 224 provided in the trench 220 in the chip peripheral portion. The recesses 225 serve as alignment marks and are aligned in place with the photomask.

Subsequently, as shown in FIG. 29D , a p ^- type epitaxial film 226 is formed on the p ^- type epitaxial film 224 .

After that, as shown in FIG. 26, LOCOS oxide film 15 is formed. Further, p well layer 7, trench 8, gate oxide film 9, polysilicon gate electrode 10, n ⁺ source region 11 and p ⁺ source contact region 12 are formed in the element portion. Also, electrodes and wiring are formed. In the formation of this element portion, when n ⁺ source region 11, p ⁺ source contact region 12, etc. are formed by ion implantation, the upper surface of epitaxial film 226 provided in trench 220 in the chip peripheral portion in FIG. A depression 227 is formed on it. The recesses 227 serve as alignment marks and are aligned in place with the photomask.

A mixed gas of a silicon source gas and a halide gas is used as a gas supplied to the silicon substrates 1, 2 to form the epitaxial film 223 after forming the trench 4 in the n-type epitaxial film 2, up to the film from the epitaxial film 223 The formation starts until the inside of the trench 4 is buried with the epitaxial film 223 . However, in a broad sense, in the final process of filling at least the inside of the trench 4 with the epitaxial film 223, a mixed gas of a silicon source gas and a halide gas may be used as the gas supplied to the silicon substrates 1, 2 to form the epitaxial film 223. Film 223.

In this manufacturing process, the buried epitaxial film formation process shown in FIGS. 28C and 28D will be specifically described by using FIGS. 30A, 30B, and 30C.

As shown in FIG. 30A , trench 4 is formed in epitaxial film 2 formed on n ⁺ silicon substrate 1 . After that, as shown in FIG. 30C , the inside of trench 4 is filled with epitaxial film 223 . At this time, as shown in FIG. 30B, as the film formation conditions of the epitaxial film 223, by introducing a halide gas to the epitaxial film 223 grown on the side surface of the trench, the growth rate in the trench opening portion is set to be higher than that in the deep trench. The growth rate in the opening portion of the trench is slow. That is, when the growth rate in the trench opening portion is set to ra, and the growth rate in a portion deeper than the trench opening portion is set to rb, ra<rb is set.

Thus, by introducing a halide gas, the epitaxial film formed in the trench is formed so that the film thickness of the opening portion of the trench becomes smaller than that of the bottom portion of the trench. Thus, with regard to the epitaxial film on the side of the trench, the film thickness of the trench opening portion becomes smaller than that of the trench bottom portion, and blocking in the trench opening portion due to the epitaxial film is suppressed, and improvement can be made. Buried characteristics in trenches (film formation without voids possible). That is, the withstand voltage of the super junction structure (p/n column structure) at the reverse bias application time (setting the source to the ground potential and setting the drain potential to a positive voltage) can be secured, and the film formation without pores can suppress junction leakage current. Furthermore, void-free formation (reduced pore size), as well as improved withstand voltage yield and improved junction leakage yield can be obtained.

In particular, when forming the epitaxial film 223 in FIG. 28D, the following are set according to the aspect ratio of the trench.

When the aspect ratio of the trench is less than 10, and the standard flow rate of the halide gas is set to X [slm] and the growth rate to Y [μm/min], the following relationship is satisfied.

Y＜0.2X+0.1 (F4)

When the aspect ratio of the trench is 10 or more and less than 20, and the standard flow rate of the halide gas is set to X [slm] and the growth rate to Y [μm/min], the following relationship is satisfied.

Y＜0.2X+0.05 (F5)

When the aspect ratio of the trench is 20 or more, and the standard flow rate of the halide gas is set to X [slm] and the growth rate to Y [μm/min], the following relationship is satisfied.

Y＜0.2X (F6)

Thus, it is preferable from the viewpoint of effectively filling the trenches with the epitaxial film while suppressing generation of voids.

The experimental results on which this is based are shown in FIGS. 10 , 11 and 12 . In FIGS. 10 , 11 and 12 , the standard flow rate X [slm] of hydrogen chloride is set on the axis of abscissas, and the growth rate Y [μm/min] is set on the axis of ordinates. FIG. 10 shows a case where the aspect ratio is "5". FIG. 11 shows a case where the aspect ratio is "15". FIG. 12 shows a case where the aspect ratio is "25". In Figures 10, 11 and 12, black circles show the presence of pores, while white circles show the absence of pores. In each of these figures, it is known that if the standard flow rate of hydrogen chloride is increased, voids are not generated even when the growth rate of the epitaxial film is fast. Furthermore, it is also known that, at the same standard flow rate of hydrogen halide, if the growth rate of the epitaxial film is not lowered as the aspect ratio increases, the generation of voids may not be prevented. In each of these figures, the formulas showing the boundary where void generation exists are Y=0.2X+0.1 in FIG. 10 and Y=0.2X+0.05 in FIG. 11 and Y=0.2X in FIG. 12 . If it is the area under each formula, no porosity will be created. As shown in FIG. 28C, the aspect ratio of the groove is dl/Wt, ie, the depth of the groove/the width of the groove.

Next, the influence of the trench width Wt is explained by using FIGS. 31A to 33C.

As shown in FIGS. 31A and 31B , samples with a groove width Wt of 0.8 μm and samples with a groove width Wt of 3 μm were prepared. In this case, the sum (=Wt+Lt) of the interval Lt between the trenches 4 and the trench width Wt is constant (the same).

These two samples were then subjected to epitaxial growth. The results are shown in Figures 32A and 32B. In FIGS. 32A and 32B , the film formation time is set on the horizontal axis, and the grown film thickness (specifically, the film thickness on the upper surface of the substrate) is set on the vertical axis. In Figure 32B, the growth thickness was measured at five points on the substrate surface.

In FIGS. 32A and 32B , when its minimum value of 3 µm is required to ensure the polishing allowance for the growth film thickness on the vertical axis, the film formation time in the sample of Wt = 3 µm requires 220 minutes to satisfy the condition. In contrast, the film formation time can be 60 minutes in the sample of Wt = 0.8 μm. That is, the film formation time can be set to 1/3.

Thus, as shown in FIGS. 33A to 33C , in the relationship between the flow rate of the film forming gas and the flow rate of the etching gas (halide gas) and the film forming temperature, when the flow rate of the film forming gas increases, the etching gas (halide gas) ) is likely to generate voids in the trenches when the flow rate decreases and the film formation temperature increases. Here, the growth gas amount is the largest in FIG. 33A, and the growth gas amount is the smallest in FIG. 33C. The amount of etching gas in FIG. 33A is the smallest, while the amount of etching gas in FIG. 33C is the largest. The process temperature in FIG. 33A is the highest, while the process temperature in FIG. 33C is the lowest. Conversely, when the flow rate of the film forming gas is decreased, the flow rate of the etching gas (halide gas) is increased, and the film forming temperature is decreased, it is difficult to generate voids in the trenches. In this embodiment mode, voids are suppressed, and the growth rate is increased in consideration of these contents. It will be described in detail as follows.

As a method of manufacturing a semiconductor substrate by burying an epitaxial film in a trench and forming a diffusion layer with a high aspect ratio, especially as a method of manufacturing a p/n column of a drift layer applied to a super junction (SJ-MOS), in the hybrid In epitaxy, the growth rate in the upper surface of the substrate and in the opening portion of the trench is small, and the growth proceeds from the bottom portion of the trench. Therefore, since the width of the bottom portion is reduced, the growth volume per unit time is increased, and filling is performed at a high speed. Therefore, as shown in FIGS. 31A and 31B , if the column pitch (Wt+Lt) is the same, a super junction (SJ-MOS) in which p/n columns are formed at high speed can be manufactured when the following three conditions are satisfied.

(E) As a trench structure condition, the interval Lt between adjacent trenches 4 is formed so as to be larger than the trench width Wt (Wt<Lt).

(F) As filling epitaxial concentration conditions, in terms of the relationship between the concentration Ne1 of the n-type epitaxial film 2 and the concentration Ne2 of the p-type epitaxial film 223, the p-type epitaxial film 223 is set to be higher than that of the n-type epitaxial film 2 (Ne2>Ne1) thick.

(G) As filling epitaxial concentration conditions, the concentration Ne2 of the p-type epitaxial film 223 and the sum (sum) of the trench width Wt (=Ne2×Wt) and the concentration Ne1 of the n-type epitaxial film 2 and the difference between the concentration Ne1 of the adjacent trench 4 The total number of intervals Lt (=Ne1×Lt) is set to be equal (Ne2×Wt=Ne1×Lt).

Also, as for the substrate plane orientation, as shown in FIG. 28C, the trench side was set to Si(111) by using the Si(110) substrate according to the bottom portion selective characteristic of hybrid epitaxy. Otherwise, the trench sides are set to Si(100) by using a Si(100) substrate. Thereby, it becomes excellent in filling characteristics.

According to the above-described embodiment modes, the following effects can be obtained.

(8) As a manufacturing method of a semiconductor substrate, a first process and a second process are provided. In the first process, a plurality of trenches 4 are formed in an n-type (first conductivity type) epitaxial film 2 formed on an n-type (first conductivity type) silicon substrate 1 so that adjacent trenches The interval Lt between 4 is larger than the trench width Wt. In the second process, the p-type (second conductivity type) epitaxial film 223 having a concentration higher than the impurity concentration of the epitaxial film 2 is formed by using a mixed gas of a silicon source gas and a halide gas as a supplied gas. On this epitaxial film 2 including the inside of the trench 4 , a p-type epitaxial film 223 is formed in the final process for filling at least the trench 4 . The inside of trench 4 is then filled with p-type epitaxial film 223 .

Therefore, in the final process for filling at least trench 4 , film formation is performed by using a mixed gas of a silicon source gas and a halide gas as a supplied gas to form p-type epitaxial film 223 . The inside of trench 4 is then filled with p-type epitaxial film 223 . Thereby, blocking of the opening portion of the trench can be suppressed. On the other hand, the growth rate can be increased by forming the interval Lt between adjacent trenches to be larger than the trench width Wt.

Thereby, when filling the trench 4 with the epitaxial film 223 and manufacturing the semiconductor substrate, suppression of blocking of the opening portion of the trench and improvement of the growth speed can be reconciled.

(9) In the final process for filling at least the trench 4 when filling the inside of the trench 4 with the p-type epitaxial film 223 , as the film formation conditions of the epitaxial film 223 , with respect to the epitaxial film grown on the side surface of the trench, The growth rate in the opening portion of the trench is set to be lower than that in the deep portion of the opening portion of the trench. Thereby, blocking in the trench opening portion due to the epitaxial film 223 is suppressed, and the filling characteristics in the trench 4 can be improved.

(10) When the width of the trench 4 is set to "Wt", the interval between adjacent trenches 4 is set to "Lt", the impurity concentration of the n-type epitaxial film 2 is set to "Ne1", and the When the impurity concentration of the filled p-type epitaxial film 223 is set to "Ne2", the following relationship is satisfied.

Ne2×Wt＝Ne1×Lt (F7)

Therefore, optimization can be performed for optimal depletion formation in superjunction structures.

(11) In forming the p-type (second conductivity type) epitaxial film in the second process, when the standard flow rate of the halide gas is set to X [slm] and the growth rate is set to Y [μm/min], set the following relationship. That is, when the aspect ratio of the trench is less than 10, it is set to satisfy Y<0.2X+0.1. Also, when the aspect ratio of the groove is 10 or more and less than 20, it is set to satisfy Y<0.2X+0.05. Also, it is set to satisfy Y<0.2X when the aspect ratio of the groove is 20 or more. These relationships are preferable from the viewpoint of effectively filling the trenches with the epitaxial film while suppressing generation of voids.

In the explanation made so far, the first conductivity type is set to be n type, and the second conductivity type is set to be p type. However, conversely, the first conductivity type can also be set to p-type, and the second conductivity type can also be set to n-type (specifically, in FIG. 26, substrate 1 is set to p ⁺ , and region 5 is set to n type, region 6 is set to be p-type).

The above disclosure has the following aspects.

According to a first aspect of the present disclosure, a method for manufacturing a semiconductor device includes the steps of: forming a trench on a main surface of a silicon substrate; forming a first epitaxial film on and in the trench, thereby filling the trench with the first epitaxial film; and forming a second epitaxial film on the first epitaxial film by using another mixed gas of a silicon source gas and a halide gas. The step of forming the first epitaxial film has a first process condition of growing the first epitaxial film at a first growth rate on the main surface of the silicon substrate. The step of forming the second epitaxial film has a second process condition of growing the second epitaxial film at the second growth rate on the main surface of the silicon substrate. The second growth rate of the second epitaxial film is greater than the first growth rate of the first epitaxial film.

In the above method, since the halide gas is used to form the first epitaxial film, the first epitaxial film in the trench has substantially no voids. Also, since the second growth rate of the second epitaxial film is greater than the first growth rate of the first epitaxial film, the production time, that is, the manufacturing time of the device can be improved. Thus, planarization of the device surface is simplified.

Alternatively, the method may further include a step of polishing the surface of the second epitaxial film on the main surface of the silicon substrate after the step of forming the second epitaxial film.

Alternatively, in the step of forming the first epitaxial film, the halide gas may be made to flow at the first halide gas flow rate. In the step of forming the second epitaxial film, the halide gas may be made to flow at a second halide gas flow rate. The second halide gas flow rate is smaller than the first halide gas flow rate, so that the second growth rate of the second epitaxial film is greater than the first growth rate of the first epitaxial film. Also, in the step of forming the second epitaxial film, the mixed gas may not include a halide gas so that the second growth rate of the second epitaxial film is greater than the first growth rate of the first epitaxial film.

Alternatively, in the step of forming the first epitaxial film, the silicon source gas may be made to flow at the first silicon source gas flow rate. In the step of forming the second epitaxial film, the silicon source gas may be made to flow at a second silicon source gas flow rate. The flow rate of the second silicon source gas is greater than the flow rate of the first silicon source gas so that the second growth rate of the second epitaxial film is greater than the first growth rate of the first epitaxial film.

Alternatively, in the step of forming the first epitaxial film, the first process conditions may include a first process temperature. In the step of forming the second epitaxial film, the second process conditions may include a second process temperature. The second process temperature is higher than the first process temperature so that the second growth rate of the second epitaxial film is greater than the first growth rate of the first epitaxial film.

Alternatively, in the step of forming the first epitaxial film, the first process condition may include a first process pressure. In the step of forming the second epitaxial film, the second process condition may include a second process pressure. The second process pressure is greater than the first process pressure so that the second growth rate of the second epitaxial film is greater than the first growth rate of the first epitaxial film.

Alternatively, in the step of forming the first epitaxial film, the first epitaxial film may be formed by a low-pressure CVD method, and in the step of forming the second epitaxial film, the second epitaxial film may be formed by a low-pressure CVD method. Also, in the step of forming the first epitaxial film, the first epitaxial film may be formed by a low pressure CVD method, and in the step of forming the second epitaxial film, the second epitaxial film may be formed by an atmospheric pressure CVD method.

Alternatively, in the step of forming the second epitaxial film, the second process conditions may include at least two different parameters different from the first process conditions, so that the second growth rate of the second epitaxial film is faster than the first growth rate of the first epitaxial film. A growth rate is large and at least two different parameters are selected from the group consisting of halide gas flow rate, silicon source gas flow rate, process temperature and process pressure.

Alternatively, at least one parameter selected from the group consisting of halide gas flow rate, silicon source gas, process temperature, and process pressure is gradually changed so that the second growth rate of the second epitaxial film is faster than the first growth rate of the first epitaxial film. In order to increase the speed, the step of forming the first epitaxial film is continuously switched to the step of forming the second epitaxial film.

Alternatively, the method may further include a step of monitoring the surface temperature of the first epitaxial film from the main surface side of the silicon substrate by using a pyrometer. When the output signal of the pyrometer becomes substantially constant at a predetermined monitor temperature, the step of forming the first epitaxial film is switched to the step of forming the second epitaxial film.

Alternatively, the halide gas may be hydrogen chloride gas, chlorine gas, fluorine gas, chlorine trifluoride gas, hydrogen fluoride gas, or hydrogen bromide gas. Alternatively, the silicon source gas may be monosilane gas, disilane gas, dichlorosilane gas, or trichlorosilane gas.

Alternatively, the trench may have a bottom and side surfaces. The bottom of the trench includes a (110) crystal plane, and the side surfaces of the trench include a (111) crystal plane. Also, the bottom of the trench may include a (100) crystal plane, and the side surfaces of the trench may include a (100) crystal plane.

Alternatively, in the step of forming the first epitaxial film, the halide gas may be flowed at a standard flow rate, which is defined as X, and the unit is slm, and the first epitaxial film may be grown at a growth rate, which is defined as Y, and the unit is microns per minute. When the trench has an aspect ratio of less than 10, the standard flow rate of the halide gas and the growth rate of the first epitaxial film have a relationship: Y<0.2X+0.1. Also, when the trench has an aspect ratio equal to or greater than 10 and less than 20, the standard flow rate of the halide gas and the growth rate of the first epitaxial film have a relationship: Y<0.2X+0.05. Also, when the trench has an aspect ratio equal to or greater than 20, the standard flow rate of the halide gas and the growth rate of the first epitaxial film have a relationship: Y<0.2X.

Alternatively, the silicon substrate may have the first conductivity type. The trench includes a plurality of grooves in the silicon substrate. The silicon substrate between two adjacent grooves has a width which is larger than the width of the grooves. The first epitaxial film has the second conductivity type, and the first epitaxial film has an impurity concentration higher than that of the silicon substrate. Also, in the step of forming the first epitaxial film, the growth rate of the first epitaxial film near the opening of the groove may be slower than the growth rate of the first epitaxial film in the groove. Moreover, the width of the groove is defined as W, and the width of the silicon substrate between two adjacent grooves is defined as L. The impurity concentration of the silicon substrate is defined as N1, and the impurity concentration of the first epitaxial film is defined as N2. The width of the groove, the width of the silicon substrate, the impurity concentration of the silicon substrate, and the impurity concentration of the first epitaxial film have a relationship: N2*W=N1*L.

According to a second aspect of the present disclosure, a method for manufacturing a semiconductor device includes the steps of: forming a trench on a main surface of a silicon substrate; and forming in the trench by using a mixed gas of a silicon source gas and a halide gas epitaxial film, thereby filling the trench with the epitaxial film. In the step of forming the epitaxial film, no epitaxial film is formed on the main surface of the silicon substrate, and the step of forming the epitaxial film is completed when the top surface of the epitaxial film in the trench and the main surface of the silicon substrate are in the same plane.

In the above method, since the halide gas is used to form the epitaxial film, the epitaxial film in the trench has substantially no voids. Furthermore, planarization of the device surface is simplified.

According to a third aspect of the present disclosure, a method for manufacturing a semiconductor device includes the steps of: forming a mask for a trench on a main surface of a silicon substrate; etching the main surface of the silicon substrate by opening through the mask , forming a trench on the main surface of the silicon substrate; forming an epitaxial film in the trench of the silicon substrate with a mask by using a mixed gas of a silicon source gas and a halide gas, thereby filling the trench with the epitaxial film; and This mask is removed after the step of forming an epitaxial film. In the step of forming the epitaxial film, the epitaxial film is not formed on the mask, and the step of forming the epitaxial film is completed when the top surface of the epitaxial film in the trench and the main surface of the silicon substrate are on the same plane.

In the above method, since the halide gas is used to form the epitaxial film, the epitaxial film in the trench has substantially no voids. Furthermore, planarization of the device surface is simplified.

According to a fourth aspect of the present disclosure, a method for manufacturing a semiconductor device includes the steps of: forming a mask for a trench on a main surface of a silicon substrate; etching the main surface of the silicon substrate by opening through the mask A trench is formed on the main surface of a silicon substrate; an epitaxial film is formed in the trench of the silicon substrate with a mask by using a mixed gas of a silicon source gas and a halide gas, thereby filling the trench with an epitaxial film, wherein the epitaxial film The film is not formed on the mask, and when the top surface of the epitaxial film in the trench is higher than the main surface of the silicon substrate, the step of forming the epitaxial film is completed; the main surface of the silicon substrate is polished by using the mask as a polishing stop the surface of the epitaxial film on the side, thereby planarizing the main surface side of the silicon substrate; and removing the mask after the step of polishing the surface of the epitaxial film.

In the above method, since the halide gas is used to form the epitaxial film, the epitaxial film in the trench has substantially no voids. Furthermore, planarization of the device surface is simplified.

Alternatively, the method may further include the steps of: oxidizing the main surface of the silicon substrate to form a sacrificial oxide layer on the main surface after the step of removing the mask; and removing the sacrificial oxide layer.

According to a fifth aspect of the present disclosure, a method for manufacturing a semiconductor device includes the steps of: forming a mask for a trench on a main surface of a silicon substrate; etching the main surface of the silicon substrate by opening through the mask Forming a trench on the main surface of a silicon substrate; forming an epitaxial film on a mask and in the trench by using a mixture of silicon source gas and halide gas, thereby filling the trench with the epitaxial film; by using a mask as a polishing stop layer to polish the surface of the epitaxial film on the main surface side of the silicon substrate, thereby planarizing the main surface side of the silicon substrate; and removing the mask after the step of polishing the surface of the epitaxial film.

In the above method, since the halide gas is used to form the epitaxial film, the epitaxial film in the trench has substantially no voids. Furthermore, planarization of the device surface is simplified.

Alternatively, in the step of forming the epitaxial film, the epitaxial film on the mask may be made of a single crystal. Also, in the step of forming the epitaxial film, the epitaxial film on the mask may be made of polycrystalline.

According to a sixth aspect of the present disclosure, an epitaxial growth apparatus includes: a chamber; a chuck provided in the chamber and holding a silicon substrate having a main surface on which grooves are provided; a first gas flow controller for a gas flow rate of a source gas, wherein a silicon source gas is introduced into the chamber to form an epitaxial film on a silicon substrate; a second gas flow controller for controlling a gas flow rate of a halide source gas, wherein Introduction of halide gas into the chamber; temperature controller for controlling the process temperature in the chamber; pressure controller for controlling the process pressure in the chamber; high temperature for monitoring the surface temperature of the epitaxial film on the silicon substrate in the chamber and a master controller for controlling at least one of the first airflow controller, the second airflow controller, the temperature controller and the pressure controller based on the output signal of the pyrometer. The main controller switches at least one of the gas flow rate of the silicon source gas, the gas flow rate of the halide source gas, the process temperature, and the process pressure to increase the epitaxial film when the output signal of the pyrometer becomes substantially constant at a predetermined monitored surface temperature. growth rate.

By using the above apparatus, an epitaxial film is formed in the trench substantially without voids. Furthermore, planarization of the device surface is simplified.

According to a seventh aspect of the present disclosure, a method for manufacturing a semiconductor device includes the steps of: forming a first epitaxial film of a first conductivity type on a silicon substrate of a first conductivity type; forming a plurality of epitaxial films in the first epitaxial film trenches, wherein the first epitaxial film between adjacent two trenches has a width greater than the width of the trenches; a second epitaxial film of the second conductivity type is formed on the first epitaxial film and in the trenches, thereby The trench is filled with a second epitaxial film having a higher impurity concentration than the first epitaxial film. The step of forming the second epitaxial film includes a final step in which a mixed gas of a silicon source gas and a halide gas is used to form the second epitaxial film.

In the above method, the opening of the trench is not covered with the second epitaxial film before the trench is filled with the second epitaxial film. Also, since the first epitaxial film has a width larger than the width of the trenches between adjacent two trenches, the growth speed of the second epitaxial film is increased

While the invention has been described with reference to preferred embodiments thereof, it is to be understood that the invention is not limited to the preferred embodiments and constructions. The invention is intended to cover various modification and equivalent arrangements. In addition, while the various combinations and configurations are preferred, other combinations and configurations, including more, less or only a single element, are also within the spirit and scope of the invention.

Claims (23)

1, a kind of method that is used for producing the semiconductor devices may further comprise the steps:

First type surface top at silicon substrate (1) forms groove (4) and makes this groove (4) arrive this silicon substrate (1);

By using the mist of silicon source gas and halide gas, form first epitaxial film (20) on the first type surface of this silicon substrate (1) and in this groove (4), thereby fill this groove (4) with this first epitaxial film (20); And

By using another mist of silicon source gas and halide gas, go up formation second epitaxial film (21) at this first epitaxial film (20), wherein

The step that forms this first epitaxial film (20) has with grow on the first type surface of this silicon substrate (1) first process conditions of this first epitaxial film (20) of first speed of growth,

The step that forms this second epitaxial film (21) has with second process conditions of second speed of growth at this second epitaxial film (21) of the last growth of this first epitaxial film (20), and

Second speed of growth of this second epitaxial film (21) is bigger than first speed of growth of this first epitaxial film (20).

2, the method for claim 1, further comprising the steps of:

After the step that forms this second epitaxial film (21), the surface of this second epitaxial film (21) on this first epitaxial film (20) is polished.

3, the method for claim 1, wherein

In the step that forms this first epitaxial film (20), with the first halide gas flow velocity this halide gas is flowed,

In the step that forms this second epitaxial film (21), with the second halide gas flow velocity this halide gas is flowed, and

This second halide gas flow velocity is less than this first halide gas flow velocity, thereby second speed of growth of this second epitaxial film (21) is bigger than first speed of growth of this first epitaxial film (20).

4, the method for claim 1, wherein

In the step that forms this first epitaxial film (20), with the first silicon source gas flow velocity this silicon source gas is flowed,

In the step that forms this second epitaxial film (21), with the second silicon source gas flow velocity this silicon source gas is flowed, and

This first silicon source gas flow velocity of this second silicon source gas velocity ratio is big, thereby second speed of growth of this second epitaxial film (21) is bigger than first speed of growth of this first epitaxial film (20).

5, the method for claim 1, wherein

In the step that forms this first epitaxial film (20), these first process conditions comprise first technological temperature,

In the step that forms this second epitaxial film (21), these second process conditions comprise second technological temperature, and

This second technological temperature is than this first technological temperature height, thereby second speed of growth of this second epitaxial film (21) is bigger than first speed of growth of this first epitaxial film (20).

6, the method for claim 1, wherein

In the step that forms this first epitaxial film (20), these first process conditions comprise first operation pressure,

In the step that forms this second epitaxial film (21), these second process conditions comprise second operation pressure, and

This second operation pressure is bigger than this first operation pressure, thereby second speed of growth of this second epitaxial film (21) is bigger than first speed of growth of this first epitaxial film (20).

7, the method for claim 1, wherein

In the step that forms this first epitaxial film (20), this first epitaxial film (20) forms by the low pressure chemical vapor deposition method, and

In the step that forms this second epitaxial film (21), this second epitaxial film (21) forms by the low pressure chemical vapor deposition method.

8, the method for claim 1, wherein

In the step that forms this first epitaxial film (20), this first epitaxial film (20) forms by the low pressure chemical vapor deposition method, and

In the step that forms this second epitaxial film (21), this second epitaxial film (21) forms by atmospheric pressure CVD method.

9, a kind of method that is used for producing the semiconductor devices may further comprise the steps:

First type surface top at silicon substrate (1) forms groove (4) and makes this groove (4) arrive this silicon substrate (1);

By using the mist of silicon source gas and halide gas, form first epitaxial film (20) on the first type surface of this silicon substrate (1) and in this groove (4), thereby fill this groove (4) with this first epitaxial film (20); And

By using silicon source gas, go up formation second epitaxial film (21) at this first epitaxial film (20), wherein

The step that forms this first epitaxial film (20) has with grow on the first type surface of this silicon substrate (1) first process conditions of this first epitaxial film (20) of first speed of growth,

The step that forms this second epitaxial film (21) has with second process conditions of second speed of growth at this second epitaxial film (21) of the last growth of this first epitaxial film (20), and

Second speed of growth of this second epitaxial film (21) is bigger than first speed of growth of this first epitaxial film (20).

10, as each described method among the claim 1-9, wherein

In the step that forms this second epitaxial film (21), these second process conditions comprise at least two different parameters different with these first process conditions, thereby second speed of growth of this second epitaxial film (21) is bigger than first speed of growth of this first epitaxial film (20), and

From the group that halide gas flow velocity, silicon source gas flow velocity, technological temperature and operation pressure constitute, select these at least two different parameters.

11, as each described method among the claim 1-9, wherein

Thereby change second speed of growth that makes this second epitaxial film (21) the big mode of first speed of growth than this first epitaxial film (20) gradually so that be selected from least one parameter in the group that is made of halide gas flow velocity, silicon source gas, technological temperature and operation pressure, the step that will form this first epitaxial film (20) switches to the step that forms this second epitaxial film (21) continuously.

12, as each described method among the claim 1-9, also comprise step:

By using pyrometer (35) to monitor the surface temperature of this first epitaxial film (20), wherein from the main surface side of this silicon substrate (1)

When the output signal of this pyrometer (35) under predetermined monitoring temperature became substantially constant, the step that will form this first epitaxial film (20) switched to the step that forms this second epitaxial film (21).

13, as each described method among the claim 1-9, wherein

This halide gas is hydrogen chloride gas, chlorine, fluorine gas, chlorine trifluoride gas, hydrogen fluoride gas or bromize hydrogen gas.

14, as each described method among the claim 1-9, wherein

This silicon source gas is monosilane gas, b silane gas, dichlorosilane gas or trichlorosilane gas.

15, as each described method among the claim 1-9, wherein

This groove (4) has bottom and side surface,

The bottom of this groove (4) comprises (110) crystal face, and

The side surface of this groove (4) comprises (111) crystal face.

16, as each described method among the claim 1-9, wherein

This groove (4) has bottom and side surface,

The bottom of this groove (4) comprises (100) crystal face, and

The side surface of this groove (4) comprises (100) crystal face.

17, as each described method among the claim 1-9, wherein

In forming the step of this first epitaxial film (20), this halide gas flows with standard flow rate, and it is restricted to X, and unit is slm, and this first epitaxial film (20) is with a growth, and this speed of growth is restricted to Y, and unit be a micron per minute,

This groove (4) has the aspect ratio less than 10, and

The speed of growth of the standard flow rate of this halide gas and this first epitaxial film (20) has following relation:

Y＜0.2X+0.1。

18, as each described method among the claim 1-9, wherein

In the step that forms this first epitaxial film (20), this halide gas flows with standard flow rate, and it is restricted to X, and unit is slm, and this first epitaxial film (20) is with a growth, and this speed of growth is restricted to Y, and its unit is a micron per minute,

This groove (4) has and is equal to or greater than 10 and less than 20 aspect ratio, and

The speed of growth of the standard flow rate of this halide gas and this first epitaxial film (20) has following relation:

Y＜0.2X+0.05。

19, as each described method among the claim 1-9, wherein

In the step that forms this first epitaxial film (20), this halide gas flows with standard flow rate, and it is restricted to X, and unit is slm, and this first epitaxial film (20) is with a growth, and this speed of growth is restricted to Y, and unit is the micron per minute,

This groove (4) has and is equal to or greater than 20 aspect ratio, and

The speed of growth of the standard flow rate of this halide gas and this first epitaxial film (20) has following relation:

Y＜0.2X。

20, according to each described method among the claim 1-9, wherein

This silicon substrate (1) has first conduction type,

This groove (4) is included in a plurality of grooves (4) in this silicon substrate (1),

Silicon substrate (1) between adjacent two grooves (4) has a width, and this width is bigger than the width of this groove (4),

This first epitaxial film (20) has second conduction type, and

This first epitaxial film (20) has the high impurity concentration of impurity concentration than this silicon substrate (1).

21, method as claimed in claim 20, wherein

In forming the step of this first epitaxial film (20), near the speed of growth of this first epitaxial film (20) this groove (4) opening than this groove (4) in the speed of growth of this first epitaxial film (20) little.

22, method as claimed in claim 20, wherein

The width of this groove (4) is defined as W,

The width of the silicon substrate (1) between adjacent two grooves (4) is defined as L,

The impurity concentration of this silicon substrate (1) is defined as N1,

The impurity concentration of this first epitaxial film (20) is defined as N2,

The impurity concentration of the impurity concentration of the width of the width of this groove (4), this silicon substrate (1), this silicon substrate (1) and this first epitaxial film (20) has following relation:

N2×W＝N1×L。

23, a kind of epitaxial growth device comprises:

Chamber (30);

Chuck (31), it is arranged in this chamber (30) and fixing silicon substrate (1), and wherein this silicon substrate (1,32,70,80,90) has first type surface, and groove (4,72,83,93) is set on this first type surface;

First gas flow controller (36a) is used to control the gas flow rate of silicon source gas, wherein this silicon source gas is incorporated in this chamber (30), forms epitaxial film (20,21,73,84,94,95) so that go up at this silicon substrate (1,32,70,80,90);

Second gas flow controller (36b) is used to control the gas flow rate of halide source gas, wherein this halide gas is incorporated in this chamber (30);

Temperature controller (37) is used for controlling the technological temperature of this chamber (30);

Pressure controller (34) is used for controlling the operation pressure of this chamber (30);

Pyrometer (35) is used for this epitaxial film (20,21,73,84,94,95) is gone up in monitoring at this silicon substrate (1,32,70,80,90) of this chamber (30) surface temperature;

Master controller (38) is used for controlling according to the output signal of this pyrometer (35) at least one of this first gas flow controller (36a), this second gas flow controller (36b), this temperature controller (37) and this pressure controller (34), wherein

When the output signal of this pyrometer (35) under predetermined monitoring form surface temperature becomes substantially constant, this master controller (38) switches at least one in gas flow rate, this technological temperature and this operation pressure of gas flow rate, this halide source gas of this silicon source gas, to increase the speed of growth of this epitaxial film (20,21,73,84,94,95).

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