CN100547644C - Flat panel display and time schedule controller thereof - Google Patents
Flat panel display and time schedule controller thereof Download PDFInfo
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- CN100547644C CN100547644C CNB2006101423367A CN200610142336A CN100547644C CN 100547644 C CN100547644 C CN 100547644C CN B2006101423367 A CNB2006101423367 A CN B2006101423367A CN 200610142336 A CN200610142336 A CN 200610142336A CN 100547644 C CN100547644 C CN 100547644C
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- 230000009183 running Effects 0.000 claims description 9
- 238000001514 detection method Methods 0.000 abstract 2
- 206010047571 Visual impairment Diseases 0.000 description 13
- 239000010409 thin film Substances 0.000 description 8
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
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Abstract
一种时序控制器，适用于平面显示器。时序控制器包括电压检测电路、时钟发生器、第一多路复用器及第二多路复用器。电压检测电路检测操作电压的变化并从而输出重置信号。时钟发生器输出起始信号以及第一时钟信号。第一多路复用器接受重置信号的控制，并耦接至起始信号以及固定电压。第二多路复用器接受重置信号的控制，并耦接至第一时钟信号以及第二时钟信号，其中第二时钟信号的频率明显大于第一时钟信号的频率。
A timing controller is suitable for a flat panel display. The timing controller includes a voltage detection circuit, a clock generator, a first multiplexer and a second multiplexer. The voltage detection circuit detects the change of the operating voltage and outputs a reset signal. The clock generator outputs a start signal and a first clock signal. The first multiplexer is controlled by the reset signal and coupled to the start signal and a fixed voltage. The second multiplexer is controlled by the reset signal and coupled to the first clock signal and the second clock signal, wherein the frequency of the second clock signal is significantly greater than the frequency of the first clock signal.
Description
Technical field
The present invention relates to a kind of flat-panel screens, and be particularly related to a kind of flat-panel screens and time schedule controller thereof, utilize sequential control to eliminate the shutdown afterimage of flat-panel screens.
Background technology
Flat-panel screens, such as: LCD (Liquid Crystal Display, LCD) etc., because have that high image quality, volume are little, in light weight, low driving voltage, with advantage such as low consumpting power, therefore be widely used in personal digital assistant (Personal Digital Assistant, PDA), mobile phone, shoot with video-corder consumer communication or electronic products such as projector, mobile computer, desktop display, automobile-used display and projection TV, and (Cathode RayTube CRT) becomes the main flow of display to replace cathode-ray tube (CRT) gradually.
In general LCD framework; on display panels, see afterimage through regular meeting after the LCD shutdown; sometimes even treat just to disappear after the several seconds, this kind phenomenon not only is not inconsistent the expectation of user's vision, with the passing of time more can reduce the display quality of panel of LCD.With thin film transistor (TFT) (Thin FilmTransistor, TFT) LCD is an example, the one of the main reasons that causes shutdown afterimage (residual image) phenomenon is that the velocity of discharge of Thin Film Transistor-LCD pixel electrode is too slow, so that shutdown back electric charge can't snap-out release and residue in the liquid crystal capacitance, must treat a period of time discharge off fully again.
Please refer to Fig. 1, it has illustrated the synoptic diagram of conventional liquid crystal.In the LCD 10, time schedule controller (not illustrating in Fig. 1) output data is to pel array 16, it utilizes source electrode driver to receive and writes the scan columns data, and utilizes gate drivers 12 to select to write the scan columns of data, to show that the output picture is on panel of LCD.During shutdown, for eliminating the phenomenon of shutdown afterimage, the variation of reset circuit 14 detecting operation voltage VDD is with the scan columns standard-sized sheet pin XAO of output voltage signal Sr to gate drivers 12, make the thin film transistor (TFT) on all scan columns in gate drivers 12 conducting (turn on) the simultaneously pel arrays 16, make electric charge neutralize mutually and reach rapid discharge, shorten remaining electric charge and discharge fully the required time, thereby eliminate the phenomenon of shutdown afterimage.
Aforesaid LCD 10, for the influence that makes afterimage reduces, and must in LCD 10, increase reset circuit 14, and, open the thin film transistor (TFT) of all scan columns in the pel array 16 with notice gate drivers 12 when shutting down in gate drivers 12 increase scan columns standard-sized sheet pin XAO.Yet in the circuit realization of reality, extra reset circuit 14 that increases and scan columns standard-sized sheet pin XAO will cause the increase of circuit unit number, printed circuit board area and package area to become big, cost thereby significantly rising.
Summary of the invention
In view of this, purpose of the present invention is providing a kind of flat-panel screens exactly, and particularly relevant for a kind of flat-panel screens and time schedule controller thereof of utilizing, utilizes sequential control to eliminate the afterimage that produces when shutting down.
According to purpose of the present invention, a kind of time schedule controller is proposed, be applicable to flat-panel screens.Time schedule controller comprises voltage detecting circuit, clock generator, first multiplexer and second multiplexer.Thereby the variation of voltage detecting circuit detecting operation voltage and output reset signal.The clock generator output start signal and first clock signal.First multiplexer is accepted the control of reset signal, and is coupled to start signal and fixed voltage.Second multiplexer is accepted the control of reset signal, and is coupled to first clock signal and second clock signal, and wherein the frequency of second clock signal is obviously greater than the frequency of first clock signal.Wherein, when the flat-panel screens normal running, voltage-level detector is exported the reset signal of first level voltage according to the existence of operating voltage, controlling first multiplexer output start signal to gate drivers, and controls second multiplexer and exports first clock signal to gate drivers.Wherein, when flat-panel screens is shut down, voltage-level detector is exported the reset signal of second level voltage according to the variation of operating voltage, to control first multiplexer output fixed voltage to gate drivers, and control second multiplexer output second clock signal to gate drivers, wherein, first level voltage has relative level voltage with second level voltage.
According to purpose of the present invention, a kind of flat-panel screens is also proposed, comprise pel array, gate drivers and source electrode driver.It is characterized in that flat-panel screens also comprises voltage detecting circuit, time schedule controller, first multiplexer and second multiplexer.Thereby the variation of voltage detecting circuit detecting operation voltage and output reset signal.The time schedule controller output start signal and first clock signal.First multiplexer is accepted the control of reset signal, and is coupled to start signal and fixed voltage.Second multiplexer is accepted the control of reset signal, and is coupled to first clock signal and second clock signal, and wherein the frequency of second clock signal is obviously greater than the frequency of first clock signal.Wherein, when the flat-panel screens normal running, voltage-level detector is exported the reset signal of first level voltage according to the existence of operating voltage, controlling first multiplexer output start signal to gate drivers, and controls second multiplexer and exports first clock signal to gate drivers.Wherein, when flat-panel screens is shut down, voltage-level detector is exported the reset signal of second level voltage according to the variation of operating voltage, to control first multiplexer output fixed voltage to gate drivers, and control second multiplexer output second clock signal to gate drivers, wherein, first level voltage has relative level voltage with second level voltage.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, two preferred embodiments cited below particularly, and conjunction with figs. are described in detail below:
Description of drawings
Fig. 1 illustrates the synoptic diagram of conventional liquid crystal.
Fig. 2 A illustrates the calcspar according to the flat-panel screens of first embodiment of the invention.
Fig. 2 B illustrates the sequential chart of operating voltage VDD, reset signal Reset, output start signal STV_OUT and clock signal CPV_OUT according to first embodiment of the invention.
Fig. 3 illustrates the calcspar according to the flat-panel screens of second embodiment of the invention.
[primary clustering symbol description]
10: LCD
12,22,32: gate drivers
14: reset circuit
16,33: pel array
20,30: flat-panel screens
21,314: time schedule controller
23: pel array
212,312: voltage detecting circuit
214: clock generator
216,316: the first multiplexers
218,318: the second multiplexers
31: printed circuit board (PCB)
Embodiment
The invention provides a kind of flat-panel screens and time schedule controller thereof, utilize sequential control to eliminate the afterimage that when shutting down, produces.So, must additionally not increase reset circuit, and on gate drivers, must not increase scan columns standard-sized sheet pin yet, can eliminate afterimage rapidly at the thin film transistor (TFT) of all scan columns in when shutdown rapid switch on pixel array.The flat-panel screens of the embodiment of the invention explains with LCD, but is not limited to LCD, and all flat-panel screens all do not break away from the spirit and scope of the present invention.
Embodiment one
Please refer to Fig. 2 A, it has illustrated the calcspar according to the flat-panel screens of first embodiment of the invention.Flat-panel screens 20 for example is a kind of LCD, comprises time schedule controller 21, gate drivers 22, source electrode driver (not being illustrated among Fig. 2 A) and pel array 23.Time schedule controller 21 comprises voltage detecting circuit 212, clock generator 214, first multiplexer 216 and second multiplexer 218.Voltage detecting circuit 212 is in order to the variation of detecting operation voltage VDD, thus and output reset signal Reset.Clock generator 214 is in order to the required start signal STV and the first clock signal C PV1 of output gate drivers 22 normal runnings.First multiplexer 216 is accepted the control of reset signal Reset, in order to select start signal STV or fixed voltage as output signal STV_OUT, wherein this fixed voltage has relative level voltage with start signal STV, for example, when the required start signal STV of normal running is low level voltage, this fixed voltage can be operating voltage VDD or time schedule controller 21 other from producing high level voltage.
Please refer to Fig. 2 B, it has illustrated the sequential chart of operating voltage VDD, reset signal Reset, output start signal STV_OUT and clock signal CPV_OUT according to first embodiment of the invention.When flat-panel screens 20 normal runnings, voltage detecting circuit 212 is according to operating voltage VDD (=V
0) existence, the reset signal Reset (that is voltage level is H) of output high level, to control first multiplexer, 216 output start signal STV to gate drivers 22, just, the output signal STV_OUT that real-time sequence controller 21 is exported is start signal STV.Simultaneously, voltage detecting circuit 212 and the reset signal Reset (that is voltage level is H) that exports high level are to control second multiplexer, 218 outputs, the first clock signal C PV1 to gate drivers 22, just, in real time the output signal CPV_OUT that exported of sequence controller 21 is the first clock signal C PV1.At this moment, gate drivers 22 is exported signal to pel array 23 according to normal start signal STV and clock signal C PV1, carries out normal image and shows.
When flat-panel screens 20 shutdown, for instance, it (is 0.7V that voltage detecting circuit 212 is reduced to 70 of percentage at operating voltage VDD
0) time, the reset signal Reset of output low level (that is voltage level is L) with control first multiplexer, 216 output function voltage VDD or fixedly high level voltage to gate drivers 22, just, in real time the output signal STV_OUT that exported of sequence controller 21 is converted to operating voltage VDD or fixing high level voltage.Simultaneously, the reset signal Reset (that is voltage level is L) of voltage detecting circuit 212 and output low level is to control second multiplexer, 218 this second clock signal of output CPV2 to gate drivers 23, just, in real time the output signal CPV_OUT that exported of sequence controller 21 is converted to second clock signal CPV2.
At this moment, gate drivers 23 is according to the operating voltage VDD that is received or fixedly high level voltage and obviously the clock signal C PV2 of higher-frequency, the rapid signal of output high level voltage Vgh, the thin film transistor (TFT) of all scan columns and reach the effect of eliminating the shutdown afterimage in the switch on pixel array 23 rapidly.
Embodiment two
Please refer to Fig. 3, it has illustrated the calcspar according to the flat-panel screens of second embodiment of the invention.Flat-panel screens 30, for example be a kind of LCD, comprise gate drivers 32, source electrode driver (not being illustrated among the 3rd figure), pel array 33, voltage detecting circuit 312, time schedule controller 314, first multiplexer 316 and second multiplexer 318.Voltage detecting circuit 312, time schedule controller 314, first multiplexer 316 and second multiplexer 318 can be arranged on the printed circuit board (PCB) 31.Voltage detecting circuit 312 is in order to the variation of detecting operation voltage VDD, thus and output reset signal Reset.Time schedule controller 314 is in order to the required start signal STV and the first clock signal C PV1 of output gate drivers 32 normal runnings.First multiplexer 316 is accepted the control of reset signal Reset, in order to select start signal STV or fixed voltage as output signal STV_OUT, wherein this fixed voltage has relative level voltage with start signal STV, for example, when start signal STV was low level voltage, fixed voltage was the high level voltage that other circuit produces on operating voltage VDD or the printed circuit board (PCB) 31.
Referring again to 2B figure, described as first embodiment, when flat-panel screens 30 normal runnings, voltage detecting circuit 312 is according to operating voltage VDD (=V
0) existence, the reset signal Reset of output high level, to control first multiplexer, 316 output start signal STV to gate drivers 32, and control second multiplexer, 318 outputs, the first clock signal C PV1 to gate drivers 32, make the normal signal of gate drivers 32 outputs to pel array 23, show to carry out normal image.And when flat-panel screens 30 shutdown, voltage detecting circuit 312 is reduced to 70 (=0.7V of percentage at operating voltage VDD
0) time output low level reset signal Reset, with control first multiplexer, 316 output function voltage VDD or fixedly high level voltage to gate drivers 32, and control second multiplexer, 318 this second clock signal of output CPV2 to gate drivers 33, make gate drivers 33 according to operating voltage VDD or fixedly high level voltage and obviously the clock signal C PV2 of higher-frequency, the signal of output high level voltage Vgh, the thin film transistor (TFT) of all scan columns is to reach the effect of eliminating the shutdown afterimage in the rapid switch on pixel array 23.
The disclosed flat-panel screens of the above embodiment of the present invention is a kind of flat-panel screens of utilizing the sequential control of time schedule controller internal circuit or other circuit of flat-panel screens with elimination shutdown afterimage.So, must additionally not increase reset circuit, and on gate drivers, must not increase scan columns standard-sized sheet pin yet, can eliminate afterimage rapidly at the thin film transistor (TFT) of all scan columns in when shutdown rapid switch on pixel array.
In sum; though the present invention discloses as above with two preferred embodiments; right its is not in order to limit the present invention; any those of ordinary skills; without departing from the spirit and scope of the present invention; should do various changes and retouching, so protection scope of the present invention should be defined by the appended claims.
Claims (14)
1. a time schedule controller is applicable to flat-panel screens, comprising:
Voltage detecting circuit, in order to the variation of detecting operation voltage, thereby and output reset signal;
Clock generator is in order to the output start signal and first clock signal;
First multiplexer is accepted the control of this reset signal, and is coupled to this start signal and fixed voltage; And
Second multiplexer is accepted the control of this reset signal, and is coupled to this first clock signal and second clock signal, and wherein the frequency of this second clock signal is obviously greater than the frequency of this first clock signal;
Wherein, when this flat-panel screens normal running, this voltage detecting circuit is exported this reset signal of first level voltage according to the existence of this operating voltage, export the gate drivers of this start signal to control this first multiplexer, and control this second multiplexer and export this first clock signal to this gate drivers to this flat-panel screens;
Wherein, when this flat-panel screens shutdown, this voltage detecting circuit is exported this reset signal of second level voltage according to the variation of this operating voltage, export this fixed voltage to this gate drivers to control this first multiplexer, and control this second multiplexer and export this second clock signal to this gate drivers, wherein, this first level voltage is the level voltage with the corresponding relation of height with this second level voltage.
2. time schedule controller as claimed in claim 1, wherein this fixed voltage is the level voltage with the corresponding relation of height with this start signal.
3. time schedule controller as claimed in claim 1, wherein this time schedule controller also comprises oscillator, in order to produce this second clock signal.
4. time schedule controller as claimed in claim 1, wherein this second clock signal is the oscillating clock signal that the oscillator by this flat-panel screens provides.
5. time schedule controller as claimed in claim 1, wherein when this flat-panel screens shutdown, this voltage detecting circuit is exported this reset signal of this second level voltage when this operating voltage is reduced to certain proportion, export this fixed voltage to control this first multiplexer, and control this second multiplexer and export this second clock signal.
6. time schedule controller as claimed in claim 1, wherein this flat-panel screens is a LCD.
7. flat-panel screens, comprising: pel array, gate drivers and source electrode driver is characterized in that: this flat-panel screens also comprises:
Voltage detecting circuit, in order to the variation of detecting operation voltage, thereby and output reset signal:
Time schedule controller is in order to the output start signal and first clock signal;
First multiplexer is accepted the control of this reset signal, and is coupled to this start signal and fixed voltage; And
Second multiplexer is accepted the control of this reset signal, and is coupled to this first clock signal and second clock signal, and wherein the frequency of this second clock signal is obviously greater than the frequency of this first clock signal;
Wherein, when this flat-panel screens normal running, this voltage detecting circuit is exported this reset signal of first level voltage according to the existence of this operating voltage, export this start signal to this gate drivers to control this first multiplexer, and control this second multiplexer and export this first clock signal to this gate drivers;
Wherein, when this flat-panel screens shutdown, this voltage detecting circuit is exported this reset signal of second level voltage according to the variation of this operating voltage, export this fixed voltage to this gate drivers to control this first multiplexer, and control this second multiplexer and export this second clock signal to this gate drivers, wherein, this first level voltage is the level voltage with the corresponding relation of height with this second level voltage.
8. flat-panel screens as claimed in claim 7, wherein this fixed voltage is the level voltage with the corresponding relation of height with this start signal.
9. flat-panel screens as claimed in claim 7, wherein this time schedule controller also comprises oscillator, in order to produce this second clock signal.
10. flat-panel screens as claimed in claim 7, wherein this second clock signal is produced by the oscillator of this flat-panel screens.
11. flat-panel screens as claimed in claim 7, wherein when this flat-panel screens shutdown, this voltage detecting circuit is exported this reset signal of this second level voltage when this operating voltage is reduced to certain proportion, export this fixed voltage to control this first multiplexer, and control this second multiplexer and export this second clock signal.
12. flat-panel screens as claimed in claim 7 is a LCD.
13. flat-panel screens as claimed in claim 7, wherein, this voltage detecting circuit, this time schedule controller, this first multiplexer, and this second multiplexer be integrated in single IC for both.
14. flat-panel screens as claimed in claim 7, wherein, this voltage detecting circuit, this time schedule controller, this first multiplexer, and this second multiplexer be formed on the printed circuit board (PCB) discretely.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101423367A CN100547644C (en) | 2006-10-10 | 2006-10-10 | Flat panel display and time schedule controller thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101423367A CN100547644C (en) | 2006-10-10 | 2006-10-10 | Flat panel display and time schedule controller thereof |
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| CN101162567A CN101162567A (en) | 2008-04-16 |
| CN100547644C true CN100547644C (en) | 2009-10-07 |
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| CNB2006101423367A Expired - Fee Related CN100547644C (en) | 2006-10-10 | 2006-10-10 | Flat panel display and time schedule controller thereof |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI411993B (en) * | 2010-12-29 | 2013-10-11 | Au Optronics Corp | Flat display apparatus |
| CN106952610B (en) * | 2017-05-27 | 2023-05-23 | 深圳市明微电子股份有限公司 | Shadow eliminating control circuit and method for LED display screen |
| CN107644609B (en) * | 2017-10-11 | 2020-11-20 | 京东方科技集团股份有限公司 | Circuit and driving method for improving signal amplitude of GOA signal end during shutdown and gate driving circuit |
| CN108510932B (en) * | 2018-03-30 | 2021-08-10 | 京东方科技集团股份有限公司 | Level conversion chip, control method thereof and shutdown drive circuit |
| CN109192168B (en) * | 2018-10-17 | 2021-08-20 | 维沃移动通信有限公司 | Pixel charging method and electronic equipment |
| CN112150976A (en) * | 2019-06-28 | 2020-12-29 | 格科微电子（上海）有限公司 | Power-down screen cleaning method for liquid crystal display screen |
| CN112967692B (en) * | 2021-02-26 | 2022-01-04 | 惠科股份有限公司 | Ghost eliminating circuit and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6476590B2 (en) * | 2000-10-11 | 2002-11-05 | Au Optronics Corporation | Residual image improving system for a liquid crystal display (LCD) |
| CN1141687C (en) * | 1996-11-26 | 2004-03-10 | 夏普株式会社 | Erasing device for liquid crystal display image and liquid crystal display device containing the device |
| CN1160678C (en) * | 1997-05-27 | 2004-08-04 | 国际商业机器公司 | LCD Monitor |
| CN1547730A (en) * | 2002-05-31 | 2004-11-17 | 索尼株式会社 | Liquid crystal display device, method thereof, and mobile terminal |
| US7109965B1 (en) * | 1998-09-15 | 2006-09-19 | Lg.Philips Lcd Co., Ltd. | Apparatus and method for eliminating residual image in a liquid crystal display device |
-
2006
- 2006-10-10 CN CNB2006101423367A patent/CN100547644C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1141687C (en) * | 1996-11-26 | 2004-03-10 | 夏普株式会社 | Erasing device for liquid crystal display image and liquid crystal display device containing the device |
| CN1160678C (en) * | 1997-05-27 | 2004-08-04 | 国际商业机器公司 | LCD Monitor |
| US7109965B1 (en) * | 1998-09-15 | 2006-09-19 | Lg.Philips Lcd Co., Ltd. | Apparatus and method for eliminating residual image in a liquid crystal display device |
| US6476590B2 (en) * | 2000-10-11 | 2002-11-05 | Au Optronics Corporation | Residual image improving system for a liquid crystal display (LCD) |
| CN1547730A (en) * | 2002-05-31 | 2004-11-17 | 索尼株式会社 | Liquid crystal display device, method thereof, and mobile terminal |
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| CN101162567A (en) | 2008-04-16 |
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