CN100541782C - Package structure with stacked platform and packaging method thereof - Google Patents
Package structure with stacked platform and packaging method thereof Download PDFInfo
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- CN100541782C CN100541782C CNB2005101059234A CN200510105923A CN100541782C CN 100541782 C CN100541782 C CN 100541782C CN B2005101059234 A CNB2005101059234 A CN B2005101059234A CN 200510105923 A CN200510105923 A CN 200510105923A CN 100541782 C CN100541782 C CN 100541782C
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- 238000004806 packaging method and process Methods 0.000 title claims description 27
- 238000000034 method Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 72
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 57
- 239000000565 sealant Substances 0.000 claims abstract description 49
- 239000007788 liquid Substances 0.000 claims abstract description 48
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 25
- 239000000084 colloidal system Substances 0.000 claims description 25
- 239000003292 glue Substances 0.000 claims description 11
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 239000004332 silver Substances 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 description 21
- 239000010931 gold Substances 0.000 description 21
- 125000006850 spacer group Chemical group 0.000 description 9
- 238000007789 sealing Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 235000002017 Zea mays subsp mays Nutrition 0.000 description 1
- 241000482268 Zea mays subsp. mays Species 0.000 description 1
- 230000004308 accommodation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 208000018883 loss of balance Diseases 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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Abstract
Description
技术领域 technical field
本发明涉及一种封装结构,且特别涉及一种具有堆叠平台之封装结构。The present invention relates to a packaging structure, and in particular to a packaging structure with a stacking platform.
背景技术 Background technique
随着芯片封装演进,目前的封装技术已可完成极为轻薄的封装芯片。而薄芯片可再利用芯片堆叠的技术把多个薄芯片封装在一起,形成所谓的复封装(package in package)芯片或多芯片模块(multi chip module,MCM)。请参照图1,其为传统复封装芯片之结构剖面图,封装结构100包括基板10、第一封装件20、第二封装件30及封胶40。第一封装件20包括芯片21、芯片23及间隔物(spacer)50,芯片21设置于基板10上,并通过金线22与基板10电连接。芯片23设置于芯片21上方,并分别以金线24及金线25与芯片21及基板10电连接。第二封装件30设置于间隔物50之表面51上。第二封装件30包括基板31及芯片32,芯片32设置于基板31上并以金线33电连接基板31,第二封装件30并以金线35与基板10电连接。封胶34将基板31、芯片32及金线33覆盖起来。封胶40包覆基板10之表面12、第一封装件20及第二封装件30,基板10底部具有多个焊球(solder ball)11。With the evolution of chip packaging, the current packaging technology can complete extremely thin packaged chips. Thin chips can be packaged together with chip stacking technology to form a so-called package in package chip or multi chip module (MCM). Please refer to FIG. 1 , which is a cross-sectional view of a traditional repackaged chip structure. The
但目前的芯片堆叠技术,对于在基板上已有金线连结(wire bond)的半成品芯片并未能提供适当的保护,因此堆叠的芯片容易倾斜而将连结的线型压坏,造成封装的失败,降低生产合格率,使得生产成本提高。如图1中由于间隔物50仅以表面51与第二封装件30接触,由于接触面积不足,容易使得第二封装件30因为失去平衡或轻微的震动或碰撞而倾斜,而压到金线22、金线24及金线25,造成封装失败。再者,由于间隔物50以及金线22、金线24及金线25阻挡,容易造成封胶40在灌模时不能完全包覆各元件而产生孔洞,尤其是芯片23及间隔物50之间,极易有气体孔洞产生。此孔洞将可能于后续工艺之温度变化中,产生爆米花效应(popcorneffect)而导致封胶破裂,而降低产品合格率。However, the current chip stacking technology does not provide proper protection for semi-finished chips with gold wire bonds on the substrate. Therefore, the stacked chips are easy to tilt and the connected wires will be crushed, resulting in package failure. , Reduce production pass rate, make production cost increase. As shown in Figure 1, since the spacer 50 only contacts the
发明内容 Contents of the invention
鉴于上述情况,本发明的目的就是提供一种具有堆叠平台之封装结构,利用液态封胶形成堆叠平台,提供芯片置放,可保护需维持的线型位置及粘合部位。In view of the above, the object of the present invention is to provide a packaging structure with a stacking platform, which uses a liquid sealant to form a stacking platform, provides chip placement, and can protect the linear position and bonding parts that need to be maintained.
根据本发明的目的,提出一种封装结构,包括第一基板、第一封装件、第二封装件及封胶,第一基板具有第一表面。第一封装件包括第一芯片及液态封胶,第一芯片设置于第一基板上,并通过第一金线与第一基板电连接。液态封胶,包括由第一胶体在该第一芯片之第二表面上形成的围坝结构,其在该第一芯片之第二表面围出容置空间,以及在该围坝结构所围成的容置空间内填入的第二胶体,该第二胶体的粘滞性小于该第一胶体,流动性大于该第一胶体,该液态封胶覆盖第一芯片之第二表面,并覆盖部分之第一金线,液态封胶之表面形成平台。第二封装件设置于平台之上,封胶包覆至少部分之第一基板之第一表面、第一封装件及第二封装件。According to the object of the present invention, a packaging structure is proposed, including a first substrate, a first package, a second package and a sealant. The first substrate has a first surface. The first package includes a first chip and a liquid sealant. The first chip is arranged on the first substrate and is electrically connected to the first substrate through the first gold wire. The liquid sealant includes a dam structure formed by the first glue on the second surface of the first chip, which encloses an accommodating space on the second surface of the first chip, and the dam structure surrounded by the dam structure The second colloid filled in the accommodating space, the viscosity of the second colloid is less than the first colloid, the fluidity is greater than the first colloid, the liquid sealant covers the second surface of the first chip, and covers part of the The first gold wire, the surface of the liquid sealant forms a platform. The second package is disposed on the platform, and the sealing glue covers at least part of the first surface of the first substrate, the first package and the second package.
根据本发明的再一目的,提出一种封装方法。首先,提供第一基板,具有第一表面。接着,设置第一芯片于第一基板上。然后,以第一金线电连接第一芯片与第一基板。接着,以第一胶体在该第一芯片之第二表面上形成围坝结构,其在该第一芯片之第二表面围出容置空间;以第二胶体填入该围坝结构所围成的容置空间内,该第二胶体的粘滞性小于上述第一胶体,流动性大于上述第一胶体,该第二胶体与该围坝结构形成液态封胶,该液态封胶覆盖第一芯片之第二表面及部分第一金线,液态封胶之表面形成平台。然后,设置第二封装件于平台上方。接着,以封胶包覆第一封装件、第二封装件及至少部分之基板之第一表面。According to still another object of the present invention, a packaging method is proposed. Firstly, a first substrate is provided, having a first surface. Next, the first chip is set on the first substrate. Then, the first chip and the first substrate are electrically connected with the first gold wire. Then, the first colloid is used to form a dam structure on the second surface of the first chip, which encloses an accommodating space on the second surface of the first chip; the second colloid is filled into the dam structure surrounded In the accommodating space, the viscosity of the second colloid is lower than that of the first colloid, and its fluidity is greater than that of the first colloid. The second colloid forms a liquid sealant with the dam structure, and the liquid sealant covers the first chip. The second surface and part of the first gold wire form a platform on the surface of the liquid sealant. Then, a second package is disposed on the platform. Then, encapsulating the first package, the second package and at least part of the first surface of the substrate with sealing glue.
为让本发明之上述目的、特征、和优点能更明显易懂,下文特举两个实施例,并配合附图,作详细说明如下:In order to make the above-mentioned purposes, features, and advantages of the present invention more obvious and understandable, two embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows:
附图说明 Description of drawings
图1为传统复封装芯片之结构剖面图;Fig. 1 is the structural sectional view of traditional re-packaging chip;
图2为本发明之第一实施例的一种封装结构之侧视图;Fig. 2 is a side view of a package structure of the first embodiment of the present invention;
图3A~3G为本发明之第一实施例的封装结构之封装流程图;及3A-3G are the packaging flowchart of the packaging structure of the first embodiment of the present invention; and
图4为本发明之第二实施例的封装结构之侧视图。FIG. 4 is a side view of the package structure of the second embodiment of the present invention.
主要元件标记说明Description of main component marking
100、200、300:封装结构100, 200, 300: package structure
10、31、210、231、310、331:基板10, 31, 210, 231, 310, 331: substrate
11、211、311:焊球11, 211, 311: solder balls
12、51、212、226、312、326:表面12, 51, 212, 226, 312, 326: surface
20、220、320:第一封装件20, 220, 320: the first package
21、23、33、221、223、232、321、323、332:芯片21, 23, 33, 221, 223, 232, 321, 323, 332: chips
22、24、25、33、35、222、224、225、233、235、322、324、325、333、335:金线22, 24, 25, 33, 35, 222, 224, 225, 233, 235, 322, 324, 325, 333, 335: gold wire
30、230、330:第二封装件30, 230, 330: second package
34、40、234、240、334、340:封胶34, 40, 234, 240, 334, 340: sealant
50:间隔物50: spacer
250、350:液态封胶250, 350: Liquid sealant
251、351:平台251, 351: Platform
252、352:围坝结构252, 352: Dam structure
253、353:胶体253, 353: colloid
260、360:银胶260, 360: silver glue
具体实施方式 Detailed ways
实施例一Embodiment one
请参照图2,其为本发明之第一实施例的一种封装结构之侧视图。封装结构200包括基板210、第一封装件220、第二封装件230及封胶240。第一封装件220包括芯片221、芯片223及液态封胶250,芯片221设置于基板210上,并通过金线222与基板210电连接。芯片223设置于芯片221上方,并分别以金线224及金线225与芯片221及基板210电连接。Please refer to FIG. 2 , which is a side view of a package structure according to the first embodiment of the present invention. The
第二封装件230设置于液态封胶250之表面所形成之平台251上。第二封装件230包括基板231及芯片232,芯片232设置于基板231上并以金线233电连接基板231,第二封装件230并以金线235与基板210电连接。封胶234覆盖基板231、芯片232及金线233。封胶240包覆基板210之表面212、第一封装件220及第二封装件230,基板210底部具有多个焊球(solder ball)211。The
请参照图3A~3G,其为本发明之第一实施例的封装结构之封装流程图。首先,请参照图3A,提供基板210,基板210具有表面212,之后,设置芯片221于表面212上。接着,请参照图3B,在芯片221之表面226上设置芯片223。然后,请参照图3C,以金线222电连接芯片221与基板210,以金线224电连接芯片223与芯片221,并以金线225电连接芯片223与基板210。接着,请参照图3D,以粘滞性较大,不会任意流动之胶体形成围坝结构252于芯片221之表面226上。较佳地围坝结构252形成于表面226之周围,以于表面226之中心部分围出一容置空间。Please refer to FIGS. 3A-3G , which are the packaging flowcharts of the packaging structure of the first embodiment of the present invention. First, please refer to FIG. 3A , a
然后,请参照图3E,以粘滞性较小、流动性较大之胶体253,其类似银胶,填入围坝结构252所围成之容置空间内,胶体253与围坝结构252形成液态封胶250。液态封胶250覆盖芯片221之表面226、部分金线222、芯片223、金线224以及部分金线225。之后,将封装结构送进烤箱内烘烤。于液态封胶250固化后,再将液态封胶250之表面磨平,以形成可供置放之平台251,第一封装件220于是形成。Then, please refer to FIG. 3E , fill the containing space surrounded by the
接着,请参照图3F,以银胶260将第二封装件230粘接于平台251上。第二封装件230包括基板231、芯片232及封胶234。芯片232设置于基板231上并以金线233与基板231电连接。封胶234覆盖芯片232、金线233以及基板231。第二封装件230还以金线235与基板210电连接。之后,请参照图3G,以封胶240覆盖基板210之至少部分之表面212、第一封装件220以及第二封装件230,本实施例以封胶240覆盖基板210之全部之表面212为例说明之。然后,于基板210底部形成多个焊球211,以完成封装结构200之封装步骤。Next, referring to FIG. 3F , the
在本实施例之封装结构200中,以液态封胶250包覆芯片221及223,及其所连接之金线222、224及225。如此,当第二封装件230叠置于芯片221及223之上时,液态封胶250包覆了芯片221及223。故液态封胶250比图1所示之间隔物50,更能对芯片221和223,及与其相连之金线222、224及225,提供更完善地保护,以维持金线222、224及225之线型,避免金线222、224及225短路。In the
此外,由于液态封胶250之表面形成面积与芯片221之面积相当之平台,以供第二封装件230置放。与图1中形成于芯片21上方,芯片23之侧的间隔物50相比较,液态封胶250所提供之平台251的表面大于间隔物50之面积,且平台251可接触到第二封装件230之底面的大部分区域。故本实施例之第二封装件230得以平稳地置放于平台251上,可避免第二封装件230产生倾斜之现象。In addition, since the surface of the
再者,由于本实施例使用粘滞性较小、流动性较大之液态封胶250来保护芯片221及223,液态封胶250产生气体孔洞的机率远比图1之使用灌模工艺来形成封胶40的机率小,故本实施例之封装结构还具有提高合格率之优点。Furthermore, since this embodiment uses a
实施例二Embodiment two
请参照图4,其为本发明之第二实施例的封装结构之侧视图。本实施例之封装结构300与第一实施例之封装结构200的主要不同之处,在于液态封胶与基板接触的部分。本实施例之液态封胶350除完全覆盖芯片321之表面326外,还覆盖部分基板310之表面312。液态封胶350的形成方式例如为,先形成围坝结构352于基板310之表面312,围坝结构352位于距离芯片321一段距离之外围。之后,将胶体353填入围坝352所围成之容置空间内,形成液态封胶350覆盖部分基板310之表面312及芯片321之表面326。其余元件之连接关系与形成步骤与第一实施例相同,不再赘述。Please refer to FIG. 4 , which is a side view of the package structure of the second embodiment of the present invention. The main difference between the
由于第二实施例所形成之封胶350的平台351之面积,大于第一实施例之封胶250之平台251之面积。故本实施例可提供更大的平台351,以使第二封装件330得以更平稳地置放于平台351上。Because the area of the
本发明上述实施例所披露之具有堆叠平台之封装结构,以封胶包覆芯片及其连接金线,如此可以提供有效地保护芯片及其连接金线的保护,并于液态封胶表面形成平台,供另一芯片置放。故本发明之封装结构可以简单之工艺亦提供芯片一较佳之堆叠平台,避免堆叠芯片倾斜压坏连结之金线造成损坏,可以提高产品的合格率,降低生产成本,为本发明之优点及特色。The packaging structure with a stacking platform disclosed in the above embodiments of the present invention covers the chip and its connecting gold wires with encapsulant, which can effectively protect the chip and its connecting gold wires, and form a platform on the surface of the liquid encapsulant , for another chip placement. Therefore, the packaging structure of the present invention can provide a better stacking platform for chips with a simple process, avoiding the damage caused by the stacked chips being tilted and crushing the connecting gold wires, which can improve the pass rate of products and reduce production costs, which are the advantages and characteristics of the present invention. .
综上所述,虽然本发明已以较佳实施例披露如上,然其并非用以限定本发明,任何所属技术领域的技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与改进,因此本发明的保护范围当视权利要求所界定者为准。In summary, although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications without departing from the spirit and scope of the present invention. Changes and improvements, so the protection scope of the present invention should be defined by the claims.
Claims (14)
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US20040113253A1 (en) * | 2002-10-08 | 2004-06-17 | Chippac, Inc. | Semiconductor stacked multi-package module having inverted second package |
US20040183180A1 (en) * | 2003-03-21 | 2004-09-23 | Advanced Semiconductor Engineering, Inc. | Multi-chips stacked package |
US20050133916A1 (en) * | 2003-12-17 | 2005-06-23 | Stats Chippac, Inc | Multiple chip package module having inverted package stacked over die |
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US20040113253A1 (en) * | 2002-10-08 | 2004-06-17 | Chippac, Inc. | Semiconductor stacked multi-package module having inverted second package |
US20040183180A1 (en) * | 2003-03-21 | 2004-09-23 | Advanced Semiconductor Engineering, Inc. | Multi-chips stacked package |
US20050133916A1 (en) * | 2003-12-17 | 2005-06-23 | Stats Chippac, Inc | Multiple chip package module having inverted package stacked over die |
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