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CN100541782C - Package structure with stacked platform and packaging method thereof - Google Patents

Package structure with stacked platform and packaging method thereof Download PDF

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Publication number
CN100541782C
CN100541782C CNB2005101059234A CN200510105923A CN100541782C CN 100541782 C CN100541782 C CN 100541782C CN B2005101059234 A CNB2005101059234 A CN B2005101059234A CN 200510105923 A CN200510105923 A CN 200510105923A CN 100541782 C CN100541782 C CN 100541782C
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chip
package
substrate
gold wire
platform
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CN1941360A (en
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林圣惟
宋威岳
黄文彬
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A package structure includes a first substrate, a first package, a second package and a sealant, wherein the first substrate has a first surface. The first package comprises a first chip and liquid sealant, wherein the first chip is arranged on the first substrate and is electrically connected with the first substrate through a first gold wire. The liquid sealant comprises a dam structure formed by a first sealant on the second surface of the first chip, an accommodating space surrounded by the dam structure, and a second sealant filled in the accommodating space surrounded by the dam structure, wherein the viscosity of the second sealant is smaller than that of the first sealant, the fluidity of the second sealant is larger than that of the first sealant, the liquid sealant covers the second surface of the first chip and covers a part of the first gold wire, and a platform is formed on the surface of the liquid sealant. The second package is disposed on the platform, and the encapsulant encapsulates at least a portion of the first surface of the first substrate, the first package, and the second package.

Description

具有堆叠平台之封装结构及其封装方法 Packaging structure with stacking platform and packaging method thereof

技术领域 technical field

本发明涉及一种封装结构,且特别涉及一种具有堆叠平台之封装结构。The present invention relates to a packaging structure, and in particular to a packaging structure with a stacking platform.

背景技术 Background technique

随着芯片封装演进,目前的封装技术已可完成极为轻薄的封装芯片。而薄芯片可再利用芯片堆叠的技术把多个薄芯片封装在一起,形成所谓的复封装(package in package)芯片或多芯片模块(multi chip module,MCM)。请参照图1,其为传统复封装芯片之结构剖面图,封装结构100包括基板10、第一封装件20、第二封装件30及封胶40。第一封装件20包括芯片21、芯片23及间隔物(spacer)50,芯片21设置于基板10上,并通过金线22与基板10电连接。芯片23设置于芯片21上方,并分别以金线24及金线25与芯片21及基板10电连接。第二封装件30设置于间隔物50之表面51上。第二封装件30包括基板31及芯片32,芯片32设置于基板31上并以金线33电连接基板31,第二封装件30并以金线35与基板10电连接。封胶34将基板31、芯片32及金线33覆盖起来。封胶40包覆基板10之表面12、第一封装件20及第二封装件30,基板10底部具有多个焊球(solder ball)11。With the evolution of chip packaging, the current packaging technology can complete extremely thin packaged chips. Thin chips can be packaged together with chip stacking technology to form a so-called package in package chip or multi chip module (MCM). Please refer to FIG. 1 , which is a cross-sectional view of a traditional repackaged chip structure. The package structure 100 includes a substrate 10 , a first package 20 , a second package 30 and a sealant 40 . The first package 20 includes a chip 21 , a chip 23 and a spacer 50 . The chip 21 is disposed on the substrate 10 and is electrically connected to the substrate 10 through gold wires 22 . The chip 23 is disposed above the chip 21 and is electrically connected to the chip 21 and the substrate 10 by gold wires 24 and 25 respectively. The second package 30 is disposed on the surface 51 of the spacer 50 . The second package 30 includes a substrate 31 and a chip 32 . The chip 32 is disposed on the substrate 31 and is electrically connected to the substrate 31 by gold wires 33 . The second package 30 is electrically connected to the substrate 10 by gold wires 35 . The sealing glue 34 covers the substrate 31 , the chips 32 and the gold wires 33 . The encapsulant 40 covers the surface 12 of the substrate 10 , the first package 20 and the second package 30 , and the bottom of the substrate 10 has a plurality of solder balls 11 .

但目前的芯片堆叠技术,对于在基板上已有金线连结(wire bond)的半成品芯片并未能提供适当的保护,因此堆叠的芯片容易倾斜而将连结的线型压坏,造成封装的失败,降低生产合格率,使得生产成本提高。如图1中由于间隔物50仅以表面51与第二封装件30接触,由于接触面积不足,容易使得第二封装件30因为失去平衡或轻微的震动或碰撞而倾斜,而压到金线22、金线24及金线25,造成封装失败。再者,由于间隔物50以及金线22、金线24及金线25阻挡,容易造成封胶40在灌模时不能完全包覆各元件而产生孔洞,尤其是芯片23及间隔物50之间,极易有气体孔洞产生。此孔洞将可能于后续工艺之温度变化中,产生爆米花效应(popcorneffect)而导致封胶破裂,而降低产品合格率。However, the current chip stacking technology does not provide proper protection for semi-finished chips with gold wire bonds on the substrate. Therefore, the stacked chips are easy to tilt and the connected wires will be crushed, resulting in package failure. , Reduce production pass rate, make production cost increase. As shown in Figure 1, since the spacer 50 only contacts the second package 30 with the surface 51, due to insufficient contact area, it is easy to make the second package 30 tilt due to loss of balance or slight vibration or impact, and press the gold wire 22 , the gold wire 24 and the gold wire 25, resulting in packaging failure. Furthermore, due to the obstruction of the spacer 50 and the gold wire 22, the gold wire 24 and the gold wire 25, it is easy to cause the sealant 40 to not completely cover each component during the mold filling process, resulting in holes, especially between the chip 23 and the spacer 50. , It is very easy to have gas holes. This hole may cause a popcorn effect in the temperature change of the subsequent process and cause the sealant to break, thereby reducing the product yield.

发明内容 Contents of the invention

鉴于上述情况,本发明的目的就是提供一种具有堆叠平台之封装结构,利用液态封胶形成堆叠平台,提供芯片置放,可保护需维持的线型位置及粘合部位。In view of the above, the object of the present invention is to provide a packaging structure with a stacking platform, which uses a liquid sealant to form a stacking platform, provides chip placement, and can protect the linear position and bonding parts that need to be maintained.

根据本发明的目的,提出一种封装结构,包括第一基板、第一封装件、第二封装件及封胶,第一基板具有第一表面。第一封装件包括第一芯片及液态封胶,第一芯片设置于第一基板上,并通过第一金线与第一基板电连接。液态封胶,包括由第一胶体在该第一芯片之第二表面上形成的围坝结构,其在该第一芯片之第二表面围出容置空间,以及在该围坝结构所围成的容置空间内填入的第二胶体,该第二胶体的粘滞性小于该第一胶体,流动性大于该第一胶体,该液态封胶覆盖第一芯片之第二表面,并覆盖部分之第一金线,液态封胶之表面形成平台。第二封装件设置于平台之上,封胶包覆至少部分之第一基板之第一表面、第一封装件及第二封装件。According to the object of the present invention, a packaging structure is proposed, including a first substrate, a first package, a second package and a sealant. The first substrate has a first surface. The first package includes a first chip and a liquid sealant. The first chip is arranged on the first substrate and is electrically connected to the first substrate through the first gold wire. The liquid sealant includes a dam structure formed by the first glue on the second surface of the first chip, which encloses an accommodating space on the second surface of the first chip, and the dam structure surrounded by the dam structure The second colloid filled in the accommodating space, the viscosity of the second colloid is less than the first colloid, the fluidity is greater than the first colloid, the liquid sealant covers the second surface of the first chip, and covers part of the The first gold wire, the surface of the liquid sealant forms a platform. The second package is disposed on the platform, and the sealing glue covers at least part of the first surface of the first substrate, the first package and the second package.

根据本发明的再一目的,提出一种封装方法。首先,提供第一基板,具有第一表面。接着,设置第一芯片于第一基板上。然后,以第一金线电连接第一芯片与第一基板。接着,以第一胶体在该第一芯片之第二表面上形成围坝结构,其在该第一芯片之第二表面围出容置空间;以第二胶体填入该围坝结构所围成的容置空间内,该第二胶体的粘滞性小于上述第一胶体,流动性大于上述第一胶体,该第二胶体与该围坝结构形成液态封胶,该液态封胶覆盖第一芯片之第二表面及部分第一金线,液态封胶之表面形成平台。然后,设置第二封装件于平台上方。接着,以封胶包覆第一封装件、第二封装件及至少部分之基板之第一表面。According to still another object of the present invention, a packaging method is proposed. Firstly, a first substrate is provided, having a first surface. Next, the first chip is set on the first substrate. Then, the first chip and the first substrate are electrically connected with the first gold wire. Then, the first colloid is used to form a dam structure on the second surface of the first chip, which encloses an accommodating space on the second surface of the first chip; the second colloid is filled into the dam structure surrounded In the accommodating space, the viscosity of the second colloid is lower than that of the first colloid, and its fluidity is greater than that of the first colloid. The second colloid forms a liquid sealant with the dam structure, and the liquid sealant covers the first chip. The second surface and part of the first gold wire form a platform on the surface of the liquid sealant. Then, a second package is disposed on the platform. Then, encapsulating the first package, the second package and at least part of the first surface of the substrate with sealing glue.

为让本发明之上述目的、特征、和优点能更明显易懂,下文特举两个实施例,并配合附图,作详细说明如下:In order to make the above-mentioned purposes, features, and advantages of the present invention more obvious and understandable, two embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows:

附图说明 Description of drawings

图1为传统复封装芯片之结构剖面图;Fig. 1 is the structural sectional view of traditional re-packaging chip;

图2为本发明之第一实施例的一种封装结构之侧视图;Fig. 2 is a side view of a package structure of the first embodiment of the present invention;

图3A~3G为本发明之第一实施例的封装结构之封装流程图;及3A-3G are the packaging flowchart of the packaging structure of the first embodiment of the present invention; and

图4为本发明之第二实施例的封装结构之侧视图。FIG. 4 is a side view of the package structure of the second embodiment of the present invention.

主要元件标记说明Description of main component marking

100、200、300:封装结构100, 200, 300: package structure

10、31、210、231、310、331:基板10, 31, 210, 231, 310, 331: substrate

11、211、311:焊球11, 211, 311: solder balls

12、51、212、226、312、326:表面12, 51, 212, 226, 312, 326: surface

20、220、320:第一封装件20, 220, 320: the first package

21、23、33、221、223、232、321、323、332:芯片21, 23, 33, 221, 223, 232, 321, 323, 332: chips

22、24、25、33、35、222、224、225、233、235、322、324、325、333、335:金线22, 24, 25, 33, 35, 222, 224, 225, 233, 235, 322, 324, 325, 333, 335: gold wire

30、230、330:第二封装件30, 230, 330: second package

34、40、234、240、334、340:封胶34, 40, 234, 240, 334, 340: sealant

50:间隔物50: spacer

250、350:液态封胶250, 350: Liquid sealant

251、351:平台251, 351: Platform

252、352:围坝结构252, 352: Dam structure

253、353:胶体253, 353: colloid

260、360:银胶260, 360: silver glue

具体实施方式 Detailed ways

实施例一Embodiment one

请参照图2,其为本发明之第一实施例的一种封装结构之侧视图。封装结构200包括基板210、第一封装件220、第二封装件230及封胶240。第一封装件220包括芯片221、芯片223及液态封胶250,芯片221设置于基板210上,并通过金线222与基板210电连接。芯片223设置于芯片221上方,并分别以金线224及金线225与芯片221及基板210电连接。Please refer to FIG. 2 , which is a side view of a package structure according to the first embodiment of the present invention. The package structure 200 includes a substrate 210 , a first package 220 , a second package 230 and a sealant 240 . The first package 220 includes a chip 221 , a chip 223 and a liquid sealant 250 . The chip 221 is disposed on the substrate 210 and is electrically connected to the substrate 210 through gold wires 222 . The chip 223 is disposed above the chip 221 and is electrically connected to the chip 221 and the substrate 210 by gold wires 224 and gold wires 225 respectively.

第二封装件230设置于液态封胶250之表面所形成之平台251上。第二封装件230包括基板231及芯片232,芯片232设置于基板231上并以金线233电连接基板231,第二封装件230并以金线235与基板210电连接。封胶234覆盖基板231、芯片232及金线233。封胶240包覆基板210之表面212、第一封装件220及第二封装件230,基板210底部具有多个焊球(solder ball)211。The second package 230 is disposed on the platform 251 formed on the surface of the liquid encapsulant 250 . The second package 230 includes a substrate 231 and a chip 232 , the chip 232 is disposed on the substrate 231 and is electrically connected to the substrate 231 by gold wires 233 , and the second package 230 is electrically connected to the substrate 210 by gold wires 235 . The sealant 234 covers the substrate 231 , the chip 232 and the gold wire 233 . The encapsulant 240 covers the surface 212 of the substrate 210 , the first package 220 and the second package 230 , and a plurality of solder balls 211 are formed on the bottom of the substrate 210 .

请参照图3A~3G,其为本发明之第一实施例的封装结构之封装流程图。首先,请参照图3A,提供基板210,基板210具有表面212,之后,设置芯片221于表面212上。接着,请参照图3B,在芯片221之表面226上设置芯片223。然后,请参照图3C,以金线222电连接芯片221与基板210,以金线224电连接芯片223与芯片221,并以金线225电连接芯片223与基板210。接着,请参照图3D,以粘滞性较大,不会任意流动之胶体形成围坝结构252于芯片221之表面226上。较佳地围坝结构252形成于表面226之周围,以于表面226之中心部分围出一容置空间。Please refer to FIGS. 3A-3G , which are the packaging flowcharts of the packaging structure of the first embodiment of the present invention. First, please refer to FIG. 3A , a substrate 210 is provided, and the substrate 210 has a surface 212 , and then, a chip 221 is disposed on the surface 212 . Next, referring to FIG. 3B , a chip 223 is disposed on the surface 226 of the chip 221 . Then, referring to FIG. 3C , the chip 221 is electrically connected to the substrate 210 with gold wires 222 , the chip 223 is electrically connected to the chip 221 with gold wires 224 , and the chip 223 is electrically connected to the substrate 210 with gold wires 225 . Next, referring to FIG. 3D , a dam structure 252 is formed on the surface 226 of the chip 221 with a colloid with high viscosity and no random flow. Preferably, the dam structure 252 is formed around the surface 226 to enclose an accommodating space at the central part of the surface 226 .

然后,请参照图3E,以粘滞性较小、流动性较大之胶体253,其类似银胶,填入围坝结构252所围成之容置空间内,胶体253与围坝结构252形成液态封胶250。液态封胶250覆盖芯片221之表面226、部分金线222、芯片223、金线224以及部分金线225。之后,将封装结构送进烤箱内烘烤。于液态封胶250固化后,再将液态封胶250之表面磨平,以形成可供置放之平台251,第一封装件220于是形成。Then, please refer to FIG. 3E , fill the containing space surrounded by the dam structure 252 with a less viscous, more fluid colloid 253, which is similar to silver colloid, and the colloid 253 and the dam structure 252 form a liquid state Sealant 250. The liquid encapsulant 250 covers the surface 226 of the chip 221 , a portion of the gold wire 222 , the chip 223 , the gold wire 224 and a portion of the gold wire 225 . Afterwards, the encapsulation structure is sent into an oven for baking. After the liquid sealant 250 is cured, the surface of the liquid sealant 250 is smoothed to form a platform 251 for placement, and the first package 220 is thus formed.

接着,请参照图3F,以银胶260将第二封装件230粘接于平台251上。第二封装件230包括基板231、芯片232及封胶234。芯片232设置于基板231上并以金线233与基板231电连接。封胶234覆盖芯片232、金线233以及基板231。第二封装件230还以金线235与基板210电连接。之后,请参照图3G,以封胶240覆盖基板210之至少部分之表面212、第一封装件220以及第二封装件230,本实施例以封胶240覆盖基板210之全部之表面212为例说明之。然后,于基板210底部形成多个焊球211,以完成封装结构200之封装步骤。Next, referring to FIG. 3F , the second package 230 is bonded on the platform 251 with silver glue 260 . The second package 230 includes a substrate 231 , a chip 232 and a sealant 234 . The chip 232 is disposed on the substrate 231 and electrically connected to the substrate 231 by gold wires 233 . The encapsulant 234 covers the chip 232 , the gold wire 233 and the substrate 231 . The second package 230 is also electrically connected to the substrate 210 by gold wires 235 . After that, please refer to FIG. 3G , the sealant 240 covers at least part of the surface 212 of the substrate 210, the first package 220 and the second package 230. In this embodiment, the sealant 240 covers the entire surface 212 of the substrate 210 as an example. Explain it. Then, a plurality of solder balls 211 are formed on the bottom of the substrate 210 to complete the packaging step of the packaging structure 200 .

在本实施例之封装结构200中,以液态封胶250包覆芯片221及223,及其所连接之金线222、224及225。如此,当第二封装件230叠置于芯片221及223之上时,液态封胶250包覆了芯片221及223。故液态封胶250比图1所示之间隔物50,更能对芯片221和223,及与其相连之金线222、224及225,提供更完善地保护,以维持金线222、224及225之线型,避免金线222、224及225短路。In the packaging structure 200 of this embodiment, the chips 221 and 223 and the gold wires 222 , 224 and 225 connected thereto are covered with a liquid encapsulant 250 . In this way, when the second package 230 is stacked on the chips 221 and 223 , the liquid encapsulant 250 covers the chips 221 and 223 . Therefore, the liquid sealant 250 can provide better protection to the chips 221 and 223 and the gold wires 222, 224 and 225 connected thereto than the spacer 50 shown in FIG. The wire type can avoid the short circuit of the gold wires 222, 224 and 225.

此外,由于液态封胶250之表面形成面积与芯片221之面积相当之平台,以供第二封装件230置放。与图1中形成于芯片21上方,芯片23之侧的间隔物50相比较,液态封胶250所提供之平台251的表面大于间隔物50之面积,且平台251可接触到第二封装件230之底面的大部分区域。故本实施例之第二封装件230得以平稳地置放于平台251上,可避免第二封装件230产生倾斜之现象。In addition, since the surface of the liquid encapsulant 250 forms a platform with an area equivalent to that of the chip 221 , it is used for placing the second package 230 . Compared with the spacer 50 formed above the chip 21 and on the side of the chip 23 in FIG. 1 , the surface of the platform 251 provided by the liquid encapsulant 250 is larger than the area of the spacer 50 , and the platform 251 can contact the second package 230 most of the bottom area. Therefore, the second package 230 of this embodiment can be placed on the platform 251 stably, which can prevent the second package 230 from being tilted.

再者,由于本实施例使用粘滞性较小、流动性较大之液态封胶250来保护芯片221及223,液态封胶250产生气体孔洞的机率远比图1之使用灌模工艺来形成封胶40的机率小,故本实施例之封装结构还具有提高合格率之优点。Furthermore, since this embodiment uses a liquid sealant 250 with low viscosity and high fluidity to protect the chips 221 and 223, the probability of gas holes generated by the liquid sealant 250 is much higher than that formed by using the pouring process in FIG. 1 The probability of sealing glue 40 is small, so the packaging structure of this embodiment also has the advantage of improving the yield.

实施例二Embodiment two

请参照图4,其为本发明之第二实施例的封装结构之侧视图。本实施例之封装结构300与第一实施例之封装结构200的主要不同之处,在于液态封胶与基板接触的部分。本实施例之液态封胶350除完全覆盖芯片321之表面326外,还覆盖部分基板310之表面312。液态封胶350的形成方式例如为,先形成围坝结构352于基板310之表面312,围坝结构352位于距离芯片321一段距离之外围。之后,将胶体353填入围坝352所围成之容置空间内,形成液态封胶350覆盖部分基板310之表面312及芯片321之表面326。其余元件之连接关系与形成步骤与第一实施例相同,不再赘述。Please refer to FIG. 4 , which is a side view of the package structure of the second embodiment of the present invention. The main difference between the package structure 300 of the present embodiment and the package structure 200 of the first embodiment lies in the portion where the liquid sealant contacts the substrate. The liquid encapsulant 350 of this embodiment not only completely covers the surface 326 of the chip 321 , but also partially covers the surface 312 of the substrate 310 . The method of forming the liquid encapsulant 350 is, for example, to firstly form a dam structure 352 on the surface 312 of the substrate 310 , and the dam structure 352 is located at the periphery of a certain distance from the chip 321 . After that, the glue 353 is filled into the accommodation space surrounded by the dam 352 to form a liquid sealant 350 covering part of the surface 312 of the substrate 310 and the surface 326 of the chip 321 . The connection relationship and formation steps of the remaining components are the same as those in the first embodiment, and will not be repeated here.

由于第二实施例所形成之封胶350的平台351之面积,大于第一实施例之封胶250之平台251之面积。故本实施例可提供更大的平台351,以使第二封装件330得以更平稳地置放于平台351上。Because the area of the platform 351 of the sealant 350 formed in the second embodiment is larger than the area of the platform 251 of the sealant 250 in the first embodiment. Therefore, this embodiment can provide a larger platform 351 so that the second package 330 can be placed on the platform 351 more stably.

本发明上述实施例所披露之具有堆叠平台之封装结构,以封胶包覆芯片及其连接金线,如此可以提供有效地保护芯片及其连接金线的保护,并于液态封胶表面形成平台,供另一芯片置放。故本发明之封装结构可以简单之工艺亦提供芯片一较佳之堆叠平台,避免堆叠芯片倾斜压坏连结之金线造成损坏,可以提高产品的合格率,降低生产成本,为本发明之优点及特色。The packaging structure with a stacking platform disclosed in the above embodiments of the present invention covers the chip and its connecting gold wires with encapsulant, which can effectively protect the chip and its connecting gold wires, and form a platform on the surface of the liquid encapsulant , for another chip placement. Therefore, the packaging structure of the present invention can provide a better stacking platform for chips with a simple process, avoiding the damage caused by the stacked chips being tilted and crushing the connecting gold wires, which can improve the pass rate of products and reduce production costs, which are the advantages and characteristics of the present invention. .

综上所述,虽然本发明已以较佳实施例披露如上,然其并非用以限定本发明,任何所属技术领域的技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与改进,因此本发明的保护范围当视权利要求所界定者为准。In summary, although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications without departing from the spirit and scope of the present invention. Changes and improvements, so the protection scope of the present invention should be defined by the claims.

Claims (14)

1.一种封装结构,其特征是包括:1. A package structure, characterized in that it comprises: 第一基板,具有第一表面;a first substrate having a first surface; 第一封装件,包括:A first package, including: 第一芯片,设置于该第一基板上,并通过第一金线与该第一基板电连接;及a first chip, disposed on the first substrate, and electrically connected to the first substrate through a first gold wire; and 液态封胶,包括由第一胶体在该第一芯片之第二表面上形成的围坝结构,其在该第一芯片之第二表面围出容置空间,以及在该围坝结构所围成的容置空间内填入的第二胶体,该第二胶体的粘滞性小于该第一胶体,流动性大于该第一胶体,该液态封胶覆盖该第一芯片之第二表面,并覆盖部分之该第一金线,该液态封胶之表面形成平台;The liquid sealant includes a dam structure formed by the first glue on the second surface of the first chip, which encloses an accommodating space on the second surface of the first chip, and the dam structure surrounded by the dam structure The second colloid filled in the accommodating space of the first colloid has less viscosity than the first colloid and greater fluidity than the first colloid, and the liquid encapsulant covers the second surface of the first chip and covers A part of the first gold wire forms a platform on the surface of the liquid encapsulant; 第二封装件,设置于该平台之上;以及a second package disposed on the platform; and 封胶,包覆至少部分之该第一基板之该第一表面、该第一封装件及该第二封装件。The sealant covers at least part of the first surface of the first substrate, the first package and the second package. 2.根据权利要求1所述之封装结构,其特征是该第一封装件之该液态封胶完全覆盖该第一芯片,并覆盖部分该第一基板之该第一表面。2 . The package structure according to claim 1 , wherein the liquid encapsulant of the first package completely covers the first chip and partially covers the first surface of the first substrate. 3.根据权利要求1所述之封装结构,其特征是该第二封装件包括第二芯片、第二基板及第二金线,该第二芯片通过该第二金线与该第二基板电连接。3. The package structure according to claim 1, wherein the second package includes a second chip, a second substrate and a second gold wire, and the second chip is electrically connected to the second substrate through the second gold wire. connect. 4.根据权利要求1所述之封装结构,其特征是还包括第三芯片,设置于该第一芯片之该第二表面上,该液态封胶还包覆该第三芯片。4. The packaging structure according to claim 1, further comprising a third chip disposed on the second surface of the first chip, and the liquid encapsulant also covers the third chip. 5.根据权利要求4所述之封装结构,其特征是该第三芯片通过至少一第三金线与该第一芯片电连接,该液态封胶包覆该第三金线。5. The packaging structure according to claim 4, wherein the third chip is electrically connected to the first chip through at least one third gold wire, and the liquid encapsulant covers the third gold wire. 6.根据权利要求5所述之封装结构,其特征是该第三芯片通过第四金线与该第一基板电连接,该液态封胶包覆部分之该第四金线。6 . The package structure according to claim 5 , wherein the third chip is electrically connected to the first substrate through a fourth gold wire, and the liquid encapsulant covers part of the fourth gold wire. 7.根据权利要求1所述之封装结构,其特征是该第二封装件通过银胶设置于该平台上。7. The package structure according to claim 1, wherein the second package is disposed on the platform through silver glue. 8.根据权利要求1所述之封装结构,其特征是该第一基板底部具有多个焊球。8. The package structure according to claim 1, wherein a plurality of solder balls are formed on the bottom of the first substrate. 9.一种封装方法,其特征是包括:9. A packaging method, characterized in that it comprises: 提供第一基板,具有第一表面;providing a first substrate having a first surface; 设置第一封装件,设置第一芯片于该第一基板上;disposing a first package, disposing a first chip on the first substrate; 以第一金线电连接该第一芯片与该第一基板;electrically connecting the first chip and the first substrate with a first gold wire; 以第一胶体在该第一芯片之第二表面上形成围坝结构,其在该第一芯片之第二表面围出容置空间;forming a dam structure on the second surface of the first chip with the first colloid, which encloses an accommodating space on the second surface of the first chip; 以第二胶体填入该围坝结构所围成的容置空间内,该第二胶体的粘滞性小于上述第一胶体,流动性大于上述第一胶体,该第二胶体与该围坝结构形成液态封胶,该液态封胶覆盖该第一芯片之第二表面及部分该第一金线,该液态封胶之表面形成平台,以形成第一封装件;filling the containing space surrounded by the dam structure with the second colloid, the viscosity of the second colloid is lower than that of the first colloid, and its fluidity is greater than that of the first colloid, and the second colloid is compatible with the dam structure forming a liquid sealant, the liquid sealant covers the second surface of the first chip and part of the first gold wire, the surface of the liquid sealant forms a platform to form a first package; 设置第二封装件于该平台上方;以及disposing a second package over the platform; and 以封胶包覆该第一封装件、该第二封装件及至少部分之该基板之该第一表面。The first package, the second package and at least part of the first surface of the substrate are covered with encapsulant. 10.根据权利要求9所述之封装方法,其特征是于该液态封胶覆盖该第一芯片之该第二表面及部分该第一金线,该液态封胶之表面形成该平台之步骤中,该液态封胶并覆盖部分该第一基板之该第一表面。10. The packaging method according to claim 9, wherein the liquid sealant covers the second surface of the first chip and part of the first gold wire, and the surface of the liquid sealant forms the platform , the liquid sealant covers part of the first surface of the first substrate. 11.根据权利要求9所述之封装方法,其特征是该第二封装件还包括第二芯片、第二基板及第二金线,在设置该第二封装件于该平台上方之步骤中,还包括:以该第二金线电连接该第二芯片与该第二基板。11. The packaging method according to claim 9, wherein the second package further comprises a second chip, a second substrate and a second gold wire, and in the step of setting the second package above the platform, It also includes: electrically connecting the second chip and the second substrate with the second gold wire. 12.根据权利要求9所述之封装方法,其特征是于设置该第一芯片于该第一基板上之后,还包括:12. The packaging method according to claim 9, further comprising: after disposing the first chip on the first substrate: 设置第三芯片于该第一芯片之该第二表面上;disposing a third chip on the second surface of the first chip; 其中,在以该液态封胶覆盖该第一芯片之该第二表面及部分该第一金线,该液态封胶之表面形成该平台之步骤中,还以该液态封胶包覆该第三芯片。Wherein, in the step of covering the second surface of the first chip and part of the first gold wire with the liquid encapsulant, and the surface of the liquid encapsulant forms the platform, the third chip is also covered with the liquid encapsulant. chip. 13.根据权利要求12所述之封装方法,其特征是于设置该第三芯片于该第一芯片之该第二表面上之后,还包括:13. The packaging method according to claim 12, further comprising: after arranging the third chip on the second surface of the first chip: 以第三金线电连接该第三芯片与该第一芯片,并以第四金线电连接该第三芯片与该第一基板;electrically connecting the third chip and the first chip with a third gold wire, and electrically connecting the third chip and the first substrate with a fourth gold wire; 其中,该液态封胶包覆该第三金线及部分之该第四金线。Wherein, the liquid encapsulant covers the third gold wire and part of the fourth gold wire. 14.根据权利要求9所述之封装方法,其特征是于设置该第二封装件于该平台上方之步骤中,还包括:14. The packaging method according to claim 9, wherein the step of disposing the second package on the platform further comprises: 以银胶粘接该第二封装件于该平台上。The second package is bonded on the platform with silver glue.
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