CN100538885C - Be used for changing circuit and method at the page length of semiconductor memory - Google Patents
Be used for changing circuit and method at the page length of semiconductor memory Download PDFInfo
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- CN100538885C CN100538885C CNB2003101163188A CN200310116318A CN100538885C CN 100538885 C CN100538885 C CN 100538885C CN B2003101163188 A CNB2003101163188 A CN B2003101163188A CN 200310116318 A CN200310116318 A CN 200310116318A CN 100538885 C CN100538885 C CN 100538885C
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
- G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
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Abstract
The present invention relates to a kind of semiconductor memory, it has the structure that makes the user can change the page length of semiconductor memory.The invention still further relates to the circuit and the method for the page length that is used to change semiconductor memory, it makes it possible to optionally to activate one or more corresponding word lines (having identical row address) of the memory cell array block of memory cell array, thereby changes page length according to the operator scheme of appointment.
Description
The cross reference of related application
The application requires the right of priority of the korean patent application submitted in Korea S Department of Intellectual Property on November 19th, 2002 2002-72093 number.
Technical field
The present invention relates to a kind of semiconductor memory, it has the structure that makes the user can change the page length of semiconductor devices.In addition, the present invention relates to be used to change the circuit and the method for the page length of semiconductor devices, wherein, addressing scheme and control circuit enable optionally to activate one or more corresponding word lines (having identical row address) of the cells of memory arrays piece of memory cell array, so that therefore change page length according to the operator scheme of appointment.
Background technology
Current, semiconductor memory provides widely to different operator schemes and uses.For example, synchronous semiconductor memory device (such as SDRAM (Synchronous Dynamic Random Access Memory)) can support to use the variable column address strobe stand-by period (CL) and burst length (BL) pattern of mode register set (MRS).These semiconductor memories are used for different devices and use, such as the primary memory of electronic equipment, network system, communication system, control system, multimedia application and PC (personal computer).
Figure 1A-1C illustrates the hierarchical memory structure according to the semiconductor memory of prior art.Shown in Figure 1A, semiconductor memory (100) comprises a plurality of memory sticks (100A, 100B, 100C, 100D).Each memory stick is represented for example logical block of the storer on PC, and each memory stick can comprise one or more memory modules (for example DIMM (double in-line memory module), SIMM (single-row inline memory modules)).Each memory stick (100A, 100B, 100C, 100D) also logically is divided into a plurality of memory cell array blocks.For example, as described in the exemplary embodiments of Figure 1B, memory stick (100A) comprises four memory cell array blocks (100a, 100b, 100c, 100d).
In addition, each memory cell array block (100a, 100b, 100c, 100d) further logically is divided into a plurality of sub-memory cell array blocks, wherein, and the control circuit control that each sub-memory cell array block is associated.For example, described in the exemplary embodiments in Fig. 1 C, memory cell array block (100a) comprises four sub-memory cell array blocks (110,120,130,140).Memory cell array block (100a) also comprises a plurality of word line drivers (111,121,131,141), wherein, each word line driver and sub-memory cell array block (110,120,130,140) one of and a plurality of sub-demoder (112,122,132,142) and a row decoder (150) be associated.
Memory construction described in Figure 1A-C generally is implemented in the part activating semiconductor storage component part such as fast cycle dynamic RAM (FCRAM), wherein, for example can utilizing, row block address (CBA) activates sub-memory cell array block (110,120,130,140) one of so that carry out data access or refresh operation.
Pass through example, in order to carry out storage access operations, initially select one of memory stick (100A, 100B, 100C, 100D) in response to predetermined bar address, be chosen in the memory cell array block (100a, 100b, 100c, 100d) in the selected memory stick then in response to predetermined address (for example row address).Then, select (in selected memory cell array block) sub-memory cell array block in response to for example row block address (CBA).For example, in the exemplary embodiments of Fig. 1 C,, therefore use two row block address (CBA) to come one of chooser storage block because memory cell array block (100a) comprises four sub-storage blocks (110,120,130,140).
More specifically, write or read operation (memory access) during, row address RAi (i=2,3 ..., n) be imported into row decoder (150) and decoded.Then, according to decoded results, row decoder (150) will activate one of a plurality of normal character line enable signals (NWE) corresponding with the row address RAi of input.In response to another row address RAi (i=0,1) and CBA, sub-demoder (112,122,132,142) the word line power supply signal that generation is had predetermined boost level one of, and to word line driver (111, an output word line power supply signal of correspondence 121,131,141).In response to described word line power supply signal and word line enable signal NEW, described word line activates word line (WL_0, WL_1, WL_2, WL_3) one of the correspondence in by predetermined on-off circuit (not shown).In case activated word line for selected sub-memory cell array block, then column address is transfused to decoded so that reading of data with to selected sub-storage block and writes data.
In DRAM with the storage organization as shown in Figure 1A-1C, because among can only activating sub-memory cell array block (110,120,130,140) in any given time one, so the page length of semiconductor devices is fixed.As known in this area, one " page " refers to the quantity of the bit that can visit from a row address, and the quantity of column address is determined the size of " page ".For example, in the memory cell array block (100a) of Fig. 1 C, the sum of supposing outside Input Address is n, and being used to select the sum of column address of a column selection row (CSL) of each sub-memory cell array block is n-2.This is because two column addresss are used to select one of four sub-memory cell array blocks (100a, 100b, 100c, 100d).Therefore, the page length corresponding to the word line that is activated of a selected sub-memory cell array block is fixed on 2
N-2Therefore, provide fixedly page length 2
N-2The conventional semiconductors storage component part with the structure shown in Fig. 1 C with have a for example page length 2
nOr 2
N-1Semiconductor memory (for example SDRAM) incompatible.
Therefore, it will be very useful having the semiconductor memory that makes it possible to adjust for given application the structure of page length.
Summary of the invention
The semiconductor memory of the structure of the page length that the present invention relates to make the user can change semiconductor devices.In addition, the preferred embodiments of the present invention comprise the circuit and the method for the page length that is used to change semiconductor devices, wherein, addressing scheme and control circuit make it possible to optionally to activate one or more corresponding word lines (having identical row address) of the cells of memory arrays piece of memory cell array, so that therefore change page length according to the operator scheme of appointment.
Useful is, can change page length by making, the invention enables having between the semiconductor devices of different page lengths to have compatibility.
Semiconductor devices according to one embodiment of the present of invention comprises: memory cell array, and it logically is divided into a plurality of storage blocks, wherein, can come each storage block of addressing by the block address of correspondence; A plurality of Word line control circuits, wherein, one of storage block of each Word line control circuit and the word line that is used to activate the storage block that is associated is associated; Control circuit, being used for optionally, the control word line control circuit has one or more corresponding word lines of identical row address so that change the page length of semiconductor memory with activation, wherein control circuit receives the block address (for example row block address) and first control signal as input, produces second control signal then and optionally activates one or more Word line control circuits.
In one embodiment, utilize mode register set dynamically to produce first control signal in response to predetermined order and external address.In other embodiments, by being programmed, the control signal generator that uses wire bond, metal solder or fusing cutting solidifies first control signal.
In another embodiment of the present invention, accumulator system comprises: first memory equipment, and it comprises memory cell array, described memory cell array logically is divided into a plurality of storage blocks, wherein, can come each storage block of addressing by the block address of correspondence; A plurality of Word line control circuits, wherein, one of storage block of each Word line control circuit and the word line that is used to activate the storage block that is associated is associated; Control circuit, being used for optionally, the control word line control circuit has one or more corresponding word lines of identical row address so that change the page length of semiconductor memory with activation.
In another embodiment of the present invention, a kind of method that is used to change the page length of semiconductor memory is provided, described semiconductor memory comprises: memory cell array, it logically is divided into a plurality of storage blocks, wherein, can come each storage block of addressing by the block address of correspondence.Described method comprises first control signal that produces one of a plurality of page length operator schemes of appointment, and produces second control signal according to first control signal and block address.In response to second control signal, the one or more word lines in storage block with identical row address are optionally activated so that the page length corresponding to the semiconductor memory of specifying the page length operator scheme to be provided.
By preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, these and other embodiment of the present invention, aspect, characteristic and advantage will be illustrated and become clear.
Description of drawings
Figure 1A, 1B and 1C are the synoptic diagram of diagram according to the layering storage organization of the semiconductor memory of prior art.
Fig. 2 is that described memory cell array block structure enables to change the page length of semiconductor memory according to the synoptic diagram of the memory cell array block structure of one embodiment of the present of invention.
Fig. 3 is the circuit diagram according to the memory cell array block of one embodiment of the present of invention, and described memory cell array block enables to use the control signal that is produced by MRS (mode register set) to change the page length of semiconductor memory.
Fig. 4 A, 4B and 4C are the tabular drawings of the various operator schemes of the memory cell array block among diagram Fig. 3, wherein obtain different page lengths and are used for a semiconductor memory.
Fig. 5 is the circuit diagram of diagram according to the sub-demoder of one embodiment of the present of invention, and described sub-demoder can be implemented in the circuit of Fig. 3.
Fig. 6 is the circuit diagram according to the word line driver of one embodiment of the present of invention, and described word line driver can be implemented in the circuit of Fig. 3.
Fig. 7 illustrates the control signal generator according to one embodiment of the present of invention.
Fig. 8 illustrates the control signal generator according to an alternative embodiment of the invention.
Fig. 9 is diagram according to the high level flow chart of method of page length that is used to change semiconductor memory of one embodiment of the present of invention.
Figure 10 is the schematic block diagram that diagram wherein can realize accumulator system of the present invention.
Embodiment
The present invention relates to a kind of semiconductor memory, it has the structure that makes the user can change the page length of semiconductor devices.Particularly, be based on such addressing scheme according to the circuit of the preferred embodiments of the present invention with method and make its one or more corresponding word lines that can optionally activate the cells of memory arrays piece of memory cell array (having identical row address), so that change the page length of semiconductor memory according to the operator scheme of appointment with control circuit.
Fig. 2 is that described memory cell array block structure enables to change the page length of semiconductor memory according to the high level schematic diagram of the memory cell array block structure of one embodiment of the present of invention.The exemplary embodiments of Fig. 2 can be counted as the extension of the storage organization shown in Fig. 1 C, and wherein, control and addressing mechanism be feasible can to change page length (opposite with Fig. 1 C-structure with fixing page length).Referring to Fig. 2, semiconductor memory comprises memory cell array block (200) (or " storage block "), it has and logically is divided into a plurality of sub-memory cell array blocks (110,120,130,140) storage array of (or " sub-storage block "), wherein, can each sub-storage block of addressing by the block address (for example CBA (row block address)) of correspondence.In exemplary embodiments, 4 sub-storage blocks ( piece 0,1,2,3) are illustrated and are used for illustration purpose, can comprise more or less sub-storage block though can understand storage block (200).
Storage block (200) also comprises: a plurality of word line drivers (111,121,131,141), and wherein, one in each word line driver (111,121,131,141) and a plurality of sub-memory cell array blocks (110,120,130,140) is associated; A plurality of sub-demoders (212,222,232,242), wherein, each sub-demoder (212,222,232,242) is associated with one of word line driver (111,121,131,141).Sub-demoder/the word line driver of each correspondence is used to activate the word line of the sub-storage block that is associated to comprising Word line control circuit.
Generally, control circuit (250) optionally the control word line control circuit optionally to activate the sub-memory cell array block (110 have by the identical row address of row decoder (150) decoding, 120,130,140) one or more corresponding word lines (WL_0, WL_1, WL_2, WL_3), so that therefore change the page length of semiconductor memory.Particularly, row decoder (150) receive the decode the second line of input address RAi (wherein, i=2,3 ..., n), and activate the normal character line enable signal (NWE) of row address corresponding to input according to decoded result.Control circuit (250) receives row block address (CBA) and control signal as input, and in response, to the corresponding control signal of sub-demoder (212,222,232,242) output.Sub-demoder (212,222,232,242) receives control signal and the first row address RAi (i=0,1) as input from control circuit (250), produces the control signal that is output to word line driver (111,121,131,141) then.
According to from sub-demoder (212,222,232,242) control signal and from the NEW signal of row decoder (150), word line driver (111,121,131,141) will optionally activate sub-memory cell array block (110,120 with identical row address, 130,140) one or more corresponding word lines (WL_0, WL_1, WL_2, WL_3), so that change the page length of conductor memory.For example, in exemplary embodiments shown in Figure 2, the quantity of supposing the column address of each sub-storage block is n-2, then or the word line that (i) can activate one of sub-storage block to obtain 2
N-2Page length; Perhaps (ii) can activate the corresponding word line of two sub-storage blocks to obtain 2
N-1Page length, the corresponding word lines that perhaps (iii) can activate all four sub-storage blocks is to obtain 2
nPage length.
Therefore, in the exemplary embodiments of Fig. 2, one or more word line drivers (111,121,131,141) can according to control signal and be input to control circuit (250) CBA combination and optionally Be Controlled circuit (250) drive.Therefore, can adjust the quantity of word line, therefore change the page length of conductor memory according to expectation with identical row address.
Fig. 3 is the circuit diagram according to the memory cell array block of one embodiment of the present of invention, and described memory cell array block enables to change based on specific operator scheme the page length of semiconductor memory.The circuit diagram of Fig. 3 illustrates a specific embodiment of the general structure of Fig. 2.For example, Fig. 3 illustrates an embodiment of the control circuit (250) of Fig. 2.In addition, in Fig. 3, a MRS (mode register set) is used to produce the control signal that is imported into control circuit, and wherein, the control signal of exporting from MRS can be provided with and control to change page length according to expectation by the user.
More specifically, referring to Fig. 3, the storage block of semiconductor memory (300) comprises a storage array, it logically is divided into a plurality of sub-memory cell array blocks (110,120,130,140), wherein, use block address CBA0, CBA1 can the sub-storage block of addressing.In described exemplary embodiments, 4 sub-storage blocks ( piece 0,1,2,3) are illustrated and are used for illustration purpose, can comprise more or less sub-storage block though can understand storage block (300).
Storage block (300) also comprises: a plurality of word line drivers (111,121,131,141), and wherein, each word line driver (111,121,131,141) is associated with one of a plurality of sub-memory cell array blocks (110,120,130,140); A plurality of sub-demoders (312,322,332,342), wherein, each sub-demoder (312,322,332,342) is associated with one of word line driver (111,121,131,141).Sub-demoder/the word line driver of each correspondence is used for activating according to the control signal from control circuit (360) output the word line of the sub-storage block that is associated to comprising Word line control circuit.
Generally, control circuit (360) optionally control word line control circuit has the sub-memory cell array block (110 of (by row decoder (150) decoding) identical row address optionally to activate, 120,130,140) one or more corresponding word lines (WL_0, WL_1, WL_2, WL_3), so that therefore change the page length of conductor memory.Particularly, row decoder (150) receive the decode the second line of input address RAi (wherein, i=2,3 ..., n), and activate the normal character line enable signal (NWE) of row address corresponding to input according to decoded result.Control circuit (360) is as the control signal PL0B and the PL1B that import reception row block address CBA0 and CBA1 and produced by control signal generator (350), then according to block address and the control signal imported, to sub-demoder (312,322,332,342) output control signal.Sub-demoder (312,322,332,342) receives control signal and the first row address RAi (i=0,1) as input from control circuit (360), produces the control signal that is output to word line driver (111,121,131,141) then.
According to from sub-demoder (312,322,332,342) control signal and from the NEW signal of row decoder (150), word line driver (111,121,131,141) will optionally activate sub-memory cell array block (110,120 with identical row address, 130,140) one or more corresponding word lines (WL_0, WL_1, WL_2, WL_3), so that change the page length of conductor memory.
Control signal generator (350) comprises commands buffer (351), address buffer (352) and mode register set (MRS) 353.Memory Controller (or for example CPU) sends predetermined command signal and address signal to control signal generator (350).Commands buffer (351) receives described predetermined command signal, and address buffer (352) receives external address signal from Memory Controller.MRS (353) receives order and address signal from commands buffer (351) and address buffer (352), and exports control signal PL0B and PL1B according to the order and the address signal of input then.
Control circuit (360) preferably comprises a plurality of phase inverters (361,362,365,366) and a plurality of NAND circuit (363,364,367,368).Phase inverter (361) receives row block address complement code CBA0B as input, and phase inverter (362) receives row block address CBA0 as input.NAND circuit (363) receives output signal and the control signal PL0B and the PL1B of phase inverter (361) as input.NAND circuit (364) receives output signal and the control signal PL0B and the PL1B of phase inverter (362) as input.Phase inverter (365) receives row block address complement code CBA1B as input, and phase inverter (366) receives row block address CBA1 as input.NAND circuit (367) receives the output signal and the control signal PL1B of phase inverter (365) as input.NAND circuit (368) receives the output signal and the control signal PL1B of phase inverter (366) as input.
Storage block (300) also comprises preposition demoder (375), a plurality of column decoder (371,372,373,374) and a plurality of logical circuit (381,382,383,384,391,392,393,394,395,396,397,398), and their function will illustrate below.Preposition demoder (375) receives and the column address of pre decoding except being used for the class block address.For example, in the exemplary embodiments of Fig. 3, the sum of presumptive address is n, because two addresses are used to CBA, n-2 column address is imported into preposition demoder (375).
Logical circuit (392) receives row block address CBA0B and CBA1B as input.Logical circuit (394) receives row block address CBA0 and CBA1B as input.Logical circuit (396) receives row block address CBA0B and CBA1 as input.Logical circuit (398) receives row block address CBA0 and CBA1 as input.Logical circuit 392,394,396 and 398 output are anti-phase by phase inverter 391,393,395 and 397 respectively.
Logical circuit (381) receives the output signal of phase inverter (391) and the output signal of preposition demoder (375) as input, and to the signal of column decoder (371) output that is associated with the first sub-storage block (110).Logical circuit (382) receives the output signal of phase inverter (393) and the output signal of preposition demoder (375) as input, and to the signal of column decoder (372) output that is associated with the second sub-storage block (120).Logical circuit (383) receives the output signal of phase inverter (395) and the output signal of preposition demoder (375) as input, and to the signal of column decoder (373) output that is associated with the 3rd sub-storage block (130).Logical circuit (384) receives the output signal of phase inverter (397) and the output signal of preposition demoder (375) as input, and to the signal of column decoder (374) output that is associated with the 4th sub-storage block (140).
In the exemplary embodiments of Fig. 3, as mentioned above, the control signal of using MRS (353) to produce in control signal generator (350) can be changed to adjust page length according to expectation.The control signal that MRS (353) output is handled by control circuit (360) is to carry out the specified operator scheme of external command and address that is received from for example Memory Controller or CPU by control signal generator (350).
By example, Fig. 4 A-4C is diagram wherein changes the conductor memory of Fig. 3 according to control signal PL0B and PL1B the various operator schemes of page length.On concrete, Fig. 4 A be diagram wherein invalid/forbid that (for example logic level height) control signal PL0B and PL1B are to obtain 2
N-2The form of operator scheme of page length, wherein, activate only sub-storage block according to as shown in the figure row block address CBA0 and the logic level of CBA1.In addition, Fig. 4 B is that diagram wherein only activates/enable (for example logic level is low) control signal PL0B to obtain 2
N-1The form of operator scheme of page length, wherein, perhaps when row block address CBA1 is logic low, activate sub-storage block 0 and 1, perhaps when CBA1 is logic high, activate sub-storage block 2 and 3 (under this pattern, CBA0 has nothing to do).In addition, Fig. 4 C is that diagram wherein only activates/enable (for example logic level is low) control signal PL1B to obtain 2
nThe form of operator scheme of page length, wherein, irrespectively activate all storage blocks (0,1,2 and 3) with the logic level of row block address CBA0 and CBA1.
Referring now to the exemplary embodiments of Fig. 3 and Fig. 4 A, 4B and 4C various operator schemes according to semiconductor memory of the present invention are described in further detail.Referring to Fig. 3, control signal generator (350) receives external command and address, and utilizes MRS (353) to produce predetermined control signal PL0B and PL1B in response to order and address.Control circuit (360) receives row block address CBA0 and CBA1 and control signal PL0B and PL1B, then to sub-demoder (312,322,332,342) output control signal.Sub-demoder (312,322,332,342) is according to optionally activating corresponding word lines driver (111,121,131,141) from the control signal of control circuit (360) and the first row address RAi (wherein, i=0,1).When producing normal word line enable signal NEW from row decoder (150) when, a sub-demoder that is activated is exported word line power supply signal (PXI) so that enable the corresponding word lines (WL_0 of selected sub-storage block to the corresponding word lines driver, WL_1, WL_2, WL_3).In other words, in response to the normal character line enable signal NEW that produces by row decoder (350), word line driver (111,121,131,141) with the sub-demoder (312 of correspondence, 322,332,342) output signal is converted to the word line that will activate, thereby activates the word line of the word memory piece that is associated.Below with reference to Fig. 5 and 6 further describe for example can in the device of Fig. 3, realize, according to the exemplary embodiments of sub-demoder of the present invention and word line driver.
The selective activation of one of a sub-memory cell array block of mode enable (110,120,130,140) of operation of semiconductor memory of typical structure with Fig. 3 is so that obtain the page length of 2n-2.On concrete, in the time of invalid (for example logic " high " state) control signal PL0B and PL1B, activate one of only sub-storage block (110,120,130,140) according to the logic state of row block address CBA0 and CBA1, shown in Fig. 4 A.And, in this operator scheme, activate one of column decoder (371,372,373,374) according to the logic state of row block address CBA0 and CBA1.
By example, suppose that control signal PL0B and PL1B are disabled (for example at logic high state) and row block address CBA0 and CBA1 at the logic " low " state.In this case, the output of each Sheffer stroke gate (363) and (367) will be logic " height ", make to activate sub-demoder (312) (supposing that certainly needed address signal RAi is imported into sub-demoder (312)).Sub-demoder (312) will produce appropriate control signals subsequently so that word line driver (111) activates the word line (WL_0) of sub-storage block (110).And, because row block address CBA0 and CBA1 be at the logic " low " state, therefore logical circuit (392) only, (391) and (381) will work, and activation column decoder (371).Column decoder (371) receives the column address information of preposition demoder (375), and subsequently on sub-storage block (110) 2
N-2Select a column selection line (CSL) in the individual column selection line (CSL).That is, the semiconductor memory corresponding to the sub-storage block (110) that activates has 2
N-2Page length.For example, in page mode operation, word line (OK) is held effectively, and n-2 column address used in regular turn to visit the storage unit of the row that is activated simultaneously.
Another operator scheme of semiconductor memory with typical structure of Fig. 3 enables optionally to activate two sub-storage blocks to obtain 2
N-1Page length.On concrete, if activation control signal PL0B (for example logic " low " state) and invalid control signal PL1B (for example logic " high " state), then the logic state according to row block address CBA1B and CBA1 activates two sub-storage blocks, and irrelevant with the logic state of row block address CBA0 and CBA0B, shown in Fig. 4 B.Particularly, if row block address CBA1 has the logic " low " state, the word line of then sub-storage block (110) and (120) (WL_0 and WL_1) is activated and irrelevant with the logic state of row block address CBA0.And if row block address CBA1 has the logic " high " state, the word line of then sub-storage block (130) and (140) (WL_2 and WL_3) is activated and irrelevant with the logic state of row block address CBA0.And, in this operator scheme, can optionally activate the column decoder that is associated with the sub-storage block that is activated according to the logic state of row block address CBA0.
By example, suppose activation control signal PL0B (for example logic " low " state) and invalid control signal PL1B (for example logic " high " state).In this case, because have NAND circuit (363) and (364) that the control signal PL1B of " height " logic level is imported into control circuit (360), so the output of each NAND circuit will be logic " high " state and irrelevant with the logic state of row block address CBA0B and CBA0.Further supposition row block address CBA1 has the logic " low " state, and the output of NAND circuit (367) will be at the logic " high " state.In this case, because the output of NAND circuit (363), (364) and (367) is logic " height ", therefore sub-demoder (312) and (322) will be activated (supposing that certainly needed address signal RAi is imported into so sub-demoder).Sub-demoder (312) and (322) will produce appropriate control signals subsequently so that the word line separately (WL_0) of sub-storage block (110) and (120) and (WL_1) is activated in corresponding word lines driver (111) and (121).
And as row block address CBA1 in the logic " low " state and when activating sub-storage block (110) and (120), column decoder (371) or (372) should be activated respectively to obtain 2
N-1Page length.In a preferred embodiment, can come in one of sub-storage block (110) or (120) upward to activate column selection line (CSL) according to the logic state of row block address CBA0.For example, in Fig. 3, if row block address CBA0 is in the logic " low " state, then two inputs for NAND circuit (392) will all be " height ", therefore go up at sub-memory cell array block (110) and activate the column selection line (CSL) that produces from column decoder (371), and in response to column selection line (CSL) can chooser storage block (110) alignment.Then, by row block address CBA0 is changed to logic " height ", with the invalid column decoder (371) that is used for sub-storage block (110), and, therefore activation is used for the column decoder (372) of sub-storage block (120) because all inputs of NAND circuit (394) will be logic " height ".
Therefore, in the typical mode of operation described in Fig. 4 B, be 2 for the page length of the word line of an activation
N-1, it is the twice with the page length that operator scheme was obtained of Fig. 4 A.That is, if the user need have 2
N-1The semiconductor memory of page length, then the control signal PL0B controlled signal generator (350) of an activation produces, and is imported into control circuit (360), thereby changes the page length of semiconductor memory.
Another operator scheme of semiconductor memory with schematic construction of Fig. 3 makes the selective activation of four sub-storage blocks can obtain 2
nPage length.On concrete, if control signal PL1B is activated (for example logic " low " state), then all sub-storage blocks (110,120,130,140) will be activated, and no matter the logic state of row block address CBA0B, CBA0, CBA1B and CBA1 how, shown in Fig. 4 C.Particularly, if control signal PL1B is logic " low ", each NAND circuit (363 of control circuit (360) then, 364,367,368) output will be logic " height ", and no matter the logic state of row block address CBA0B, CBA0, CBA1B and CBA1 how.In this operator scheme, will activate sub-storage block (110), (120), (130) and (140) word line (WL_0, WL_1, WL_2, WL_3), and no matter the logic state of row block address CBA0B and CBA1 how.
And, in this operator scheme, can optionally activate the column decoder that is associated with the sub-storage block that is activated according to the logic state of row block address CBA0 and CBA1.Therefore, by the incompatible given column selection line (CSL) that has determined whether to activate sub-storage block of the logical groups of row block address CBA0 and CBA1.Therefore, in this case, semiconductor memory has 2
nPage length.
Useful is, in the exemplary embodiments of Fig. 3, because utilize mode register set (353) to realize control signal generator (350), so mode register set (353) can be exported control signal controllably to change the page length of semiconductor devices according to address and order.
Referring now to Fig. 5 and 6 the sub-demoder shown in Figure 3 and the exemplary embodiments of word line driver are described.Fig. 5 is the circuit diagram of diagram according to the sub-demoder of one embodiment of the present of invention.For description and interpretation, Fig. 5 has described the embodiment of the sub-demoder (312) of Fig. 3.Fig. 6 is the circuit diagram according to the part of the driving circuit of the word line driver of one embodiment of the present of invention.
Referring to Fig. 5, sub-demoder (312) comprises NAND circuit (510), first and second phase inverters (520 and 530).The control signal that NAND circuit (510) receives the first row address RAi (wherein, i=0,1) and exports from NAND circuit (363) and (367) of control circuit (360).First phase inverter (520) receives the output signal of NAND circuit (510) and produces the first gating signal PEIDG.Second phase inverter (530) receives the output signal of NAND circuit (510) and is created in the word line power supply signal PXI of boost level.Sub-demoder (312) is also exported the second gating signal PXIB (output of its right and wrong circuit (510)).
Referring to Fig. 6, word line driver (600) comprise a plurality of MOS transistor (MN1, MN2, MN3, MN4).Supply voltage VCC is provided for the grid of MOS transistor (MN1).First terminal of MOS transistor (MN1) is coupled to normal word line enable signal (NWE) line (as mentioned above, NWE is produced by row decoder (150)).Second terminal of MOS transistor (MN1) is connected to the gate terminal of MOS transistor (MN2).First terminal of MOS transistor (MN2) is connected to word line power supply signal PX1 (for example from sub-demoder (312) output).Second terminal of MOS transistor (MN2) is connected to word line (WL).The grid of MOS transistor (MN3) is connected to the first gating signal PXIDG (for example from demoder (312) output).The grid of MOS transistor (MN4) is connected to the second gating signal PXIB (for example from sub-demoder (312) output).The quantity of the word line that provides on the sub-storage block in correspondence is provided the quantity of the word line driver circuit of realizing in the given word line driver (111,121,131,141) of Fig. 3 (600).
Word line driver (600) in sub-demoder (312) and the word line driver (111) activates word line (WL_0) in response to the output signal of first row address RAi (wherein, i=0,1) and control circuit (360).Particularly, sub-demoder (312) and the following work of word line driver (600).Sub-demoder (312) produces the first gating signal PXIDG, the second gating signal PXIB and word line power supply signal PXI according to input control signal and row address.On concrete, the output signal of having only the NAND circuit (363) of the first line of input address RAi (wherein, i=0,1) and Fig. 3 and (367) is in the logic " high " state time, and the first gating signal PXIDG and word line power supply signal PXI are at the logic " high " state.Under these circumstances, be used for the second gating signal PXIB of pre-charge word line (WL) at logic low state.
In the word line driver (600) of Fig. 6, supply voltage VCC is applied to the grid of MOS transistor MN1, so MOS transistor (MN1) is always connected.When the first gating signal PXIDG and word line power supply signal PXI at logic " high " state and the second gating signal PXIB during at the logic " low " state, MOS transistor (MN3) is connected, and MOS transistor (MN4) disconnects.Therefore, in this case, word line power supply signal PXI and word line WL are connected to each other, and activate word line WL.
On the other hand, if the first gating signal PXIDG and word line power supply signal PXI at logic " low " state and the second gating signal PXIB at the logic " high " state, then MOS transistor (MN3) disconnects, and MOS transistor (MN4) is connected.In this case, invalid word line (WL).
In the exemplary embodiments in aforesaid Fig. 3, realize control signal generator (350) so that produce the control signal that is used to change page length with the MRS (353) of semiconductor memory.Be appreciated that other method and the device that to realize being used to produce control signal according to the present invention.For example, Fig. 7 illustrates the control signal generator (700) according to an alternative embodiment of the invention that uses wire-bonded to realize, Fig. 8 illustrates the control signal generator according to an alternative embodiment of the invention that uses fuse to realize.
More specifically, the control signal generator 700 of Fig. 7 comprise a plurality of weld zones (710a, 710b, 710c, 720a, 720b, 720c) and phase inverter (711,721).Weld zone (710a) and (720a) be connected to supply voltage VCC, and weld zone (710b) and (720b) ground connection.The input end of phase inverter (711) is connected to weld zone (710c), and the input end of phase inverter (721) is connected to weld zone (720c).Phase inverter (721) and (711) output control signal corresponding PL0B and PL1B.
During the manufacturing of semiconductor memory, carry out the process that weld zone (710c) is connected to weld zone (710a) or weld zone (710b) and weld zone (720c) is connected to weld zone (720a) or weld zone (720b).The logic state of the first control signal PL0B and the second control signal PL1B depends on being connected of weld zone.For example, describe as Fig. 7, be connected to weld zone (710b) and weld zone (720c) is connected under the situation of weld zone (720a) at weld zone (710c), control signal PL1B is set to the logic " high " state, and control signal PL0B is set to the logic " low " state.Therefore, if realize the control signal generator circuit (700) of Fig. 7 in the exemplary embodiments of Fig. 3, then the page length of semiconductor memory will be 2
N-1(seeing Fig. 4 B).Certainly, the connection between each weld zone can be changed to produce the control signal of Different Logic state, so that obtain the page length of expectation.Can understand that (VCC, VSS) connection between can realize with metal solder or wire bonds at weld zone and power supply lead wire.
Referring to Fig. 8, according to the control signal generator (800) of an alternative embodiment of the invention comprise diode-coupled MOS transistor (MP1) and (MP2), laser fuze (812) and (822) and phase inverter (813) and (823).The connection that MOS transistor (MP1) has diode-coupled, wherein, the grid and the drain electrode of MOS transistor (MP1) are connected to each other, and source electrode is connected to supply voltage VCC.Laser fuze (812) is connected between the drain electrode and ground voltage of MOS transistor (MP1).The signal of the drain electrode end of the anti-phase MOS transistor of phase inverter (813) (MP1), and output control signal PL1B.
Equally, the connection that MOS transistor (MP2) has diode-coupled, wherein, the grid and the drain electrode of MOS transistor (MP2) are connected to each other, and source electrode is connected to supply voltage VCC.Laser fuze (822) is connected between the drain electrode and ground voltage of MOS transistor (MP2).The signal of the drain electrode end of the anti-phase MOS transistor of phase inverter (823) (MP2), and output control signal PL0B.
The logic state of control signal PL0B and PL1B depends on the state of laser fuze.Particularly, if laser fuze (812) or (822) are disconnected, then Dui Ying control signal will have logic low state, if laser fuze (812) or (822) are not disconnected, then Dui Ying control signal will have the logic " high " state.For example, suppose to have connected laser fuze (812) and disconnected laser fuze (822) that then control signal PL0B is at logic low state, and control signal PL1B is at logic high state.In this case, if realized control signal generator circuit (800) in the exemplary embodiments of Fig. 3, then the page length of semiconductor memory will be 2
N-1(seeing Fig. 4 B).。Certainly, can be according to the state of laser fuze (812) and (822) with the adaptive control signal that produces of control signal generator circuit (800) with Different Logic state.
Fig. 9 is diagram according to the high level flow chart of method of page length that is used to change semiconductor memory of one embodiment of the present of invention.Generally, the method that is used to change the page length of semiconductor memory comprises: produce first control signal (step 910) of specifying one of a plurality of page length operator schemes; Produce second control signal (step 920) according to first control signal and block address; Use second control signal to come to change the page length (step 930) of semiconductor memory then according to the page length operator scheme of appointment.
In one embodiment of the invention, the step (step 910) that produces first control signal comprising: according to the external command and the address that are received by for example Memory Controller or CPU, and produce first control signal.For example, can utilize MRS (353) to come performing step 910 by control signal generator (350) shown in Figure 3.In other embodiments of the invention, can utilize device or method to produce first control signal such as above-mentioned reference example such as Fig. 7 or 8 described control signal generator circuit and method.
And, the step (step 920) that produces second control signal may be implemented as such as above described with reference to Fig. 3, wherein, control circuit is handled from the control signal of control signal generator and a row block address to produce optionally second control signal of the respective word control circuit of control store piece.And, the step (step 930) of adjusting page length in response to second control signal preferably comprises: optionally activate one or more corresponding word lines of the storage block with identical row address in response to second control signal, so that therefore change the page length of semiconductor memory.
Figure 10 is the schematic block diagram that diagram wherein can realize accumulator system of the present invention.Accumulator system (1000) comprises CPU (1001), Memory Controller (1002) and a plurality of memory module (1003).Each memory module (1003) comprises a plurality of semiconductor memories (1004), has wherein realized the present invention.CPU (1001) can be microprocessor (MPU) or network processing unit (NPU).CPU (1001) is by first bus system (B1) (control bus for example, data bus and address bus) be connected to Memory Controller, Memory Controller (1002) is connected to memory module (1003) via second bus system (B2) (control bus, data bus, address bus).In the schematic construction of Figure 10, CPU (1001) control store controller (1002), and Memory Controller (1002) control store (1004) (though can understand to realize the direct control store of CPU and do not use independently Memory Controller).
In the exemplary embodiments of Figure 10, each memory module (1003) can be represented for example memory stick, and each storer (1004) of a given memory module (1003) can represent that is wherein realized a storer of the present invention.In this case, each storer (1004) can logically be divided into a plurality of sub-storage blocks, and is controlled as mentioned above to change page length.In storer (1004), can locate the control circuit that is used for the execute store visit and/or changes page length.
In a preferred embodiment, the storer of a memory module can have the structure of x8 bit, and the storer of another memory module can have the structure of x16 bit.That is, different memory modules can be operated with different bit architecture.
In another embodiment of the present invention, accumulator system can comprise one or more independently semiconductor memories (rather than memory module with a plurality of storage component parts as shown in figure 10) and central processing unit (no memory controller).In this embodiment, storer is directly communicated by letter with central processing unit.In addition, a semiconductor memory can have the structure of x8 bit, and another storer can have the structure of x16 bit.That is, two memory modules can have different bit architecture.
In another embodiment, can comprise one or more independently semiconductor memories (rather than memory module with a plurality of storeies as shown in figure 10) according to accumulator system of the present invention, they are directly communicated by letter with Memory Controller (no CPU).In this embodiment, a storer can have the structure of x8 bit, and another storer can have the structure of x16 bit.
Though this with reference to description of drawings illustrative embodiment, be understood that to the invention is not restricted to accurate system and method embodiment described herein, can under the situation that does not break away from the spirit and scope of the present invention, carry out various other change or improvement by those skilled in the art.All such variations or improvement are intended to be included in by in the appended scope of the present invention that claim limited.
Claims (28)
1. semiconductor memory comprises:
Memory cell array, it logically is divided into a plurality of storage blocks, wherein, can come each storage block of addressing by the block address of correspondence;
A plurality of Word line control circuits, wherein, one of storage block of each Word line control circuit and the word line that is used to activate the storage block that is associated is associated;
Control circuit is used for control word line control circuit optionally and has one or more corresponding word lines of identical row address so that change the page length of semiconductor memory with activation,
Wherein, described control circuit receives the row block address and first control signal as input, produces second control signal then and optionally activates one or more Word line control circuits.
2. device as claimed in claim 1 also comprises the control signal generator, and it receives external command and external address, produces first control signal according to described external command and external address then.
3. device as claimed in claim 2, wherein, the control signal generator comprises:
Address buffer is used to receive external address and produces home address;
Commands buffer is used to receive external command and produces internal command;
Mode register set is used for producing first control signal according to home address and internal command.
4. device as claimed in claim 1, wherein, each Word line control circuit comprises sub-decoder circuit and the word line driver circuit that is associated.
5. device as claimed in claim 4, wherein, second control signal that each sub-decoder circuit receives row address and exports from control circuit is optionally to activate the word line driver circuit that is associated.
6. device as claimed in claim 1, wherein, block address comprises row address and column address.
7. device as claimed in claim 1 also comprises the control signal generator, is used to produce first control signal, and wherein, the control signal generator is configured to produce first control signal by one of wire bond, metal selection and fuse selection.
8. device as claimed in claim 1, wherein, when invalid first control signal, enable a word line in a storage block of a plurality of storage blocks, and wherein when activating first control signal, enable to have at least two word lines of identical row address in two storage blocks of described a plurality of storage blocks.
9. accumulator system comprises:
Memory Controller is used to produce a plurality of orders and address signal;
First memory module, it receives described order and address signal, and described first memory module has a plurality of storeies, wherein, comprises first memory, and described first memory comprises:
Memory cell array, it logically is divided into a plurality of storage blocks, wherein, can come each storage block of addressing by the block address of correspondence;
A plurality of Word line control circuits, wherein, one of storage block of each Word line control circuit and the word line that is used to activate the storage block that is associated is associated;
Control circuit, being used for optionally, the control word line control circuit has one or more corresponding word lines of identical row address so that change the page length of semiconductor memory with activation.
10. accumulator system as claimed in claim 9, also comprise second memory module, be used to receive order and the address signal that produces by Memory Controller, described second memory module comprises a plurality of storeies, comprising second memory, wherein, described second memory comprises the memory cell array that logically is divided into a plurality of storage blocks;
Wherein, first memory has first bit architecture, and second memory has second bit architecture, and wherein, first bit architecture is different with second bit architecture.
11. accumulator system as claimed in claim 9, wherein, control circuit receives the row block address and first control signal as input, produces second control signal then optionally to activate one or more Word line control circuits.
12. accumulator system as claimed in claim 11 also comprises the control signal generator, wherein, the control signal generator comprises:
Address buffer is used to receive the address signal that is produced by Memory Controller and produces home address;
Commands buffer is used to receive the order that is produced by Memory Controller and produces internal command;
Mode register set is used for producing first control signal according to home address and internal command.
13. accumulator system as claimed in claim 12, wherein, when invalid first control signal, a storage block in a plurality of storage blocks enables a word line, and wherein when activating first control signal, enable to have at least two word lines of identical row address in two storage blocks of described a plurality of storage blocks.
14. an accumulator system comprises:
Central processing unit is used to produce a plurality of orders and address signal;
First memory module, it receives described order and address signal, and described first memory module has a plurality of storeies, and comprising first memory, described first memory comprises:
Memory cell array, it logically is divided into a plurality of storage blocks, wherein, can come each storage block of addressing by the block address of correspondence;
A plurality of Word line control circuits, wherein, one of storage block of each Word line control circuit and the word line that is used to activate the storage block that is associated is associated;
Control circuit, being used for optionally, the control word line control circuit has one or more corresponding word lines of identical row address so that change the page length of semiconductor memory with activation.
15. accumulator system as claimed in claim 14, also comprise second memory module, be used to receive order and the address signal that produces by central processing unit, described second memory module comprises a plurality of storeies, comprising second memory, wherein, described second memory comprises the memory cell array that logically is divided into a plurality of storage blocks;
Wherein, first memory has first bit architecture, and second memory has second bit architecture, and wherein, first bit architecture is different with second bit architecture.
16. accumulator system as claimed in claim 14, wherein, first memory also comprises the control signal generator, and wherein, the control signal generator comprises:
Address buffer is used to receive the address signal that is produced by central processing unit and produces home address;
Commands buffer is used to receive the order that is produced by central processing unit and produces internal command;
Mode register set is used for producing first control signal according to home address and internal command.
17. accumulator system as claimed in claim 16, wherein, when invalid first control signal, a storage block in a plurality of storage blocks enables a word line, and wherein when activating first control signal, enable to have at least two word lines of identical row address in two storage blocks of described a plurality of storage blocks.
18. accumulator system as claimed in claim 14, wherein, central processing unit is network processing unit (NPU).
19. an accumulator system comprises:
Memory Controller is used to produce a plurality of orders and address signal;
First memory is used to receive described order and address signal, and described first memory comprises:
Memory cell array, it logically is divided into a plurality of storage blocks, wherein, can come each storage block of addressing by the block address of correspondence;
A plurality of Word line control circuits, wherein, one of storage block of each Word line control circuit and the word line that is used to activate the storage block that is associated is associated;
Control circuit, being used for optionally, the control word line control circuit has one or more corresponding word lines of identical row address so that change the page length of semiconductor memory with activation.
20. accumulator system as claimed in claim 19 also comprises second memory, it receives order and the address signal that is produced by Memory Controller, and described second memory comprises the memory cell array that logically is divided into a plurality of storage blocks;
Wherein, first memory has first bit architecture, and second memory has second bit architecture, and wherein, first bit architecture is different with second bit architecture.
21. an accumulator system comprises:
Central processing unit is used to produce a plurality of orders and address signal;
First memory is used to receive described order and address signal, and described first memory comprises:
Memory cell array, it logically is divided into a plurality of storage blocks, wherein, can come each storage block of addressing by the block address of correspondence;
A plurality of Word line control circuits, wherein, one of storage block of each Word line control circuit and the word line that is used to activate the storage block that is associated is associated;
Control circuit, being used for optionally, the control word line control circuit has one or more corresponding word lines of identical row address so that change the page length of semiconductor memory with activation.
22. accumulator system as claimed in claim 21 also comprises second memory, it receives order and the address signal that is produced by central processing unit, and described second memory comprises the memory cell array that logically is divided into a plurality of storage blocks;
Wherein, first memory has first bit architecture, and second memory has second bit architecture, and wherein, first bit architecture is different with second bit architecture.
23. accumulator system as claimed in claim 21, wherein, central processing unit is network processing unit (NPU).
24. accumulator system as claimed in claim 21, wherein, central processing unit is microprocessor (MPU).
25. method that is used to change the page length of semiconductor memory, described semiconductor memory comprises: memory cell array, and it logically is divided into a plurality of storage blocks, wherein, can come each storage block of addressing by the block address of correspondence, described method comprises step:
Produce first control signal of specifying one of a plurality of page length operator schemes;
Produce second control signal according to first control signal and block address;
In response to second control signal, the one or more word lines in storage block with identical row address are optionally activated so that the page length corresponding to the semiconductor memory of specifying the page length operator scheme to be provided.
26. method as claimed in claim 25, wherein, the step that produces first control signal comprises step:
Receive command signal and address signal;
Produce first control signal according to described command signal and address signal.
27. method as claimed in claim 26, wherein, first control signal is produced by mode register set.
28. method as claimed in claim 25, wherein, the step that activates the one or more word lines in storage block comprises step:
Import second control signal and row address to a plurality of sub-demoders;
Activate the one or more word line drivers that are associated with storage block according to the word line power supply signal that produces by sub-demoder.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
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| KR72093/2002 | 2002-11-19 | ||
| KR72093/02 | 2002-11-19 | ||
| KR10-2002-0072093A KR100510496B1 (en) | 2002-11-19 | 2002-11-19 | Semiconductor memory device having the structure of being capable of converting page length according to specific mode, and method of converting page length of the semiconductor memory device |
| US10/639,858 US6868034B2 (en) | 2002-11-19 | 2003-08-13 | Circuits and methods for changing page length in a semiconductor memory device |
| US10/639,858 | 2003-08-13 |
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| CN1503272A CN1503272A (en) | 2004-06-09 |
| CN100538885C true CN100538885C (en) | 2009-09-09 |
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| CNB2003101163188A Expired - Fee Related CN100538885C (en) | 2002-11-19 | 2003-11-19 | Be used for changing circuit and method at the page length of semiconductor memory |
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| JP (1) | JP2004171753A (en) |
| CN (1) | CN100538885C (en) |
| DE (1) | DE10354523A1 (en) |
| TW (1) | TWI233619B (en) |
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| US7793037B2 (en) * | 2005-05-31 | 2010-09-07 | Intel Corporation | Partial page scheme for memory technologies |
| JP5212100B2 (en) * | 2006-03-30 | 2013-06-19 | 富士通セミコンダクター株式会社 | Semiconductor memory and memory system |
| JP2008108417A (en) * | 2006-10-23 | 2008-05-08 | Hynix Semiconductor Inc | Low power dram and its driving method |
| TWI417894B (en) * | 2007-03-21 | 2013-12-01 | Ibm | Structure and method of implementing power savings during addressing of dram architectures |
| JP2009238323A (en) * | 2008-03-27 | 2009-10-15 | Fujitsu Microelectronics Ltd | Semiconductor memory device, image processing system and image processing method |
| CN101582295B (en) * | 2008-05-14 | 2012-04-18 | 新唐科技股份有限公司 | Data update method and system |
| US8811110B2 (en) | 2012-06-28 | 2014-08-19 | Intel Corporation | Configuration for power reduction in DRAM |
| US11210019B2 (en) | 2017-08-23 | 2021-12-28 | Micron Technology, Inc. | Memory with virtual page size |
| US10394456B2 (en) * | 2017-08-23 | 2019-08-27 | Micron Technology, Inc. | On demand memory page size |
| CN110910923A (en) * | 2018-09-14 | 2020-03-24 | 北京兆易创新科技股份有限公司 | Word line decoding method and nonvolatile memory system |
| CN109902041A (en) * | 2019-03-11 | 2019-06-18 | 中国核动力研究设计院 | A kind of SDRAM driver design method based on FPGA |
| CN114645819B (en) * | 2022-05-19 | 2022-09-13 | 东方电气风电股份有限公司 | Wind power pitch control method, device and system and storage medium |
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- 2003-11-07 TW TW92131236A patent/TWI233619B/en not_active IP Right Cessation
- 2003-11-14 DE DE2003154523 patent/DE10354523A1/en not_active Ceased
- 2003-11-17 JP JP2003387074A patent/JP2004171753A/en active Pending
- 2003-11-19 CN CNB2003101163188A patent/CN100538885C/en not_active Expired - Fee Related
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| JP2004171753A (en) | 2004-06-17 |
| TWI233619B (en) | 2005-06-01 |
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| CN1503272A (en) | 2004-06-09 |
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