CN100526902C - Circuit for inspecting semiconductor device and inspecting method - Google Patents
Circuit for inspecting semiconductor device and inspecting method Download PDFInfo
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- CN100526902C CN100526902C CNB2004800079643A CN200480007964A CN100526902C CN 100526902 C CN100526902 C CN 100526902C CN B2004800079643 A CNB2004800079643 A CN B2004800079643A CN 200480007964 A CN200480007964 A CN 200480007964A CN 100526902 C CN100526902 C CN 100526902C
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Abstract
The present invention provides an inspection circuit and method for a semiconductor device. The inspection circuit comprises an arrangement where a plurality of NAND circuits are connected in series through a plurality of inverters, and an arrangement where a plurality of NOR circuits are connected in series through the plurality of inverters. A plurality of source signal lines are connected, respectively, with one input terminal of the NAND circuits and NOR circuits and an inspection output is obtained from the final stages of the NAND circuits and NOR circuits connected in series. Inspection circuit and method capable of judging failure easily and accurately using small-scale circuitry are thereby provided.
Description
Technical field
The present invention relates to be arranged on the check circuit in the display device of pixel region that has pixel arrangement and become matrix shape and the inspection method of display device.In addition, the present invention relates to have the check circuit and the inspection method of semiconductor device that pixel arrangement becomes the pixel region of matrix shape.
Background technology
In with the display device headed by LCD (LCD) and electroluminescence (EL) display etc., in recent years big pictureization, height become more meticulous in progress, in addition, also make progress by peripheral circuit integrally formed integrated technology of circuit height that makes on substrate of pixel portions and being used for being controlled pixel portions.
In manufacturing process, when, electrostatic breakdown (ESD) etc. bad owing to composition causes element to take place to destroy, because the regular event of unpredictable display device itself must be got rid of it by the quality inspection.Generally, the quality inspection of display device, be in the TFT substrate 1201 that is formed with Source drive (circuit) 1203, gate driver 1204, pixel region 1205, signal input terminal 1206 etc. shown in Figure 12 A and counter substrate 1202 are bonded stage into finished product module 1200, shown in Figure 12 B, in fact utilize guide plate 1211 grades that signal is imported, carry out the demonstration of image or image (test pattern 1212 etc.), show and to have or not defect to carry out by picture being looked recognize to observe.
Yet, when utilizing this method, exist because display device itself is checked in the stage of almost finishing as module 1200, spend in the shortcoming with high costs that is judged to be on the defective module and make.In other words, because the bad defective that causes of circuit, cause only is TFT substrate 1201, follows the bonding operation of counter substrate 1202 grades to become waste but make.In addition, only also can consider to make the pixel portions that formed by TFT etc. and the substrate (TFT substrate) of peripheral circuit, as such forms such as semi-manufacture dispatch from the factory, but in fact be impossible carry out the quality inspection in the demonstration in reality under this occasion.In other words, must have the whether normal instrument of judgement circuit operation under the state of TFT substrate.
Figure 11 is an example of the structure of this kind of realization inspection.On substrate, form by shift register (SR) and NAND circuit 19 data latches 20, D/A transducer (DAC) 21, video data line 23, the digital source driver 18 that the input terminal 22,16 of signal, power supply etc. etc. constitute; Gate driver 5; Pixel 3 is configured as the pixel region of matrix shape; By keeping electric capacity line 15 and switch driving circuit 30, analog switch 25 is checked line 27, checks the check circuit that terminal 28 grades constitute.
Display device shown in Figure 11, the pixel of utilizing each gate signal line 6 control to be connected with this row, signal of video signal is input to digital source driver 18, outputs to source signal line 9, is written to each pixel.
In check circuit, by signal of video signal is write pixel through each pixel TFT 1, with remain on the electric charge that keeps in the electric capacity 2 successively on inspection line 27 output to and check terminal 28, whether writing of pixel is successfully judged.In addition, analog switch 25 is controlled (with reference to patent documentation 1) by switch driving circuit 30.In addition, also have, utilize probe to contact the method (with reference to patent documentation 2) of each pad inspection output each source signal line 9 difference configuration inspection pads.
Patent documentation 1: Japanese Patent Application Laid-Open 2002-116423 communique
Patent documentation 2: No. 2618042 instructions of Japanese patent application
Summary of the invention
Yet, when utilizing the method for above-mentioned patent documentation record, exist in the remarkable low problem of the processing power of checking in the display device of high-resolution, big picture, and, must utilize switch driving circuit 30 grades to control, have the problem of the erection space expansion make the check circuit on substrate etc.Particularly, when the former this method of employing, in the meticulous display device of height, be unpractical.
The present invention system is because the problems referred to above and the invention finished, can provide a kind of can be with extremely simple method and use small-scale check circuit decision circuit action, have or not the check circuit and the inspection method of line defect etc.
For addressing the above problem, adopt following way in the present invention.
Along with height becomes more meticulous,, as mentioned above, consider it is unpractical from the aspects of checking such as processing power to the method that the signal that outputs to the signal wire that the bar number increases is checked with probe respectively.So in the present invention, the output with whole grades signal wires is input to check circuit, can will all import a resulting specific figure as result of determination to these.So, will all be that the figure of the inspection output of normal occasion compares as reference figure and resulting result of determination in advance.
When the output of a certain signal line is undesired, just can obtain with above-mentioned with reference to the different output of figure.So, by measuring the output in one or several places, compare with the form of the output that under normal condition, should obtain and just can carry out whether good judgement.As a result, just needn't confirm and judge having or not of bad place rapidly each pulse output.
According to the present invention, do not check even do not utilize looking of actual detection graphic presentation to recognize, owing to can judge whether the state of TFT substrate is good, can utilize small-scale check circuit, carry out effective quality inspection extremely simply.
In specific words, can be in multiple display device such as the LCD that signal of video signal is used digital signal, EL display, plasma scope, carry out the whether good judgement of circuit operation.And, do not need to be used for driving the circuit of check circuit itself, can be by the extremely simple steps of driver action being checked with the same step of the occasion of common demonstration.In addition, because it is irrelevant with the bar number of source signal line, only the H level/L level (output signal) of the output by confirming to check lead-out terminal just can judge immediately that whole levels have zero defect, can be effectively applied to the inspection of the display device used in picture, high meticulous screen board greatly.
Description of drawings
Figure 1A, 1B are the diagrammatic sketch that one embodiment of the present invention is shown.
Fig. 2 is the diagrammatic sketch that the sequential chart of Source drive and check circuit is shown.
Fig. 3 A, 3B are check circuit action when regular event is shown and the diagrammatic sketch of checking output.
Fig. 4 A, 4B are the diagrammatic sketch that the check circuit action in the bad Mode A of action is shown and checks output.
Fig. 5 A, 5B are the diagrammatic sketch that the check circuit action in the bad Mode B of action is shown and checks output.
Fig. 6 A, 6B are the diagrammatic sketch that the check circuit action among the bad pattern C of action is shown and checks output.
Fig. 7 A, 7B are the diagrammatic sketch that the check circuit action among the bad pattern D of action is shown and checks output.
Fig. 8 A, 8B are the diagrammatic sketch that the check circuit action among the bad pattern E of action is shown and checks output.
Fig. 9 A, 9B are the diagrammatic sketch that the check circuit action in the bad model F of action is shown and checks output.
Figure 10 A, 10B are the diagrammatic sketch that another embodiment of the present invention is shown.
Figure 11 is the diagrammatic sketch that the structure of the display device with existing check circuit is shown.
Figure 12 A, 12B are the diagrammatic sketch that the form of module is shown and uses the summary that the quality of probe checks.
Figure 13 is the diagrammatic sketch that one embodiment of the present invention is shown.
Figure 14 is the diagrammatic sketch that one embodiment of the present invention is shown.
Figure 15 is the diagrammatic sketch that the sequential chart of gate driver and check circuit is shown.
Figure 16 is the diagrammatic sketch that the sequential chart of gate driver and check circuit is shown.
Figure 17 is the diagrammatic sketch of cutting apart example that check circuit is shown.
Embodiment
Utilize accompanying drawing that embodiments of the present invention are elaborated below.But, the present invention is not limited to the following description, does not break away from thought of the present invention and scope thereof and can carry out all changes to its form and details and be readily appreciated that for those skilled in the art.So the present invention is not limited to the explanation of the record content of embodiment shown below.In addition, in the following description, represent that the symbol of same parts is general between different accompanying drawings.
(embodiment 1)
In one embodiment of the present invention shown in Figure 1A.On substrate, form Source drive 101, gate driver 102, pixel region 106, check circuit 108 and check lead-out terminal 107.A plurality of pixels 105 are configured as matrix shape in the pixel region 106, and each pixel is by source signal line 103 and 104 controls of gate signal line.
The structure of check circuit is shown in Figure 1B.Check circuit 108, be by a plurality of NAND 112 and a plurality of phase inverters 114 series connection and the circuit that is connected respectively with source signal line 103 mutually, with a plurality of NOR 113 and a plurality of phase inverters 115 mutually series connection and be arranged in parallel with circuit that source signal line 103 is connected respectively form, both sides' last level output outputs to and checks lead-out terminal 107a, 107b.
In specific words, in check circuit 108, the 1st input end of the 1st grade NAND is connected with power supply (VDD), and the 2nd input end is connected with source signal line (S1), and output terminal is connected with the input end of the 1st grade phase inverter.The output terminal of the 1st grade phase inverter is connected with the 1st input end of the 2nd grade NAND.Below the 2nd grade, (in the level of 2≤m≤n), the 1st input end of the NAND of m level is connected with the inverter output of m-1 level, and the 2nd input end is connected with source signal line (Sm), and output terminal is connected with the input end of the phase inverter of m level at a certain m.The output terminal of the phase inverter of m level is connected with the 1st input end of the NAND of m+1 level.Last level, i.e. the phase inverter of n level output outputs to and checks lead-out terminal 107a.
On the other hand, the 1st input end of the 1st grade NOR 113 is connected with power supply (VSS), and the 2nd input end is connected with source signal line (S1), and output terminal is connected with the input end of the 1st grade phase inverter.The output terminal of the 1st grade phase inverter is connected with the 1st input end of the 2nd grade NOR.Below the 2nd grade, in a certain m level, the 1st input end of the NOR of m level is connected with the inverter output of m-1 level, and the 2nd input end is connected with source signal line (Sm), and output terminal is connected with the input end of the phase inverter of m level.The output terminal of the phase inverter of m level is connected with the 1st input end of the NOR of m+1 level.Last level, i.e. the phase inverter of n level output outputs to and checks lead-out terminal 107b.
Then, utilize Figure 1A, 1B that actual inspection step is shown.Herein, the example as the Source drive of line order digital form is described.
When checking, make Source drive 101 actions.As method of operating, can be the same with the common occasion of carrying out the image demonstration.But, when checking, as signal of video signal, the order input makes whole source signal lines become the state of H level output and makes whole source signal lines become the state of L level output.
In Fig. 2, the simple sequential chart of Source drive 101 is shown, below its action is illustrated successively.In Fig. 2, as input signal, clock signal (SCK), initial pulse (SSP), latch pulse (SLAT) and digital image signal (Data) are shown, the sampling pulse (Samp.1～4, Samp.n), the source signal line that illustrate the 1st grade～the 4th grade, last grade as output signal are exported (SLine: drive in proper order in order to carry out line, S1～Sn all carries out data simultaneously and switches).
At first, the 1st line cycle (Period1) was described.Shift register is according to clock signal and initial pulse 201 actions, and order is exported sampling pulse 205.Sampling pulse 205 carries out the sampling of digital image signal respectively, and data are remained in latch cicuit.
In addition, in the cycle, digital image signal 207 is all imported the H level at the 1st line.
After in the end the sampling of Ji digital image signal was finished, during input and latch pulse 203, the data that remain in the latch cicuit outputed to source signal line simultaneously.The source signal line output of this moment also remains to cycle till next latch pulse 204 inputs by latch cicuit always.
Herein, source signal line output is all becoming H level (210) in the level.
Afterwards, transferred to for the 2nd line cycle (Period2).The same with the 1st line cycle, according to clock signal and initial pulse 202, order is exported sampling pulse 206, carries out the sampling of digital image signal.
In addition, in the cycle, digital image signal 208 is all imported the L level at the 2nd line.
Then, when latch pulse 204 inputs, the data that remain in the latch cicuit output to source signal line simultaneously.At this moment, source signal line output in whole levels, becomes L level (211).
Below, action of check circuit etc. is described.Now, in the cycle 210,, all exporting the H level in the level to source signal line.So check circuit becomes the state shown in Fig. 3 A.On the 1st input end of NAND 301, import power supply (VDD), input H level on the 2nd input end.So the output of NAND 301 becomes the L level.In addition, this output through the phase inverter counter-rotating, is input to secondary NAND.After, this is repeated, at last to checking lead-out terminal 107a output H level.
On the other hand, on the 1st input end of NOR 302, import power supply (VSS), input H level on the 2nd input end.So the output of NOR 302 becomes the L level.In addition, this output through the phase inverter counter-rotating, is input to secondary NOR.After, this is repeated, at last to checking lead-out terminal 107b output H level.
Afterwards, in cycle with 211 expressions, to source signal line, in whole levels, output L level.So check circuit becomes the state shown in Fig. 3 B.With above-mentioned the same, the NAND, the NOR that are connected with whole source signal lines action in this occasion, is all exported the L level to any one that check lead-out terminal 107a, 107b.
State at the inspection lead-out terminal of this occasion, be that source signal line is exported when being the H level on whole levels, any one that check lead-out terminal all exported the H level, and source signal line is exported when being the L level on whole levels, any one that check lead-out terminal all exported the state of L level, is the normal output of checking.In other words, show in whole levels, the input of the signal of video signal of the signal of video signal of H level and L level is normally carried out, and carries out discharging and recharging of source signal line.
Hypomere at the sequential chart of Fig. 2 is illustrated in the inspection lead-out terminal 107a on 107a, the 107b, the output waveform of 107b.
Herein, suppose with shown in following A～F several and move bad pattern.
A: the output of source signal line (S4) is fixed as the occasion of H level.
B: the output of source signal line (S4) is fixed as the occasion of L level.
C: the output of source signal line (S4) and common opposite occasion.
D: the output of source signal line (S2, S4) is fixed as the occasion of H level.
E: the output that the output of source signal line (S2) is fixed as H level, source signal line (Sn) is fixed as the occasion of L level.
F: the output of source signal line (S2) is fixed as the output and common opposite occasion of L level, source signal line (Sn).
These actions are bad, such as, be since the element that the short circuit of the bad source signal line that causes of composition and power lead etc. and the electrostatic breakdown in the operation cause destroy the action of the circuit that is produced bad etc. due to.Below each of moving among bad A～F is illustrated the action of check circuit.
Fig. 4 A, 4B illustrate the check circuit action in the bad Mode A of action and check output.In this moves bad pattern, source signal line (S4), irrelevant with digital image signal, be fixed as the H level.Bad place is with symbol " * " 400 expressions.At this moment,, in other words, in Fig. 4 A, be the logic same in whole levels, all export the H level, be judged to be normally checking on lead-out terminal 107a, the 107b with regular event because source signal line is the state of output H level.Yet, when source signal line is exported the L level in whole levels, shown in Fig. 4 B, in NOR401, produce logic inversion, after, keep this reverse logic former state constant, checking output H level on the lead-out terminal 107b, promptly be judged to be bad.
Fig. 5 A, 5B illustrate the check circuit action in the bad Mode B of action and check output.In this moves bad pattern, source signal line (S4), irrelevant with digital image signal, be fixed as the L level.Bad place is with symbol " * " 500 expressions.Because source signal line for the state of output L level, in other words, in Fig. 4 B, is the logic same with regular event in whole levels, all export the L level to checking on lead-out terminal 107a, the 107b, be judged to be normally.Yet, when source signal line is exported the H level in whole levels, in NAND 501, produce logic inversion, checking output L level on the lead-out terminal 107a, promptly be judged to be bad.
Fig. 6 A, 6B illustrate the check circuit action among the bad pattern C of action and check output.In this moves bad pattern, source signal line (S4), digital image signal is exported counter-rotating relatively.Bad place is with symbol " * " 600 expressions.In this occasion, no matter be in the whole levels of source signal line for exporting the occasion of H level, still in the occasion of exporting the L level, all occurrence logic counter-rotatings in NAND 601, NOR 602 respectively, by in the former, inspection lead-out terminal 107a being exported the L level, in the latter, inspection lead-out terminal 107b is exported the H level and obtains bad judgement.
Example up to now, narration be for whole source signal lines, bad place is one a occasion.In action bad pattern D～F, be the example when having a plurality of bad place.
Fig. 7 A, 7B illustrate the check circuit action among the bad pattern D of action and check output.In this moved bad pattern, in 2 places of source signal line (S2, S4), each was all irrelevant with digital image signal, is fixed as the H level.Bad place is with symbol " * " 700,710 expressions.Because source signal line for the state of output H level, in other words, in Fig. 7 A, is the logic same with regular event in whole levels, be judged to be normal.Yet, shown in Fig. 7 B, because when being a plurality of in bad place, the initial bad place that occurs, promptly with NOR701 that source signal line (S2) is connected in after the logic inversion, the bad place that occurs secondly, promptly with NOR 702 that source signal line (S4) is connected in do not change, the logic inversion state is kept intact constant, so to checking that lead-out terminal 107b goes up output H level, is judged to be bad.
Fig. 8 A, 8B illustrate the check circuit action among the bad pattern E of action and check output.In this moves bad pattern, irrelevant with digital image signal in source signal line (S2), be fixed as the H level, and in source signal line (Sn), irrelevant with digital image signal, be fixed as the L level.Bad place is with symbol " * " 800,810 expressions.Shown in Fig. 8 A, 8B, for the former bad place, logic inversion in NOR 802, to checking that lead-out terminal 107b goes up output H level, for the latter's bad place, logic inversion in NAND 801, to checking that lead-out terminal 107a goes up output L level, can obtain bad judgement.Like this, even produce the bad of different modes, can not hinder mutual inspection output yet and correctly judge in a plurality of places.
Fig. 9 A, 9B illustrate the check circuit action in the bad model F of action and check output.In this moves bad pattern, irrelevant with digital image signal in source signal line (S2), be fixed as the L level, and in source signal line (Sn), to digital image signal, the output counter-rotating.Bad place is with symbol " * " 900,910 expressions.Shown in Fig. 9 A, 9B, for the former bad place, logic inversion in NAND 901, to checking that lead-out terminal 107a goes up output L level, for the latter's bad place, logic inversion in NOR 902, to checking that lead-out terminal 107b goes up output H level, can obtain bad judgement.Even in this pattern, source signal line (Sn) bad can not influence the logical inverse that occurs then correctly judge in NAND 901.
As mentioned above, check circuit of the present invention, can extremely correctly carry out bad judgement to multiple bad pattern, so long as input digit signal of video signal, whether good use is carried out the display device of the driver of output format for numbers to source signal line, can carry out circuit operation judgement in multiple display device such as LCD, EL display, plasma scope.And, do not need to be used for driving the circuit of check circuit itself, with the same can the inspection usually by the extremely simple steps that only makes the driver action.
In addition, as Fig. 3～shown in Figure 9, the output (signal) of the output (signal) of the inspection lead-out terminal that is connected with circuit one side of using NAND to constitute and the inspection lead-out terminal that is connected with circuit one side of using NOR to constitute, no matter be to be any occasion in H level or the L level at digital image signal, in the occasion that obtains identical output is normal, and the occasion of certain bad judgement is appearring, two output differences of checking lead-out terminal.Therefore, by the comparator circuit of the identity property of judging these two outputs of checking lead-out terminals is set, can obtain easilier and check output.
In specific words, shown in Figure 10 A, 10B, whether good checking at two also to connect on the lead-out terminals with the signal that the occurs ExNOR (Exclusive-NOR) 1001 as input, can be H level or L level according to the output of checking lead-out terminal 107 also, carry out judgement.According to the structure shown in Figure 10 A, when ExNOR output is the H level, be judged to be non-defective unit, and during the L level, be judged to be bad.Truth value table at ExNOR circuit shown in Figure 10 B.In addition, use ExOR (Exclusive-OR) to replace ExNOR too.In this occasion, when ExOR output is the L level, be judged to be non-defective unit, and during the H level, be judged to be bad.
In addition, in Figure 1A, in signal of video signal (Data) input form is the occasion of analog form, by only when checking will with the digital signal of the peak swing same degree of the signal of video signal of reality as checking the signal input, can be not limited to digital form, analog form is checked.
In addition, the invention is characterized in, be input to check circuit once, needn't observe waveform at any time, utilize the judgement waveform of 1 or 2 figure just can finish inspection by output signal with many signal line.
In other words, the structure of check circuit is not limited to Figure 1B and Figure 10, and it is different and have a structure of the function of equivalence also to comprise circuit structure.
(embodiment 2)
Check circuit of the present invention and inspection method, the action checking that is applied to gate driver also is easy to realize.In the present embodiment, the example that the check circuit of explanation in embodiment 1 is applied to the action checking of gate driver is shown.
Configuration example shown in Figure 13.On substrate, form Source drive 1301, gate driver 1302, pixel region 1306, check circuit 1310 and lead-out terminal 1313.A plurality of pixels 1305 are configured as matrix shape in the pixel region 1306, and each pixel is by source signal line 1303 and 1304 controls of gate signal line.
Source drive 1301 utilizes the input of clock signal (SCK), initial pulse (SSP), and order is exported sampling pulse in shift register and NAND circuit 1351.Thereafter, carry out the sampling of signal of video signal (Data) in data latches 1352, accept amplitude conversion or amplification in level displacement shifter and impact damper 1353, order outputs to source signal line.
Gate driver 1302 utilizes the input of clock signal (GCK), initial pulse (GSP), and order is exported strobe pulse in shift register and NAND circuit 1354., in level displacement shifter and impact damper 1355 accept amplitude conversion or amplification thereafter, and the gate signal line of each row of select progressively (G1～Gm).
The structure of check circuit 1310 shown in Figure 14.The check circuit 1310 that is provided with being used for checking gate driver 1302 describes below.Check circuit 1310, latch cicuit 1311 and the decision circuit 1312 be made up of the 1st latch cicuit the 1401, the 2nd latch cicuit 1402 constitute.Decision circuit 1312 has the structure same with the check circuit of Source drive, be by a plurality of NAND 112 and a plurality of phase inverters 114 mutually series connection and with the gate signal line (circuit of G1～Gm) be connected respectively, with a plurality of NOR 113 and a plurality of phase inverters 114 mutually series connection and with the gate signal line (circuit of G1～Gm) be connected respectively is arranged in parallel and forms, both sides' last level output outputs to and checks lead-out terminal 107a, 107b.
Then, utilize Figure 13, Figure 14 that actual inspection step is shown.When checking, make gate driver 1302 actions.As method of operating, can be the same with the common occasion of carrying out the image demonstration.
In Figure 15, the simple sequential chart of gate driver 1302 and check circuit 1310 is shown, below its sequence of movement is illustrated.In Figure 15, input signal as driver one side, clock signal (GCK), initial pulse (GSP) are shown, illustrate as the input signal of check circuit one side and to check with signal (CCK1, CCK2), check, as output signal the 1st row～the 4 row, capable strobe pulse (Gline1～4, Gline m), check circuit that m is capable are shown and latch output (C1～Cm) with data latch signal (CLAT).
At first, the 1st frame period (Period1) is described.Shift register is according to clock signal (GCK) and initial pulse (GSP) 1501 actions, and order is exported row strobe pulse 1502.Row strobe pulse 1502 thereafter, is accepted amplitude conversion or amplification respectively, selects the gate signal line of each row.
On the other hand, the capable strobe pulse 1502 of order output is input to the 1st latch cicuit 1401 in the check circuit, obtains and checks with signal (CCK1, CCK2) 1503 or 1504.In this cycle (Period1), in whole the 1st latch cicuits 1401, input H level.Row strobe pulse 1502, go up to last from the 1st row output, after input in whole levels of the 1st latch cicuit 1401 in check circuit is finished, input checking is sent to the 2nd latch cicuit 1402 with data latch signal (CLAT) 1505 simultaneously with the data that remain in the 1st latch cicuit 1401.
At this moment, check circuit latchs output (C1～C4, Cm), as shown in figure 15, all becomes H level (1506).
Afterwards, transfer to the 2nd frame period (Period2).(Period1) is the same with the 1st frame period, and row strobe pulse 1512 is selected the gate signal line of each row according to clock signal and initial pulse 1511 order outputs.
Thereafter too, the capable strobe pulse 1512 of order output is input to the 1st latch cicuit 1401 in the check circuit, obtains and checks with signal (CCK1, CCK2) 1503 or 1504.In this cycle (Period2), in whole the 1st latch cicuits 1401, input L level.Row strobe pulse 1512, go up to last from the 1st row output, after input in whole levels of the 1st latch cicuit 1401 in check circuit is finished, input checking is sent to the 2nd latch cicuit 1402 with data latch signal (CLAT) 1515 simultaneously with the data that remain in the 1st latch cicuit 1401.
At this moment, check circuit latchs output (C1～C4, Cm), all becomes L level (1516).
Afterwards, the same step of inspection of the Source drive shown in utilization and the embodiment 1, the legitimacy of the selection timing of judgement gate signal line etc.Because the action of decision circuit 1312 is identical, omit its explanation herein.
In addition, as shown in figure 16, by checking with signal (CCK1, CCK2), for example, as importing with the clock signal of gate driver one side clock signal (GCK) same frequency, even incorrect occasion regularly appears in the output of row strobe pulse in certain delegation, also can utilize inspection output to carry out bad judgement.At this moment, utilize the odd-numbered line of gate signal line that CCK1 is imported, utilize the even number line of gate signal line that CCK2 is imported.
In specific words, owing to reasons such as the TFT of shift register portion are bad, the capable strobe pulse that should export in proper order, sometimes certain a bit on bad problems such as the pulsing width broadens.Usually, because in use in the shift register of clock signal controlling, the pulse front edge or the pulse back edge of clock signal is a lot of as the occasion of action triggers point, so pulse width is incorrect or the like, the occasion of widening of degree that becomes clock semiperiod size is a lot.The timing of latching action in check circuit, the occasion that described from here this incorrect pulse is determined, utilize inspection signal shown in Figure 15, can be judged to be normal, but when signal is used in the inspection of using clock signal shape shown in Figure 16, when the 1st latch cicuit 1401 moved in incorrect timing, the logic inversion of the data during owing to input can carry out high-precision bad judgement.
At the check circuit of the present invention shown in embodiment 1, the embodiment 2, with regard to the action of the actual specification aspect of display device and nonessential circuit.So, shown in Figure 17 A, on substrate, formed after the 1st module 1700 of integrally formed check circuit 1701,1702, inspection operation through above-mentioned is partitioned into when the desired size, at last shown in Figure 17 B, remove check circuit 1701,1702, obtain module 1710 and get final product.
In addition, be not limited to display device, the output that also can be applied to the address decoder that uses among storer etc. judges or the like, can expect to be widely used in to have the inspection of the semiconductor device of a large amount of signal output pins.
Claims (23)
1. the check circuit of a semiconductor device is characterized in that comprising:
A plurality of signal wires;
A plurality of NAND; And
Be electrically connected to the lead-out terminal of above-mentioned check circuit of the lead-out terminal of above-mentioned a plurality of NAND,
The lead-out terminal of the NAND of i-1 level is electrically connected to first input end of the NAND of i level, and i is the integer more than or equal to 2,
Second input terminal of the NAND of above-mentioned i-1 level and i level is connected respectively to i-1 level and i level signal wire; And
At least one signal that use obtains on the lead-out terminal of above-mentioned check circuit carries out the whether judgement of regular event of above-mentioned semiconductor device.
2. the check circuit of semiconductor device as claimed in claim 1 is characterized in that:
Above-mentioned check circuit also has a plurality of NOR and a plurality of phase inverter;
The lead-out terminal of the NAND of above-mentioned i-1 level, sub an electrical connection of the first input end with the NAND of above-mentioned i level among above-mentioned a plurality of phase inverters;
The lead-out terminal of the NOR of i-1 level, another among above-mentioned a plurality of phase inverters is electrically connected with first input end of the NOR of i level;
Above-mentioned a plurality of signal wire is electrically connected with second input terminal of above-mentioned a plurality of NAND and second input terminal of above-mentioned a plurality of NOR respectively;
In above-mentioned a plurality of NAND, the lead-out terminal of the NAND of last level is electrically connected with the lead-out terminal that obtains the first inspection output; And
In above-mentioned a plurality of NOR, the lead-out terminal of the NOR of last level is electrically connected with the lead-out terminal that obtains the second inspection output.
3. the check circuit of semiconductor device as claimed in claim 1 is characterized in that:
Above-mentioned check circuit also has a plurality of NOR, a plurality of phase inverter and comparator circuit;
The lead-out terminal of the NAND of above-mentioned i-1 level, sub an electrical connection of the first input end with the NAND of above-mentioned i level among above-mentioned a plurality of phase inverters;
The lead-out terminal of the NOR of i-1 level, another among above-mentioned a plurality of phase inverters is electrically connected with first input end of the NOR of i level;
Above-mentioned a plurality of signal wire is electrically connected with second input terminal of above-mentioned a plurality of NAND and second input terminal of above-mentioned a plurality of NOR respectively;
In above-mentioned a plurality of NAND, the lead-out terminal of the NAND of last level is electrically connected with first input end of above-mentioned comparator circuit by another phase inverter among above-mentioned a plurality of phase inverters;
In above-mentioned a plurality of NOR, the lead-out terminal of the NOR of last level is electrically connected with second input terminal of above-mentioned comparator circuit by another phase inverter among above-mentioned a plurality of phase inverters; And
The lead-out terminal of above-mentioned comparator circuit is electrically connected with the lead-out terminal of above-mentioned check circuit.
4. the check circuit of semiconductor device as claimed in claim 3 is characterized in that:
In above-mentioned comparator circuit, use ExNOR.
5. the check circuit of a semiconductor device is characterized in that comprising:
A plurality of signal wires;
A plurality of NAND; And
Be electrically connected to the lead-out terminal of above-mentioned check circuit of the lead-out terminal of above-mentioned a plurality of NAND,
The lead-out terminal of the NAND of above-mentioned i-1 level is electrically connected to first input end of the NAND of i level, and i is the integer more than or equal to 2;
Second input terminal of the NAND of above-mentioned i-1 level and i level is connected respectively to the signal wire of i-1 level and i level; And
By the output pattern that relatively obtains from the lead-out terminal of above-mentioned check circuit with reference to figure, carry out the whether judgement of regular event of above-mentioned semiconductor device.
6. the check circuit of semiconductor device as claimed in claim 5 is characterized in that:
Above-mentioned check circuit also has a plurality of NOR and a plurality of phase inverter;
The lead-out terminal of the NAND of above-mentioned i-1 level, sub an electrical connection of the first input end with the NAND of above-mentioned i level among above-mentioned a plurality of phase inverters;
The lead-out terminal of the NOR of i-1 level, another among above-mentioned a plurality of phase inverters is electrically connected with first input end of the NOR of i level;
Above-mentioned a plurality of signal wire is electrically connected with second input terminal of above-mentioned a plurality of NAND and second input terminal of above-mentioned a plurality of NOR respectively;
In above-mentioned a plurality of NAND, the lead-out terminal of the NAND of last level is electrically connected with the lead-out terminal that obtains the first inspection output; And
In above-mentioned a plurality of NOR, the lead-out terminal of the NOR of last level is electrically connected with the lead-out terminal that obtains the second inspection output.
7. the check circuit of semiconductor device as claimed in claim 5 is characterized in that:
Above-mentioned check circuit also has a plurality of NOR, a plurality of phase inverter and comparator circuit;
The lead-out terminal of the NAND of above-mentioned i-1 level, sub an electrical connection of the first input end with the NAND of above-mentioned i level among above-mentioned a plurality of phase inverters;
The lead-out terminal of the NOR of i-1 level, another among above-mentioned a plurality of phase inverters is electrically connected with first input end of the NOR of i level;
Above-mentioned a plurality of signal wire is electrically connected with second input terminal of above-mentioned a plurality of NAND and second input terminal of above-mentioned a plurality of NOR respectively;
In above-mentioned a plurality of NAND, the lead-out terminal of the NAND of last level is electrically connected with first input end of above-mentioned comparator circuit by another phase inverter among above-mentioned a plurality of phase inverters;
In above-mentioned a plurality of NOR, the lead-out terminal of the NOR of last level is electrically connected with second input terminal of above-mentioned comparator circuit by another phase inverter among above-mentioned a plurality of phase inverters; And
The lead-out terminal of above-mentioned comparator circuit is electrically connected with the lead-out terminal of above-mentioned check circuit.
8. the check circuit of semiconductor device as claimed in claim 7 is characterized in that:
In above-mentioned comparator circuit, use ExNOR.
9. semiconductor device is characterized in that comprising:
The multiple source signals line;
Source drive, input clock signal, initial pulse and signal of video signal, and export a plurality of signals to above-mentioned a plurality of signal wires according to above-mentioned clock signal, above-mentioned initial pulse and above-mentioned signal of video signal; And
Check circuit, this check circuit have a plurality of NAND, a plurality of NOR and the lead-out terminal of the above-mentioned check circuit that is electrically connected with the lead-out terminal of above-mentioned a plurality of NAND and above-mentioned a plurality of NOR;
The lead-out terminal of the NAND of i-1 level is electrically connected with the first input end of the NAND of i level, and i is the integer more than or equal to 2;
The lead-out terminal of the NOR of i-1 level is electrically connected with the first input end of the NOR of i level;
Above-mentioned a plurality of signal wire is electrically connected with second input terminal of above-mentioned a plurality of NAND and second input terminal of above-mentioned a plurality of NOR; And
By the output pattern that relatively obtains from the lead-out terminal of above-mentioned check circuit with reference to figure, carry out the whether judgement of regular event of above-mentioned semiconductor device.
10. semiconductor device as claimed in claim 9 is characterized in that:
Above-mentioned check circuit also has a plurality of phase inverters and comparator circuit;
The lead-out terminal of the NAND of above-mentioned i-1 level, sub an electrical connection of the first input end with the NAND of above-mentioned i level among above-mentioned a plurality of phase inverters;
The lead-out terminal of the NOR of above-mentioned i-1 level, another among above-mentioned a plurality of phase inverters is electrically connected with first input end of the NOR of above-mentioned i level;
In above-mentioned a plurality of NAND, the lead-out terminal of the NAND of last level is electrically connected with first input end of above-mentioned comparator circuit by another phase inverter among above-mentioned a plurality of phase inverters;
In above-mentioned a plurality of NOR, the lead-out terminal of the NOR of last level is electrically connected with second input terminal of above-mentioned comparator circuit by another phase inverter among above-mentioned a plurality of phase inverters; And
The lead-out terminal of above-mentioned comparator circuit is electrically connected with the lead-out terminal of above-mentioned check circuit.
11. semiconductor device as claimed in claim 10 is characterized in that:
In above-mentioned comparator circuit, use ExNOR.
12. a semiconductor device is characterized in that comprising:
A plurality of gate signal lines;
Gate driver is imported clock signal and initial pulse, according to above-mentioned clock signal and above-mentioned initial pulse, exports strobe pulse in proper order to above-mentioned a plurality of gate signal lines;
Check circuit has: check lead-out terminal according to above-mentioned strobe pulse with a plurality of latch cicuits, decision circuit and the above-mentioned check circuit of the sampling of signal,
Above-mentioned decision circuit has: a plurality of NAND and a plurality of NOR;
The lead-out terminal of the NAND of i-1 level is electrically connected with the first input end of the NAND of i level, and i is the integer more than or equal to 2;
The lead-out terminal of the NOR of i-1 level is electrically connected with the first input end of the NOR of i level;
A plurality of signal wires are electrically connected with second input terminal of above-mentioned a plurality of NAND and second input terminal of above-mentioned a plurality of NOR respectively; And
By the output pattern that relatively obtains from the lead-out terminal of above-mentioned check circuit with reference to figure, carry out the whether judgement of regular event of above-mentioned semiconductor device.
13. semiconductor device as claimed in claim 12 is characterized in that:
Above-mentioned check circuit also has a plurality of phase inverters and comparator circuit;
The lead-out terminal of the NAND of above-mentioned i-1 level, sub an electrical connection of the first input end with the NAND of above-mentioned i level among above-mentioned a plurality of phase inverters;
The lead-out terminal of the NOR of above-mentioned i-1 level, another among above-mentioned a plurality of phase inverters is electrically connected with first input end of the NOR of above-mentioned i level;
In above-mentioned a plurality of NAND, the lead-out terminal of the NAND of last level is electrically connected with first input end of above-mentioned comparator circuit by another phase inverter among above-mentioned a plurality of phase inverters;
In above-mentioned a plurality of NOR, the lead-out terminal of the NOR of last level is electrically connected with second input terminal of above-mentioned comparator circuit by another phase inverter among above-mentioned a plurality of phase inverters; And
The lead-out terminal of above-mentioned comparator circuit is electrically connected with the lead-out terminal of above-mentioned check circuit.
14. semiconductor device as claimed in claim 13 is characterized in that:
In above-mentioned comparator circuit, use ExNOR.
15. the check circuit of a semiconductor device is characterized in that:
Have a plurality of signal wires, a plurality of NAND, a plurality of NOR and a plurality of phase inverter;
In above-mentioned a plurality of NAND, the lead-out terminal of the NAND of i-1 level, sub an electrical connection of the first input end with the NAND of i level among above-mentioned a plurality of phase inverters, i is the integer more than or equal to 2;
In above-mentioned a plurality of NOR, the lead-out terminal of the NOR of i-1 level, another among above-mentioned a plurality of phase inverters is electrically connected with first input end of the NOR of i level;
Above-mentioned a plurality of signal wire is electrically connected with second input terminal of above-mentioned a plurality of NAND and second input terminal of above-mentioned a plurality of NOR respectively;
In above-mentioned a plurality of NAND, the lead-out terminal of the NAND of last level is electrically connected with the lead-out terminal that obtains the first inspection output; And
In above-mentioned a plurality of NOR, the lead-out terminal of the NOR of last level is electrically connected with the lead-out terminal that obtains the second inspection output.
16. the check circuit of a semiconductor device is characterized in that:
Have a plurality of signal wires, a plurality of NAND, a plurality of NOR, a plurality of phase inverter and comparator circuit;
In above-mentioned a plurality of NAND, the lead-out terminal of the NAND of i-1 level, sub an electrical connection of the first input end with the NAND of i level among above-mentioned a plurality of phase inverters, i is the integer more than or equal to 2;
In above-mentioned a plurality of NOR, the lead-out terminal of the NOR of i-1 level, another among above-mentioned a plurality of phase inverters is electrically connected with first input end of the NOR of i level;
Above-mentioned a plurality of signal wire is electrically connected with second input terminal of above-mentioned a plurality of NAND and second input terminal of above-mentioned a plurality of NOR respectively;
In above-mentioned a plurality of NAND, the lead-out terminal of the NAND of last level is electrically connected with first input end of above-mentioned comparator circuit by another phase inverter among above-mentioned a plurality of phase inverters;
In above-mentioned a plurality of NOR, the lead-out terminal of the NOR of last level is electrically connected with second input terminal of above-mentioned comparator circuit by another phase inverter among above-mentioned a plurality of phase inverters; And
The lead-out terminal of above-mentioned comparator circuit is electrically connected with the lead-out terminal of the above-mentioned check circuit that obtains checking output.
17. the check circuit of semiconductor device as claimed in claim 16 is characterized in that:
In above-mentioned comparator circuit, use ExNOR.
18. the inspection method of a semiconductor device may further comprise the steps:
Signal is input to second input terminal that each is included in a plurality of NAND in the check circuit simultaneously, and wherein, the output of the NAND of i-1 level is imported into first input end of i level NAND, and i is the integer more than or equal to 2;
Obtain output pattern from above-mentioned check circuit; And
By more above-mentioned output pattern with reference to figure, carry out the judgement of the good or fault of the action of above-mentioned semiconductor device.
19. the inspection method of a semiconductor device may further comprise the steps:
According to the signal of exporting in proper order from a plurality of output signal lines, take a sample with signal sequence to checking;
Each above-mentioned sampled signal is input to second input terminal that each is comprised in a plurality of NAND in the check circuit simultaneously, and wherein, the output of the NAND of i-1 level is imported into first input end of i level NAND, and i is the integer more than or equal to 2;
Obtain output pattern from above-mentioned check circuit; And
By more above-mentioned output pattern with reference to figure, carry out the judgement of the good or fault of the action of above-mentioned semiconductor device.
20. a semiconductor device is characterized in that comprising:
Shift register; And
Check circuit, this check circuit has: a plurality of signal wires, a plurality of NAND and be electrically connected to the lead-out terminal of above-mentioned check circuit of the lead-out terminal of above-mentioned a plurality of NAND,
The lead-out terminal of i-1 level NAND is electrically connected to first input end of i level NAND, and i is the integer more than or equal to 2;
Second input terminal of the NAND of above-mentioned i-1 level, i level and i+1 level is connected respectively to i-1 level, i level and i+1 level signal wire;
Above-mentioned a plurality of signal wire is electrically connected to above-mentioned shift register; And
Based at least one signal that on the lead-out terminal of above-mentioned check circuit, obtains, carry out the whether judgement of regular event of above-mentioned semiconductor device.
21. semiconductor device as claimed in claim 20 is characterized in that:
Above-mentioned check circuit also comprises: a plurality of NOR and a plurality of phase inverter,
The lead-out terminal of the NAND of above-mentioned i-1 level, sub an electrical connection of the first input end with the NAND of above-mentioned i level among above-mentioned a plurality of phase inverters;
The lead-out terminal of the NOR of i-1 level, another among above-mentioned a plurality of phase inverters is electrically connected with first input end of the NOR of i level;
Above-mentioned a plurality of signal wire is electrically connected with second input terminal of above-mentioned a plurality of NAND and second input terminal of above-mentioned a plurality of NOR respectively;
In above-mentioned a plurality of NAND, the lead-out terminal of the NAND of last level is electrically connected with the lead-out terminal that obtains the first inspection output; And
In above-mentioned a plurality of NOR, the lead-out terminal of the NOR of last level is electrically connected with the lead-out terminal that obtains the second inspection output.
22. semiconductor device as claimed in claim 20 is characterized in that:
Above-mentioned check circuit also comprises: a plurality of NOR, a plurality of phase inverter and comparator circuit,
The lead-out terminal of the NAND of above-mentioned i-1 level, sub an electrical connection of the first input end with the NAND of above-mentioned i level among above-mentioned a plurality of phase inverters;
The lead-out terminal of the NOR of i-1 level, another among above-mentioned a plurality of phase inverters is electrically connected with first input end of the NOR of i level;
Above-mentioned a plurality of signal wire is electrically connected with second input terminal of above-mentioned a plurality of NAND and second input terminal of above-mentioned a plurality of NOR respectively;
In above-mentioned a plurality of NAND, the lead-out terminal of the NAND of last level is electrically connected with first input end of above-mentioned comparator circuit by another phase inverter among above-mentioned a plurality of phase inverters;
In above-mentioned a plurality of NOR, the lead-out terminal of the NOR of last level is electrically connected with second input terminal of above-mentioned comparator circuit by another phase inverter among above-mentioned a plurality of phase inverters; And
The lead-out terminal of above-mentioned comparator circuit is electrically connected with the lead-out terminal of above-mentioned check circuit.
23. semiconductor device as claimed in claim 20 is characterized in that:
In above-mentioned comparator circuit, use ExNOR.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003081666 | 2003-03-25 | ||
| JP081666/2003 | 2003-03-25 | ||
| JP137822/2003 | 2003-05-15 |
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| CN100526902C true CN100526902C (en) | 2009-08-12 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1149167A (en) * | 1995-08-29 | 1997-05-07 | 信越聚合物株式会社 | Liquid crystal display panel inspection device and method for manufacturing same |
| CN1282108A (en) * | 1999-07-23 | 2001-01-31 | 精工爱普生株式会社 | Semiconductor integrated circuit and checking method, crystal device and electronic device |
| CN1383489A (en) * | 2000-07-05 | 2002-12-04 | Oht株式会社 | Inspection appts. and inspection method |
| CN1391132A (en) * | 2001-06-13 | 2003-01-15 | 精工爱普生株式会社 | Substrate devices, its test methods, photoelectric devices and manufacturing methods thereof |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1149167A (en) * | 1995-08-29 | 1997-05-07 | 信越聚合物株式会社 | Liquid crystal display panel inspection device and method for manufacturing same |
| CN1282108A (en) * | 1999-07-23 | 2001-01-31 | 精工爱普生株式会社 | Semiconductor integrated circuit and checking method, crystal device and electronic device |
| CN1383489A (en) * | 2000-07-05 | 2002-12-04 | Oht株式会社 | Inspection appts. and inspection method |
| CN1391132A (en) * | 2001-06-13 | 2003-01-15 | 精工爱普生株式会社 | Substrate devices, its test methods, photoelectric devices and manufacturing methods thereof |
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