CN100495178C - Thin-film transistor LCD array substrate pixel structure and manufacturing method thereof - Google Patents
Thin-film transistor LCD array substrate pixel structure and manufacturing method thereof Download PDFInfo
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- CN100495178C CN100495178C CNB2006100992318A CN200610099231A CN100495178C CN 100495178 C CN100495178 C CN 100495178C CN B2006100992318 A CNB2006100992318 A CN B2006100992318A CN 200610099231 A CN200610099231 A CN 200610099231A CN 100495178 C CN100495178 C CN 100495178C
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Abstract
The invention discloses a pixel structure for an array base board of a film transistor LCD, which comprises a base board, a grid line, a grid electrode, a grid insulation layer, a semi-conductor layer, an Ohm contact layer, a pixel electrode, a source electrode, a drain electrode and data lines. wherein, at the lower part of the grid electrode, a transparent electro-conductive film of same material with the pixel electrode is reserved; the grid line is located between data lines in a discontinuous way; one end of the grid electrode is the jumping part of the grid line; the two ends of the jumping part of the grid line are provided with through holes for grid metallic film to emerge; the discontinuous grid line is electrically connected with the grid electrode and grid line through the through holes; the grid line is of same material with the source electrode, the drain electrode and the data lines. The invention additionally discloses a manufacturing method for the pixel structure for the array base board of the film transistor LCD. The invention reduces the photoetching process and process procedures for the pixel structure, reduces the process time, improves the utilization rate of the equipment, hence improves the producing capacity and reduces the cost.
Description
Technical field
The present invention relates to a kind of Thin Film Transistor-LCD (TFT LCD) array substrate pixel structure and manufacture method thereof, relate in particular to TFT LCD array substrate pixel structure and manufacture method thereof that 3 photoetching processes of a kind of usefulness are made.
Background technology
The liquid crystal display that with TFT LCD is representative has had development at full speed as a kind of important flat pannel display mode in nearly ten years, get more and more people's extensive concerning.Because the cut-throat competition between each manufacturer and the continuous progress of TFT LCD manufacturing technology, display quality is good, and the LCD that price is more cheap is constantly introduced to the market.Therefore, adopt advanced more manufacturing technology, simplify production technology, reducing production costs becomes the important assurance that TFT LCD production firm is survived in cut-throat competition.
In the process for manufacturing liquid crystal display, exposure technology must be used mask (mask), because the price of mask is very expensive, so reduce mask exposure frequency in other words, is the effectively way that reduces cost.In the process for manufacturing liquid crystal display, every layer process flow is deposition, exposure, etching and removes photoresist that each step all can not reduce now; So the minimizing single exposure, the exposure in the technology and remove photoresist and can save at least, the expense of buying MASK also can reduce.
The manufacturing technology of TFT LCD array base palte has experienced from 7 photoetching techniques (7Mask), 5 photoetching techniques (5mask) up till now, the evolution of 4 photoetching techniques (4mask).
The present 4MASK technology generally used of institute, exposure frequency is 4 times, must 4 MASK of making; In addition, deposition, etching, processing step such as remove photoresist also are essential.4 exposures simultaneously can cause the deviation ratio between each layer bigger, can reduce yield rate, are undesirable in the manufacturing process.
Summary of the invention
The present invention is in order to overcome the defective of prior art, and at Developing Trend in Technology, a kind of TFT LCD array substrate pixel structure and manufacture method thereof are provided, thereby the photoetching process and the processing step of dot structure have been reduced, reduced the process time, improved usage ratio of equipment, thereby improved production capacity and reduced cost.
To achieve these goals, the invention provides a kind of thin-film transistor LCD array substrate pixel structure, it is characterized in that, comprise a substrate, the cross-over connection position of the pixel electrode that on described substrate, forms, gate electrode, interrupted grid line, the cross-over connection position of described interrupted grid line connects an end of described gate electrode; The gate insulation layer that on the cross-over connection position of described pixel electrode, gate electrode, interrupted grid line and substrate, forms; Active layer that on described gate insulation layer, forms and ohmic contact layer, the described gate insulation layer at the two ends, cross-over connection position of described interrupted grid line is provided with first via hole at the cross-over connection position of exposing interrupted grid line, and the described gate insulation layer of described pixel electrode is provided with second via hole that exposes pixel electrode; The data line that on described gate insulation layer, forms, source electrode, drain electrode and interrupted grid line, wherein said data line connects described source electrode, described interrupted grid line is electrically connected by the cross-over connection position of described first via hole with interrupted grid line, and described pixel electrode is electrically connected with described drain electrode by described second via hole.
Described gate electrode is the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, perhaps the composite membrane that is constituted for AlNd, Al, Cu, Mo, MoW or Cr combination in any.Described gate insulation layer is the monofilm of SiNx, SiOx or SiOxNy, perhaps is the composite membrane that SiNx, SiOx or SiOxNy combination in any are constituted.Described grid line, source electrode, drain electrode or data line are the monofilm of Mo, MoW or Cr, perhaps are the composite membrane that Mo, MoW or Cr combination in any are constituted.
To achieve these goals, the present invention also provides a kind of manufacture method of thin-film transistor LCD array substrate pixel structure simultaneously, comprising:
Step 1, on substrate, deposit layer of transparent conductive film and grid metallic film successively, adopt first gray mask version to carry out mask, exposure and etching, form the cross-over connection position of pixel electrode, gate electrode and interrupted grid line, wherein, pixel electrode is formed by transparent conductive film, and the cross-over connection position of gate electrode and interrupted grid line is to be formed by the grid metallic film that is positioned on the transparent conductive film;
Wherein, first gray tone mask of described employing carried out mask, when the exposure definition forms the complete reserve area of photoresist, photoresist part reserve area and do not have the photoresist zone, made the zone, cross-over connection position of corresponding gate electrode of the complete reserve area of photoresist and interrupted grid line; The corresponding pixel electrode area that forms of photoresist part reserve area; Other parts are no photoresist zone.Second gray tone mask of described employing carried out mask, when the exposure definition forms the complete reserve area of photoresist, photoresist part reserve area and do not have the photoresist zone, made the corresponding active layer subregion that is positioned at the gate electrode top that forms of the complete reserve area of photoresist; The corresponding cross-over connection position via area that forms pixel electrode via hole and interrupted grid line in no photoresist zone; The corresponding photoresist part of other parts reserve area.The 3rd gray tone mask of described employing carried out mask, when the exposure definition forms the complete reserve area of photoresist, photoresist part reserve area and do not have the photoresist zone, made corresponding data line, grid line, source electrode and the drain electrode of forming of the complete reserve area of photoresist; Channel region between corresponding formation source electrode of photoresist part reserve area and the drain electrode; Other parts are no photoresist zone.
The present invention has reduced to 3 to the MASK number, has reduced one with respect to 4 original MASK, has obtained reduction on the cost of development.The main technique step has reduced to 17 simultaneously, and 20 steps relative and 4MASK have also had the minimizing of 3 steps, has shortened the cycle of producing.In addition, because the minimizing of exposure frequency, the error between each exposure has also reduced, and process allowance has also improved, and has improved output and yield rate.
Below in conjunction with Figure of description and specific embodiment, technical scheme of the present invention is described in further detail.
Description of drawings
Fig. 1 has deposited the sectional view of glass substrate behind ITO and the Al for the present invention;
Fig. 2 carries out mask, exposure and etching for the present invention adopts first gray mask version, finishes the pattern that obtains after the photoresist lift off;
Fig. 3 is the sectional view of Fig. 2 A-A;
Fig. 4 has deposited the sectional view of glass substrate behind insulation course, active layer and the ohmic contact layer for the present invention;
Fig. 5 uses second sectional view after the exposure of gray tone mask for the present invention;
Fig. 6 carries out mask, exposure and etching for the present invention adopts second gray mask version, finishes the pattern that obtains after the photoresist lift off;
Fig. 7 is the sectional view of Fig. 6 TFT part B-B;
Fig. 8 is the pattern after the whole dot structure of the present invention is finished;
Fig. 9 is the sectional view of TFT portion C-C after the whole dot structure of the present invention is finished.
Embodiment
Below in conjunction with concrete manufacturing process, one pixel structure process method of the present invention is described.
At first, going up deposition layer of transparent conductive film 2 at substrate 1 (glass etc.), adopt ito thin film in the present embodiment, and then deposit grid metallic film 3 on ito thin film, is Al in the present embodiment, and sectional view as shown in Figure 1.
Then, adopt the gray mask version to carry out mask and exposure, form the photoresist of different-thickness, the photoresist of 31 tops, cross-over connection position that wherein forms gate electrode and grid line is unexposed, is the complete reserve area of photoresist; The photoresist that forms top, pixel electrode 21 positions partly exposes, and is photoresist part reserve area; The photoresist of other part tops exposes fully, is no photoresist zone.Wherein, the complete reserve area of photoresist is thicker than the photoresist thickness of photoresist part reserve area.The first step of etching etches away the grid metallic film below the no photoresist zone, carries out photoresist glue cineration technics then, removes the photoresist of photoresist part reserve area, the photoresist of the complete reserve area of reserve part photoresist.Carry out etching once more, the grid metallic film above the pixel electrode position is etched away, obtain complete pixel electrode.The photoresist of the top, cross-over connection position of last gate electrode and interrupted grid line is peeled off, and obtains the cross-over connection position 31 of gate electrode and interrupted grid line, and the pattern of ground floor just forms like this, and as shown in Figure 2, the sectional view of two parts as shown in Figure 3.
Then, exhausted insulation course 4, active layer 5 and ohmic contact layer 6 of deposition grid on whole base plate, sectional view is as shown in Figure 4.Adopt second gray mask version to carry out mask and exposure, the photoresist that wherein forms top, TFT position is unexposed, is the complete reserve area of photoresist; The photoresist of cross-over connection position via hole 9 parts of pixel electrode via hole and interrupted grid line exposes fully, is no photoresist zone; Other part photoresists partly expose, and are photoresist part reserve area, as shown in Figure 5.Wherein, the thickness of photoresist 8 is different, and the complete reserve area of photoresist is thicker than the photoresist thickness of photoresist part reserve area.The first step of etching, cross-over connection position via hole 9 parts with pixel electrode via hole and interrupted grid line, the ohmic contact layer and the active layer that promptly do not have below, photoresist zone etch away, carry out photoresist glue cineration technics then, remove the photoresist of photoresist part reserve area, the photoresist of the complete reserve area of reserve part photoresist.Second step of etching, ohmic contact layer and active layer are carried out etching, because the ohmic contact layer and the active layer of cross-over connection position via hole 9 parts of pixel electrode via hole and interrupted grid line etch away in first step etching, so its below insulation course will be etched away, and exposes the grid metallic film in the via hole.At last, remove remaining photoresist, expose the TFT part.Figure after finishing as shown in Figure 6, the sectional view of TFT part is as shown in Figure 7.
At last, deposition layer of metal film on whole base plate.Adopt the 3rd gray mask version to carry out mask and exposure, the photoresist that wherein forms data line, grid line, source electrode and drain electrode is unexposed, is the complete reserve area of photoresist; The photoresist of TFT channel part partly exposes, and is photoresist part reserve area; The photoresist of other part tops exposes fully, is no photoresist zone.The first step of etching, at first remove the metallic film in no photoresist zone, carry out photoresist glue cineration technics then, remove the photoresist of photoresist part reserve area, be the photoresist on TFT channel part top, the photoresist of the complete reserve area of reserve part photoresist.In second step of etching, TFT channel part ohmic contact layer is etched away.At last the photoresist on data line, grid line, source electrode and drain electrode top is got rid of, finished the making of array substrate pixel structure, as shown in Figure 8; The sectional view of TFT part as shown in Figure 9.
As Fig. 8 and shown in Figure 9, a kind of thin-film transistor LCD array substrate pixel structure of the present invention, comprise substrate 1, be formed on the cross-over connection position 31 of pixel electrode 21, gate electrode and grid line on the substrate, the cross-over connection position 31 of gate electrode and grid line mainly is made of grid metallic film 3,31 bottoms, cross-over connection position of gate electrode and grid line remain with the transparent conductive film 2 identical with the pixel electrode material simultaneously, the gate insulation layer 4, semiconductor layer 5, the ohmic contact layer 6 that form on the gate electrode constitute TFT part 10, and grid line is interrupted shape and is distributed between the data line; There is the via hole (being labeled as 9 jointly with the via hole on the pixel electrode) that exposes the grid metallic film at the two ends, cross-over connection position of grid line, and interrupted grid line is by being electrically connected between this via hole realization and gate electrode and grid line; Grid line and source electrode, drain electrode, and the material identical (mark 7 among the figure) of data line, drain electrode links to each other with pixel electrode by the via hole on the pixel electrode.Dot structure gate electrode of the present invention can be the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, also can be one of AlNd, Al, Cu, Mo, MoW or Cr or composite membrane that combination in any constituted.Gate insulation layer can be the monofilm of SiNx, SiOx or SiOxNy, also can be one of SiNx, SiOx or SiOxNy or composite membrane that combination in any constituted.Source-drain electrode, data line and grid line can be the monofilm of Mo, MoW or Cr, also can be one of Mo, MoW or Cr or composite membrane that combination in any constituted.
It should be noted that at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art should can use different materials and equipment to realize it as required, promptly can make amendment or be equal to replacement, and not break away from the spirit and scope of technical solution of the present invention technical scheme of the present invention.
Claims (8)
1, a kind of thin-film transistor LCD array substrate pixel structure, it is characterized in that, comprise a substrate, the cross-over connection position of the pixel electrode that on described substrate, forms, gate electrode, interrupted grid line, the cross-over connection position of described interrupted grid line connects an end of described gate electrode; The gate insulation layer that on the cross-over connection position of described pixel electrode, gate electrode, interrupted grid line and substrate, forms; Active layer that on described gate insulation layer, forms and ohmic contact layer, the described gate insulation layer at the two ends, cross-over connection position of described interrupted grid line is provided with first via hole at the cross-over connection position of exposing interrupted grid line, and the described gate insulation layer of described pixel electrode is provided with second via hole that exposes pixel electrode; The data line that on described gate insulation layer, forms, source electrode, drain electrode and interrupted grid line, wherein said data line connects described source electrode, described interrupted grid line is electrically connected by the cross-over connection position of described first via hole with interrupted grid line, and described pixel electrode is electrically connected with described drain electrode by described second via hole.
2, dot structure according to claim 1 is characterized in that: described gate electrode is the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, perhaps the composite membrane that is constituted for AlNd, Al, Cu, Mo, MoW or Cr combination in any.
3, array base-plate structure according to claim 1 is characterized in that: described gate insulation layer is the monofilm of SiNx, SiOx or SiOxNy, perhaps is the composite membrane that SiNx, SiOx or SiOxNy combination in any are constituted.
4, array base-plate structure according to claim 1 is characterized in that: described grid line, source electrode, drain electrode or data line are the monofilm of Mo, MoW or Cr, perhaps are the composite membrane that Mo, MoW or Cr combination in any are constituted.
5, a kind of manufacture method of thin-film transistor LCD array substrate pixel structure is characterized in that, comprising:
Step 1, on substrate, deposit layer of transparent conductive film and grid metallic film successively, adopt first gray mask version to carry out mask, exposure and etching, form the cross-over connection position of pixel electrode, gate electrode and interrupted grid line, wherein, pixel electrode is formed by transparent conductive film, and the cross-over connection position of gate electrode and interrupted grid line is to be formed by the grid metallic film that is positioned on the transparent conductive film;
Step 2, on the substrate of completing steps one, deposit gate insulation layer, active layer and ohmic contact layer, adopt second gray mask version to carry out mask and exposure, form the cross-over connection position via hole of the active layer part, pixel electrode via hole and the interrupted grid line that are positioned at the gate electrode top;
Step 3, deposition layer of metal film adopts the 3rd gray mask version to carry out mask, exposure and etching on the substrate of completing steps two, forms the raceway groove between data line, grid line, source electrode, drain electrode and source electrode and the drain electrode.
6, manufacture method according to claim 5, it is characterized in that: first gray tone mask of described employing carried out mask, when the exposure definition forms the complete reserve area of photoresist, photoresist part reserve area and do not have the photoresist zone, made the zone, cross-over connection position of corresponding gate electrode of the complete reserve area of photoresist and interrupted grid line; The corresponding pixel electrode area that forms of photoresist part reserve area; Other parts are no photoresist zone.
7, manufacture method according to claim 5, it is characterized in that: second gray tone mask of described employing carried out mask, when the exposure definition forms the complete reserve area of photoresist, photoresist part reserve area and do not have the photoresist zone, made the corresponding active layer subregion that is positioned at the gate electrode top that forms of the complete reserve area of photoresist; The corresponding cross-over connection position via area that forms pixel electrode via hole and interrupted grid line in no photoresist zone; The corresponding photoresist part of other parts reserve area.
8, manufacture method according to claim 5, it is characterized in that: the 3rd gray tone mask of described employing carried out mask, when the exposure definition forms the complete reserve area of photoresist, photoresist part reserve area and do not have the photoresist zone, made corresponding data line, grid line, source electrode and the drain electrode of forming of the complete reserve area of photoresist; Channel region between corresponding formation source electrode of photoresist part reserve area and the drain electrode; Other parts are no photoresist zone.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006100992318A CN100495178C (en) | 2006-07-21 | 2006-07-21 | Thin-film transistor LCD array substrate pixel structure and manufacturing method thereof |
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| CNB2006100992318A CN100495178C (en) | 2006-07-21 | 2006-07-21 | Thin-film transistor LCD array substrate pixel structure and manufacturing method thereof |
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| CN101109876A CN101109876A (en) | 2008-01-23 |
| CN100495178C true CN100495178C (en) | 2009-06-03 |
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| CN102446925B (en) * | 2010-09-30 | 2015-05-20 | 京东方科技集团股份有限公司 | Array base plate, liquid crystal display and manufacturing method for array base plate |
| CN102637637B (en) * | 2012-04-28 | 2014-03-26 | 深圳市华星光电技术有限公司 | Array substrate of thin film transistor and manufacturing method thereof |
| CN103560110B (en) | 2013-11-22 | 2016-02-17 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display unit |
| CN114388596A (en) | 2020-10-19 | 2022-04-22 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display device |
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