CN106057736B - Preparation method of TFT substrate and TFT substrate - Google Patents

Abstract

The invention discloses a preparation method of a TFT substrate and the TFT substrate. The TFT substrate includes a plurality of pixel units, and each pixel unit includes a gate metal layer, a gate insulating layer, a semiconductor layer, a source/drain metal layer, an insulating medium layer, and a pixel electrode layer sequentially formed on a transparent substrate, and the data line and the gate The electrodes and the gate lines are arranged on the same layer, and the data lines and the source electrodes are connected through the first via hole and the second via hole of the insulating medium layer and the first connection line of the pixel electrode layer. The preparation method of the TFT substrate reduces 2 times of photolithography on the basis of the original 5 times of photolithography, simplifies the TFT preparation process, reduces production costs and improves production efficiency. The fewer process steps, the higher the product yield and the easier the quality control .

Description

A kind of preparation method of TFT substrate and TFT substrate

technical field

The invention relates to the field of liquid crystal display, in particular to a preparation method of a TFT substrate and the TFT substrate.

Background technique

With the development of smart phones, tablet computers and other products, TFT-LCD liquid crystal displays are more and more widely used. With the competition in the industry, cost-effective TFT-LCD screens are constantly being pushed into the market, and the use of more advanced technology, optimization and simplification of the process, and reduction of production costs have become a strong guarantee for survival in the fiercely competitive market.

The TFT-LCD industry mainly uses 5-pass lithography technology to produce TFTs, while some manufacturers use 4-pass lithography technology. However, the 5-pass photolithography and 4-pass photolithography technologies currently used in the production of TFTs still have problems such as complex process technology.

In an invention patent with the notification number CN 102023432B, an FFS-type TFT-LCD array substrate and its preparation method are disclosed. The resist is exposed and developed, and there is a residual semiconductor layer on the gate line, which is likely to cause a large storage capacitance, affect the structural stability, and lead to defective products; an invention patent with the announcement number CN 102315130B discloses a A kind of thin film field effect transistor and its preparation method, its preparation method can be finished by carrying out 3 photolithography, but the high temperature photoresist cost that it uses is higher than conventional photoresist, and TFT glass substrate is not resistant to high temperature, is not conducive to Cost reduction and product yield improvement.

Contents of the invention

In order to solve the above-mentioned deficiencies in the prior art, the present invention provides a method for preparing a TFT substrate and a TFT substrate thereof. The TFT substrate arranges the data line, the gate electrode, and the gate line on the same layer, and connects the data line and the source electrode through the first via hole and the second via hole of the insulating medium layer and the first connection line of the pixel electrode layer, and its preparation method On the basis of the original 5 photolithography process, 2 photolithography processes are reduced, the TFT preparation process is simplified, the production cost is reduced, and the production efficiency is improved. The fewer process steps, the higher the product yield and the easier the quality control.

The technical problem to be solved by the present invention is realized through the following technical solutions:

A preparation method for a TFT substrate, comprising the steps of:

S1: sequentially depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source/drain metal layer on a transparent substrate;

S2: Coating a first photoresist on the source/drain metal layer, performing masking and etching to form data lines, gate lines, gate electrodes, gate insulating layers, semiconductor channels, source electrodes and drain electrodes;

S3: depositing an insulating dielectric layer on the substrate described in S2;

S4: Coating a second photoresist on the insulating dielectric layer, performing masking and etching, and forming the first via hole and the second via hole of the insulating dielectric layer respectively located above the data line, the source electrode and the drain electrode and the third via;

S5: Depositing a pixel electrode layer on the substrate described in S4;

S6: Coating a third photoresist on the pixel electrode layer, performing masking and etching to form a pixel electrode, a first connection line between a data line and a source electrode, and a second connection line between a drain electrode and a pixel electrode.

Further, before the step S1, a step S0 is also included: providing a transparent substrate, cleaning the transparent substrate, and removing dirt on the transparent substrate.

Further, the step S2 includes:

S21: Perform a grayscale masking process on the first photoresist to form a first photoresist pattern, wherein the first photoresist in the source electrode region and the drain electrode region has a first thickness, and the gate line region, data The first photoresist in the line region and the semiconductor channel region has a second thickness, and the other regions are not covered by the first photoresist, and the first thickness is greater than the second thickness;

S22: removing the source/drain metal layer, semiconductor layer and gate insulating layer in the other regions not covered by the first photoresist through an etching process to form data lines, gate lines, gate electrodes and gate insulating layers;

S23: Perform an ashing process on the first photoresist, remove the second thickness of the first photoresist, and expose the gate line region, the data line region and the source/drain metal layer of the semiconductor channel region;

S24: Etching the exposed source/drain metal layer and the underlying semiconductor layer through an etching process to form a semiconductor channel, source electrode and drain electrode;

S25: Stripping the first photoresist, and stripping the remaining first photoresist.

Further, said S4 includes:

S41: Perform a grayscale masking process on the second photoresist to form a second photoresist pattern, wherein the second photoresist in the source electrode region, the drain electrode region, and the gate line region has a third thickness, and the data The line area is not covered by the second photoresist, and the second photoresist in other areas has a fourth thickness, and the fourth thickness is greater than the third thickness;

S42: removing the insulating dielectric layer in the data line region not covered by the second photoresist through an etching process, exposing the gate insulating layer and the semiconductor layer in the data line region;

S43: Perform an ashing process on the second photoresist, remove the photoresist with a third thickness, and expose the insulating dielectric layer in the source electrode region, the drain electrode region and the gate line region;

S44: Remove the gate insulating layer and semiconductor layer in the data line region, the insulating dielectric layer on the source/drain electrode region, the semiconductor layer and insulating dielectric layer on the gate line region, and the gate insulating layer on the data line region through an etching process and a semiconductor layer, forming a first via hole, a second via hole, and a third via hole in the insulating dielectric layer above the data line, the source electrode, and the drain electrode;

S45: Stripping the second photoresist, and stripping the remaining second photoresist.

Further, said S6 includes:

S61: Perform a grayscale masking process on the third photoresist to form a third photoresist pattern, wherein the semiconductor channel region and the gate line region are not covered by the third photoresist;

S62: Through an etching process, remove the pixel electrode layer in the semiconductor channel region and the gate line region not covered by the third photoresist, and form the pixel electrode, the first connection line of the data line and the source electrode, the drain electrode and the pixel electrode the second connection line;

S63: Stripping the third photoresist, and stripping the remaining third photoresist.

Further, when a grayscale mask is used for masking in step S21, the data line region, the gate line region and the semiconductor channel region correspond to part of the light-transmitting parts of the mask, and the source electrode region and the drain electrode region correspond to the mask The opaque parts of the mask, and other areas correspond to the completely transparent parts of the mask.

Further, when a gray scale mask is used for masking in step S41, the data line region corresponds to the completely transparent part of the mask, and the source electrode region, the drain electrode region and the gate line region correspond to the partially transparent part of the mask , and the other areas correspond to the opaque parts of the mask.

A TFT substrate comprising a plurality of pixel units, each pixel unit comprising a gate metal layer, a gate insulating layer, a semiconductor layer, a source/drain metal layer, an insulating dielectric layer and a pixel electrode layer sequentially formed on a transparent substrate, wherein:

The gate metal layer includes a gate electrode, a horizontal gate line and a vertical data line, the gate electrode is connected to the gate line, and the data line is disconnected from the gate electrode and the gate line;

The gate insulating layer is located on the gate electrode and the gate line, and is used to insulate the gate line/gate electrode from the source electrode/drain electrode;

The semiconductor layer is located on the gate insulating layer of the gate electrode, on which a semiconductor channel is formed;

The source/drain metal layer includes a source electrode and a drain electrode, respectively located on both sides of the semiconductor channel of the semiconductor layer;

The insulating medium layer is used to insulate the semiconductor layer, the gate electrode and the pixel electrode layer, and the data line is provided with a first via hole, the source electrode is provided with a second via hole, and the drain electrode is provided with a third via hole;

The pixel electrode layer includes a pixel electrode, a first connection line, and a second connection line.

Further, the source electrode is connected to the data line through the first via hole on the insulating medium layer, the second via hole and the first connection line on the pixel electrode layer, and the drain electrode is connected to the data line through the third via hole on the insulating medium layer. The hole and the second connection line on the pixel electrode layer are connected to the pixel electrode.

The present invention has following beneficial effects:

1. The TFT substrate sets the data line, the gate electrode, and the gate line on the same layer, and connects the data line and the source electrode through the first via hole and the second via hole of the insulating medium layer and the first connection line of the pixel electrode layer. The preparation method reduces the number of photolithography by 2 times on the basis of the original 5-time photolithography process, simplifies the TFT preparation process, reduces production costs, and improves production efficiency. The fewer process steps, the higher the yield rate of the product, and the easier it is to control the quality;

2. The photoresist is masked and etched with a gray-scale mask, which is more operable and will not leave a semiconductor layer on the gate line, which will affect the structural stability and the product yield is high;

3. The photoresist is a conventional photoresist with low production cost. The photoresist can be etched and stripped at normal temperature without causing damage to the TFT glass substrate, and the yield rate of its products is higher.

Description of drawings

Fig. 1 is the schematic diagram of the TFT substrate provided by the present invention;

Fig. 2 is the A-A sectional view of the TFT substrate shown in Fig. 1;

Fig. 3 is the B-B sectional view of TFT substrate shown in Fig. 1;

4 is a cross-sectional view after forming a gate metal layer, a gate insulating layer, a semiconductor layer, and a source/drain metal layer on a transparent substrate;

5a-5b are cross-sectional views after the first photoresist is coated on the structure of FIG. 4 and the first photoresist is subjected to a grayscale masking process;

6a-6b are cross-sectional views of the structure of FIGS. 5a-5b after an etching process;

7a-7b are cross-sectional views of the first photoresist in FIGS. 6a-6b after an ashing process;

8a-8b are cross-sectional views of the structure of FIGS. 6a-6b after an etching process;

Figures 9a-9b are cross-sectional views after stripping the first photoresist in Figures 8a-8b;

Figures 10a-10b are cross-sectional views of the structure of Figures 9a-9b after forming an insulating dielectric layer;

Figures 11a-11b are cross-sectional views after applying a second photoresist to the structure of Figures 10a-10b, and then performing a grayscale masking process on the second photoresist;

12a-12b are cross-sectional views of the structure of FIGS. 11a-11b after an etching process;

13a-13b are cross-sectional views of the second photoresist in FIGS. 12a-12b after the ashing process;

14a-14b are cross-sectional views of the structure of FIGS. 13a-13b after an etching process;

Figures 15a-15b are cross-sectional views after stripping the second photoresist in Figures 14a-14b;

16a-16b are cross-sectional views of the structure of FIGS. 15a-15b after forming a pixel capacitance layer;

Figures 17a-17b are cross-sectional views of the third optical glue after the third optical glue is applied to the structure of Figures 16a-16b, and the gray scale masking process is performed on the third optical glue;

Figures 18a-18b are cross-sectional views of the structure of Figures 17a-17b after an etching process;

19a-19b are cross-sectional views of the third photoresist in FIGS. 18a-18b after stripping.

detailed description

The present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

Example 1

As shown in Figure 4-19b, a method for preparing a TFT substrate includes the following steps:

S1: Depositing a gate metal layer 2 , a gate insulating layer 3 , a semiconductor layer 5 and a source/drain metal layer 5 on a transparent substrate 1 in sequence.

The material of the gate metal layer 2 and the source/drain metal layer 5 in this step is preferably but not limited to Al, Cu, Mo or Cr, etc., and the material of the gate insulating layer 3 is preferably but not limited to silicon nitride, silicon oxide or nitrogen Silicon oxide or the like, the material of the semiconductor layer 5 is preferably but not limited to single crystal silicon, polycrystalline silicon, or amorphous silicon.

S2: Coating the first photoresist 8 on the source/drain metal layer 5, performing masking and etching to form the data line 22, the gate line 23, the gate electrode 21, the gate insulating layer 3, and the semiconductor channel 41 , source electrode 52 and drain electrode 51.

Wherein, the step S2 includes:

S21: Perform a grayscale masking process on the first photoresist 8 to form a pattern of the first photoresist 8, wherein the first photoresist 8 in the region of the source electrode 52 and the region of the drain electrode 51 has a first thickness, The first photoresist 8 in the area of the gate line 23, the area of the data line 22 and the area of the semiconductor channel 41 has a second thickness, and other areas are not covered by the first photoresist 8, and the first thickness is greater than the second thickness;

S22: remove the source/drain metal layer 5, semiconductor layer 5 and gate insulating layer 3 in the other regions not covered by the first photoresist 8 through an etching process, to form data lines 22, gate lines 23, and gate electrodes 21 and a gate insulating layer 3;

S23: Perform an ashing process on the first photoresist 8, remove the second thickness of the first photoresist 8, and expose the source/drain metal in the area of the gate line 23, the area of the data line 22, and the area of the semiconductor channel 41 layer 5;

S24: Etching the exposed source/drain metal layer 5 and the underlying semiconductor layer 5 through an etching process to form a semiconductor channel 41, a source electrode 52 and a drain electrode 51;

S25: Stripping the first photoresist 8, and peeling off the remaining first photoresist 8.

S3: Depositing an insulating dielectric layer 6 on the substrate described in S2.

The dielectric insulating layer in this step is preferably but not limited to silicon nitride, silicon oxide or silicon oxynitride.

S4: Coating the second photoresist 9 on the insulating medium layer 6, performing masking and etching, forming the first pass of the insulating medium layer 6 respectively located above the data line 22, the source electrode 52 and the drain electrode 51 hole 61 , second via hole 62 and third via hole 63 .

Wherein, said S4 includes:

S41: Perform a grayscale masking process on the second photoresist 9 to form a pattern of the second photoresist 9, wherein the second photoresist 9 in the region of the source electrode 52, the region of the drain electrode 51, and the region of the gate line 23 It has a third thickness, the area of the data line 22 is not covered by the second photoresist 9, and the second photoresist 9 in other areas has a fourth thickness, and the fourth thickness is greater than the third thickness;

S42: removing the insulating dielectric layer 6 in the area of the data line 22 not covered by the second photoresist 9 through an etching process, exposing the gate insulating layer 3 and the semiconductor layer 5 in the area of the data line 22;

S43: Perform an ashing process on the second photoresist 9, remove the photoresist with a third thickness, and expose the insulating dielectric layer 6 in the region of the source electrode 52, the region of the drain electrode 51, and the region of the gate line 23;

S44: remove the gate insulating layer 3 and the semiconductor layer 5 in the region of the data line 22, the insulating dielectric layer 6 in the region of the source/drain electrode 51, the semiconductor layer 5 and the insulating dielectric layer 6 in the region of the gate line 23 through an etching process, The gate insulating layer 3 and the semiconductor layer 5 on the data line 22 area form the first via hole 61, the second via hole 62 and the third via hole 6 of the insulating dielectric layer 6 above the data line 22, the source electrode 52 and the drain electrode 51 respectively. Via 63;

S45: Stripping the second photoresist 9, and peeling off the remaining second photoresist 9.

S5: Depositing the pixel electrode layer 7 on the substrate described in S4.

The material of the pixel electrode layer 7 in this step is preferably but not limited to ITO.

S6: coating the third photoresist 10 on the pixel electrode layer 7, performing masking and etching to form the pixel electrode 73, the first connection line 71 of the data line 22 and the source electrode 52, the drain electrode 51 and the pixel The second connection wire 72 of the electrode 73 .

Wherein, said S6 includes:

S61: Perform a grayscale masking process on the third photoresist 10 to form a pattern of the third photoresist 10, wherein the semiconductor channel 41 region and the gate line 23 region are not covered by the third photoresist 10;

S62: remove the pixel electrode layer 7 in the region of the semiconductor channel 41 and the region of the gate line 23 not covered by the third photoresist 10 through an etching process, and form the first connecting line of the pixel electrode 73, the data line 22 and the source electrode 52 71. The second connection line 72 between the drain electrode 51 and the pixel electrode 73;

S63: Stripping the third photoresist 10, and peeling off the remaining third photoresist 10.

In this preparation method, the data line 22, the gate electrode 21 and the gate line 23 are arranged on the same layer, and are connected through the first via hole 61 and the second via hole 62 of the insulating medium layer 6 and the first connection line 71 of the pixel electrode layer 3. The data line 22 and the source electrode 52, on the basis of the original 5 photolithography processes, reduce 2 photolithography processes, simplify the TFT preparation process, reduce production costs, and improve production efficiency. The fewer process steps, the higher the product yield, The easier it is to control the quality; the grayscale mask is used to mask and etch the photoresist, which is more operable and will not leave a semiconductor layer on the gate line, which will affect the structural stability and the product yield is high; The resist is a conventional photoresist with low production cost. The photoresist can be etched and peeled off at normal temperature without causing damage to the TFT glass substrate, and the yield rate of its products is higher.

Preferably, before the step S1 , a step S0 is further included: providing a transparent substrate 1 , cleaning the transparent substrate 1 , and removing dirt on the transparent substrate 1 .

The transparent substrate 1 in this step is preferably but not limited to a glass substrate.

Preferably, when a grayscale mask is used for masking in step S21, the area of the data line 22, the area of the gate line 23 and the area of the semiconductor channel 41 correspond to the part of the light-transmitting part of the mask, and the area of the source electrode 52 and the area of the drain electrode 51 The region corresponds to the opaque portion of the mask, and the other regions correspond to the completely transparent portion of the mask.

Preferably, when a grayscale mask is used for masking in step S41, the area of the data line 22 corresponds to the completely transparent part of the mask, and the area of the source electrode 52, the area of the drain electrode 51 and the area of the gate line 23 correspond to the area of the mask. Part of the light-transmitting part, and other areas correspond to the opaque parts of the mask.

Example 2

As shown in Figures 1-3, a TFT substrate includes a plurality of pixel units, and each pixel unit includes a gate metal layer 2, a gate insulating layer 3, a semiconductor layer 5, and a source/drain metal layer sequentially formed on a transparent substrate 1. Layer 5, insulating medium layer 6 and pixel electrode layer 7, wherein:

The gate metal layer 2 includes a gate electrode 21, a horizontal gate line 23 and a vertical data line 22, the gate electrode 21 is connected to the gate line 23, and the data line 22 is disconnected from the gate electrode 21 and the gate line 23 ;

The gate insulating layer 3 is located on the gate electrode 21 and the gate line 23, and is used to insulate the gate line 23/gate electrode 21 from the source electrode 52/drain electrode 51;

The semiconductor layer 5 is located on the gate insulating layer 3 of the gate electrode 21, and a semiconductor channel 41 is formed thereon;

The source/drain metal layer 5 includes a source electrode 52 and a drain electrode 51, which are respectively located on both sides of the semiconductor channel 41 of the semiconductor layer 5;

The insulating medium layer 6 is used to insulate the semiconductor layer 5, the gate electrode 21 from the pixel electrode layer 7, and the data line 22 is provided with a first via hole 61, the source electrode 52 is provided with a second via hole 62, and the drain electrode 51 is provided with a third via hole 63;

The pixel electrode layer 7 includes a pixel electrode 73 , a first connection line 71 , and a second connection line 72 .

The TFT substrate sets the data line 22, the gate electrode 21, and the gate line 23 on the same layer, and connects the data through the first via hole 61 and the second via hole 62 of the insulating medium layer 6 and the first connection line 31 of the pixel electrode layer 7. Line 22 and source electrode 52, its preparation method reduces 2 times of photolithography on the basis of the original 5 times of photolithography process, simplifies the preparation process of TFT, reduces production cost, improves production efficiency, the fewer process steps, the higher the yield of products High quality, the easier to control the quality; masking and etching the photoresist with a gray scale mask plate, the operability is stronger, and there will be no residual semiconductor layer on the gate line, which will affect the structural stability, and the yield rate of the product is high The photoresist is a conventional photoresist with low production cost. The photoresist can be etched and peeled off at normal temperature without causing damage to the TFT glass substrate, and the yield rate of its products is higher.

Wherein, the source electrode 52 is connected to the data line 22 through the first via hole 61, the second via hole 62 on the insulating medium layer 6 and the first connection line 71 on the pixel electrode layer 7, and the drain electrode 51 is connected to the data line 22 through the insulating medium layer 6. The third via hole 63 on the dielectric layer 6 and the second connection line 72 on the pixel electrode layer 7 are connected to the pixel electrode 73 .

The material of the gate metal layer 2 and the source/drain metal layer 5 is preferably but not limited to Al, Cu, Mo or Cr, and the material of the gate insulating layer 3 is preferably but not limited to silicon nitride, silicon oxide or silicon oxynitride, etc. The material of the semiconductor layer 5 is preferably but not limited to single crystal silicon, polycrystalline silicon or amorphous silicon, etc., the dielectric insulating layer is preferably but not limited to silicon nitride, silicon oxide or silicon oxynitride, etc., and the material of the pixel electrode layer 7 is preferred but not limited to Limited to ITO.

The above-described embodiments only express the implementation manner of the present invention, and its description is more specific and detailed, but it should not be interpreted as limiting the scope of the patent of the present invention, as long as the technical solutions obtained in the form of equivalent replacement or equivalent transformation are adopted , should fall within the protection scope of the present invention.

Claims (14)

1. A preparation method of a TFT substrate is characterized by comprising the following steps:

s1: sequentially depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source/drain metal layer on a transparent substrate;

s2: coating a first photoresist on the source/drain metal layer, and performing masking and etching to form a data line, a grid electrode, a grid insulating layer, a semiconductor channel, a source electrode and a drain electrode;

s3: depositing an insulating medium layer on the substrate in the step S2;

s4: coating a second photoresist on the insulating medium layer, and performing masking and etching to form a first via hole, a second via hole and a third via hole of the insulating medium layer which are respectively positioned above the data line, the source electrode and the drain electrode;

s5: depositing a pixel electrode layer on the substrate in the step S4;

s6: coating a third photoresist on the pixel electrode layer, and performing masking and etching to form a first connecting line of a pixel electrode, a data line and a source electrode, a drain electrode and a second connecting line of the pixel electrode;

wherein the S4 comprises:

s41: performing a gray scale mask process on the second photoresist to form a second photoresist pattern, wherein the second photoresist in the source electrode region, the drain electrode region and the gate line region has a third thickness, the data line region is not covered by the second photoresist, the second photoresist in other regions has a fourth thickness, and the fourth thickness is greater than the third thickness;

s42: removing the insulating dielectric layer of the data line region which is not covered by the second photoresist through an etching process to expose the gate insulating layer and the semiconductor layer of the data line region;

s43: performing an ashing process on the second photoresist, removing the photoresist with a third thickness, and exposing the insulating dielectric layers of the source electrode area, the drain electrode area and the grid line area;

s44: removing the gate insulating layer and the semiconductor layer in the data line region, the insulating dielectric layer on the source/drain electrode region, the semiconductor layer and the insulating dielectric layer in the gate line region, and the gate insulating layer and the semiconductor layer in the data line region by an etching process to form a first via hole, a second via hole and a third via hole of the insulating dielectric layer respectively positioned above the data line, the source electrode and the drain electrode;

s45: and stripping the second photoresist, and stripping the residual second photoresist.

2. The method for manufacturing a TFT substrate according to claim 1, further comprising, before step S1, step S0: providing a transparent substrate, cleaning the transparent substrate, and removing dirt on the transparent substrate.

3. The method for manufacturing a TFT substrate as set forth in claim 1, wherein the step S2 includes:

s21: performing a gray scale mask process on the first photoresist to form a first photoresist pattern, wherein the first photoresist in the source electrode region and the drain electrode region has a first thickness, the first photoresist in the gate line region, the data line region and the semiconductor channel region has a second thickness, the other regions are not covered by the first photoresist, and the first thickness is greater than the second thickness;

s22: removing the source/drain metal layer, the semiconductor layer and the gate insulating layer of the other region which is not covered by the first photoresist by an etching process to form a data line, a gate electrode and a gate insulating layer;

s23: performing an ashing process on the first photoresist, removing the first photoresist with the second thickness, and exposing the gate line region, the data line region and the source/drain metal layer of the semiconductor channel region;

s24: etching the exposed source/drain metal layer and the semiconductor layer below the metal layer through an etching process to form a semiconductor channel, a source electrode and a drain electrode;

s25: and stripping the first photoresist, and stripping the residual first photoresist.

4. The method of claim 3, wherein when the gray-scale mask is used for masking in step S21, the data line region, the gate line region and the semiconductor channel region correspond to partial light-transmitting portions of the mask, the source electrode region and the drain electrode region correspond to light-proof portions of the mask, and the other regions correspond to full light-transmitting portions of the mask.

5. The method for manufacturing a TFT substrate as set forth in claim 1, wherein the S6 includes:

s61: performing a gray scale mask process on the third photoresist to form a third photoresist pattern, wherein the semiconductor channel region and the grid line region are not covered by the third photoresist;

s62: removing the pixel electrode layer of the semiconductor channel region and the grid line region which are not covered by the third photoresist through an etching process to form a first connecting line of a pixel electrode, a data line and a source electrode, a drain electrode and a second connecting line of the pixel electrode;

s63: and stripping the third photoresist, and stripping the residual third photoresist.

6. The method of manufacturing a TFT substrate according to claim 1, wherein when the gray-scale mask is used for masking in step S41, the data line region corresponds to a completely transparent portion of the mask, the source electrode region, the drain electrode region, and the gate line region correspond to a partially transparent portion of the mask, and the other regions correspond to opaque portions of the mask.

7. A preparation method of a TFT substrate is characterized by comprising the following steps:

s1: sequentially depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source/drain metal layer on a transparent substrate;

s2: coating a first photoresist on the source/drain metal layer, and performing masking and etching to form a data line, a grid electrode, a grid insulating layer, a semiconductor channel, a source electrode and a drain electrode;

s3: depositing an insulating medium layer on the substrate in the S2;

s4: coating a second photoresist on the insulating medium layer, and performing masking and etching to form a first via hole, a second via hole and a third via hole of the insulating medium layer which are respectively positioned above the data line, the source electrode and the drain electrode;

s5: depositing a pixel electrode layer on the substrate in the step S4;

s6: coating a third photoresist on the pixel electrode layer, and performing masking and etching to form a first connecting line of a pixel electrode, a data line and a source electrode, a drain electrode and a second connecting line of the pixel electrode;

wherein the S6 comprises:

s61: performing a gray scale mask process on the third photoresist to form a third photoresist pattern, wherein the semiconductor channel region and the gate line region are not covered by the third photoresist;

s62: removing the pixel electrode layer of the semiconductor channel region and the grid line region without being covered by the third photoresist through an etching process to form a first connecting line of a pixel electrode, a data line and a source electrode, a drain electrode and a second connecting line of the pixel electrode;

s63: and stripping the third photoresist, and stripping the residual third photoresist.

8. The method for manufacturing a TFT substrate according to claim 7, further comprising, before step S1, step S0: providing a transparent substrate, cleaning the transparent substrate, and removing dirt on the transparent substrate.

9. The method for manufacturing a TFT substrate as set forth in claim 7, wherein the step S2 includes:

s21: performing a gray scale mask process on the first photoresist to form a first photoresist pattern, wherein the first photoresist in the source electrode region and the drain electrode region has a first thickness, the first photoresist in the gate line region, the data line region and the semiconductor channel region has a second thickness, the other regions are not covered by the first photoresist, and the first thickness is greater than the second thickness;

s22: removing the source/drain metal layer, the semiconductor layer and the gate insulating layer of the other region which is not covered by the first photoresist through an etching process to form a data line, a gate electrode and a gate insulating layer;

s23: performing an ashing process on the first photoresist, removing the first photoresist with the second thickness, and exposing the source/drain metal layer of the gate line region, the data line region and the semiconductor channel region;

s24: etching the exposed source/drain metal layer and the semiconductor layer below the metal layer through an etching process to form a semiconductor channel, a source electrode and a drain electrode;

s25: and stripping the first photoresist, and stripping the residual first photoresist.

10. The method of claim 9, wherein when masking is performed with a gray-scale mask in step S21, the data line region, the gate line region, and the semiconductor channel region correspond to a portion of the mask where light is transmitted, the source electrode region and the drain electrode region correspond to a portion of the mask where light is not transmitted, and the other regions correspond to a portion of the mask where light is transmitted completely.

11. The method according to claim 7, wherein the step S4 comprises:

s41: performing a gray scale mask process on the second photoresist to form a second photoresist pattern, wherein the second photoresist in the source electrode region, the drain electrode region and the gate line region has a third thickness, the data line region is not covered by the second photoresist, the second photoresist in other regions has a fourth thickness, and the fourth thickness is greater than the third thickness;

s42: removing the insulating dielectric layer of the data line region which is not covered by the second photoresist through an etching process to expose the gate insulating layer and the semiconductor layer of the data line region;

s43: performing an ashing process on the second photoresist, removing the photoresist with a third thickness, and exposing the insulating dielectric layers of the source electrode area, the drain electrode area and the grid line area;

s44: removing the gate insulating layer and the semiconductor layer in the data line region, the insulating dielectric layer on the source/drain electrode region, the semiconductor layer and the insulating dielectric layer in the gate line region, and the gate insulating layer and the semiconductor layer in the data line region by an etching process to form a first via hole, a second via hole and a third via hole of the insulating dielectric layer respectively positioned above the data line, the source electrode and the drain electrode;

s45: and stripping the second photoresist, and stripping the residual second photoresist.

12. The method of manufacturing a TFT substrate according to claim 11, wherein when the gray-scale mask is used for masking in step S41, the data line region corresponds to a completely transparent portion of the mask, the source electrode region, the drain electrode region, and the gate line region correspond to a partially transparent portion of the mask, and the other regions correspond to opaque portions of the mask.

13. A TFT substrate comprising a plurality of pixel units, characterized by being prepared by the method of any one of claims 1 to 12; each pixel unit comprises a gate metal layer, a gate insulating layer, a semiconductor layer, a source/drain metal layer, an insulating medium layer and a pixel electrode layer which are sequentially formed on a transparent substrate, wherein:

the gate metal layer comprises a gate electrode, a transverse gate line and a vertical data line, the gate electrode is connected with the gate line, and the data line is disconnected with the gate electrode and the gate line;

the gate insulating layer is positioned on the gate electrode and the gate line and is used for insulating the gate line/the gate electrode from the source electrode/the drain electrode;

the semiconductor layer is positioned on the gate insulating layer of the gate electrode, and a semiconductor channel is formed on the semiconductor layer;

the source/drain metal layer comprises a source electrode and a drain electrode which are respectively positioned above two sides of the semiconductor channel of the semiconductor layer;

the insulating medium layer is used for insulating the semiconductor layer, the gate electrode and the pixel electrode layer, a first through hole is formed in the data line, a second through hole is formed in the source electrode, and a third through hole is formed in the drain electrode;

the pixel electrode layer comprises a pixel electrode, a first connecting wire and a second connecting wire.

14. The TFT substrate of claim 13, wherein the source electrode is connected to the data line through a first via hole and a second via hole in the insulating dielectric layer and a first connection line on the pixel electrode layer, and the drain electrode is connected to the pixel electrode through a third via hole in the insulating dielectric layer and a second connection line on the pixel electrode layer.

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