CN100489803C - Chip and chip testing method - Google Patents
Chip and chip testing method Download PDFInfo
- Publication number
- CN100489803C CN100489803C CNB2007100022975A CN200710002297A CN100489803C CN 100489803 C CN100489803 C CN 100489803C CN B2007100022975 A CNB2007100022975 A CN B2007100022975A CN 200710002297 A CN200710002297 A CN 200710002297A CN 100489803 C CN100489803 C CN 100489803C
- Authority
- CN
- China
- Prior art keywords
- chip
- speed bus
- address date
- outside signal
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The present invention relates to a chip and a chip testing and operating method, and more particularly, to a chip and a chip testing method applied to a low frequency test signal. The chip of the invention is applied to a computer system, wherein both ends of the chip are connected with a high-speed bus and a low-speed bus respectively, the chip comprises a test control unit, a preset address data, a control unit and a data processing unit, wherein the test control unit is provided with a preset address data, receives an external signal transmitted by the low-speed bus and determines whether to compare the address data of the external signal with the preset address data or not according to a control signal; an upstream component control unit connected to the high-speed bus and the test control unit for transmitting the external signal to the high-speed bus; and a downstream component control unit connected to the high-speed bus and the test control unit for transmitting the external signal to the low-speed bus.
Description
Technical field
The present invention relates to a kind of chip and chip testing and method of operating, particularly relate to the chip and the chip detecting method that are applied to a low frequency test signal.
Background technology
Can normally operate in order to ensure computer system, after chip manufacturing is finished, must whether can normally receive and send messages to judge chip earlier through test via its bus interface.When prior art is wanted test chip, be directly to test signal via the bus transmitting-receiving of chip with external tester table.For example an external tester table is attached to the high-speed bus end of chip, tester table is sent to a test signal in the chip, through after the running of chip, by the low speed bus termination Acceptance Tests signal that chip linked, the test signal that sends by the high-speed bus end via comparison and judge whether operate as normal of chip by the test signal that the low speed bus end is received.
Because the very high speed of high-speed bus, high-speed bus usually can be up to 6.4Ghz (super transfer bus hyper transport bus) for instance.When wanting test chip, just must use expensive high speed test board, so can significantly increase the manufacturing cost of chip.
In addition, because the gaps between their growth rates of the speed of high-speed bus and low speed bus more and more big (for instance, low speed bus is the PCI Bus of a 66MHz), so regular meeting causes the problem of chip testing distortion.
And how to solve along with the host side bus speed constantly promotes, and tester table just must constantly be eliminated and changes and upgrade, and fast between host side bus and pci bus at a slow speed gaps between their growth rates cause the problems such as distortion of chipset test result more and more greatly, be the fundamental purpose of invention development.
Summary of the invention
The present invention proposes to be applied to a chip of a computer system, its chips one end connects a high-speed bus other end and connects a low speed bus, comprise: a unit of testing and controlling, one default address date is arranged, the outside signal that reception is transmitted by low speed bus, whether decision compares the address date and the default address date of outside signal according to a controlling signal; One low speed bus control module is connected in this low speed bus, in order to control the transmission of this low speed bus end signal; One high-speed bus control module is connected in this high-speed bus, in order to control the transmission of this high-speed bus end signal; One upstream component control module is connected to high-speed bus control module and unit of testing and controlling, in order to transmit outside signal to the high speed bus; And a downstream assembly control module, be connected to high-speed bus control module and unit of testing and controlling, in order to transmit outside signal to low speed bus.
The present invention also proposes to be applied to the chip detecting method of a computer system, and its chips one end links a high-speed bus other end and links a low speed bus, and this method comprises: import an outside signal to chip by the low speed bus end; Compare the address date and a default address date of outside signal; If the address date of outside signal is identical with default address date, then utilize memory mapping output input path to transmit outside signal to the low speed bus end; Read outside signal by the low speed bus end.
The present invention also proposes to be applied to the chip operation method of a computer system, and its chips one end links a high-speed bus, and the other end links a low speed bus, and this method comprises: the initialization chip; Import an outside signal to chip by the low speed bus end; And judge that according to the state of a controlling signal chip is a normal manipulation mode or a test pattern; Wherein when chip is test pattern, compare the address date and a default address date of outside signal.
Description of drawings
Fig. 1 is the function block schematic diagram of a chip test system.
Fig. 2 is the function block schematic diagram of a chip test system of invention.
Fig. 3 is a chip detecting method process flow diagram of invention.
The reference numeral explanation
High-speed bus control module 101,201
Low speed bus control module 102,202
Upstream component control module 103,203
Downstream components control module 104,204
High-speed bus 12,22
Unit of testing and controlling 205
Memory mapping input and output path 2050
Embodiment
Fig. 1 is the function block schematic diagram of a chip test system.These chip 10 1 ends connect a high-speed bus 12, one ends and connect a low speed bus 14.Wherein high-speed bus 12 can be a host bus (Hostbus), and low speed bus 14 can be a peripheral component bus (PCI bus) or a quick peripheral assembly bus (PCI Express bus).Its chips 10 includes: a high-speed bus control module 101 is connected to high-speed bus 12, in order to the data transmission of control high-speed bus 12; One low speed bus control module 102 is connected to low speed bus 14, in order to the data transmission of control low speed bus 14; One upstream component control module 103 (Upstream control unit) is connected to high-speed bus control module 101 and low speed bus control module 102, in order to transfer data to high-speed bus control module 101; And a downstream assembly control module 104 (Downstream control unit), be connected to high-speed bus control module 101 and low speed bus control module 102, in order to transfer data to low speed bus control module 102.
As shown in Figure 1, when chip 10 when accepting test, one tester table (not shown) can be sent into a test signal (test pattern) to chip 10 by high-speed bus 12, in chip 10 inside, high-speed bus control module 101, downstream components control module 104, and low speed bus control module 102 can be done computing and processing to this test signal in regular turn, these at last will be by low speed bus 14 outputs by computing and the test signal of handling, this moment is by analyzing this by computing and the test signal of handling, and can draw the test result of this chip 10, and then judge whether the running of this chip 10 is normal.
In general in chip 10 inside, except a part of high-speed bus control module 101 is under high speed the running, all the other partly are to operate under relatively low speed.Therefore, when the high-frequency test signal that is produced with a radio-frequency signal generator (high-frequency test board) was tested in the chip 10 that operate partly assembly under relatively low speed, regular meeting caused the distortion of test result.
Fig. 2 is the function block schematic diagram of a chip test system of the present invention.This chip test system is applied to a chip 20 of a computer system.Its chips 20 1 ends connect a high-speed bus 22, one ends and connect a low speed bus 24.Wherein high-speed bus 22 can be a host side bus (host bus), and low speed bus can be a pci bus or a PCI E bus.And the operating rate of high-speed bus 22 is much larger than the operating rate of low speed bus 24.
Below with regard to the invention method of testing describe.When computer system power-on, at first utilize the ROMSIP of each register setting value that prestores among the BIOS to carry out the initializing set of chip 20, wherein be included in unit of testing and controlling 205 and insert a default address date.In addition, unit of testing and controlling 205 can be controlled its duty by a controlling signal, but and then setting chip 20 be to work in normal manipulation mode or test pattern.When controlling signal is a disabled, chip 20 is a normal manipulation mode, and this moment, unit of testing and controlling 205 received the outside signal that is transmitted by low speed bus 24, and according to the data address of outside signal this outside signal was uploaded to upstream component control module 203.When controlling signal is activation, then chip 20 is a test pattern, and is a test signal by the outside signal that low speed bus 24 is sent to chip 20.Unit of testing and controlling 205 makes test signal and default address date carry out the comparison of address date.
When the test signal address date identical with default address date, then rewrite the address date of test signal, make the test signal be sent to downstream components control module 204 by a memory mapping input and output path (Memory Map Input OutputPath is called for short MMIO Path) 2050.If address date and the default address date of test signal are inequality, then according to the original address data of test signal transmit test signal to upstream assembly control module 203 with and corresponding address (high-speed bus end or low speed bus end).
Before chip 20 was tested, chip 20 itself must be introduced into the state of normal operation, so the related register (register) in the chip must be received in suitable value earlier and finishes initialization.The method of general initialization chip 20 is normally undertaken by the configuration cycle (configuration cycle) of the initializing set that is sent from high-speed bus 12.In the present invention, owing to do not use high-speed bus 22 ends to test, the initial value that therefore can utilize among the ROMSIP to be kept in carries out the initializing set of chip 20.But along with the function of chip is more and more powerful, the quantity of register that needs to write preset data in the chip is also more and more many, and the data capacity of ROMSIP has only 64 four word groups (quad word is called for short QW) usually.Therefore, the present invention more can be used in the configuration cycle (configuration cycle) that low speed bus 24 sends initializing set in addition and carries out the initialization of chip 20.And the address date in configuration cycle (configurationcycle) will be identical with the default address date of unit of testing and controlling 205, therefore the address date in configuration cycle (configuration cycle) can be rewritten, that is make the configuration cycle by memory mapping input and output path (Memory Map Input Output Path, abbreviation MMIO path) 2050 is sent to downstream components control module 204, and then emulation becomes the configuration cycle of being sent by high-speed bus control module 201 (configuration cycle), sets to carry out chip initiation.
The present invention can also carry out the test of low-frequency signal except testing the high-frequency signals.After chip 20 initialization were finished, the proving installation (not shown) that is connected on the low speed bus 24 can be via low speed bus 24 inputs one low frequency test signal to chip 20.After low frequency test signal reaches unit of testing and controlling 205 via 202 commentaries on classics of low speed bus control module, the address date of this low frequency test signal will be compared with the default address date of unit of testing and controlling 205, if the address date of low frequency test signal is different with the default address date of this unit of testing and controlling 205, then this low frequency test signal will be reached upstream component control module 203 and then deliver to high-speed bus control module 201 by commentaries on classics, and then passes through the processing and the commentaries on classics of downstream components control module 204 and low speed bus control module 202.If the address is identical, then this low frequency test signal will reach downstream components control module 204 via 2050 commentaries on classics of MMIO path, processing and commentaries on classics via low speed bus control module 202 passes again, but last both can export a low frequency test signal of handling via low speed bus 24.At this moment, test signal by analyzing this processed low frequency, and can draw the test result of this chip 20, and then judge whether the function of this chip 20 is normal.
See also Fig. 3, it is a chip detecting method process flow diagram of the present invention.At first, initialization chip 20 (step 31); Send into a test signal to low speed bus control module 202 (step 32) by low speed bus 24; Behind the address date of unit of testing and controlling 205 acceptance test signals, with a default address date compare (step 33); If address date is identical, then this test signal is changeed reaching downstream assembly control module 204 (steps 34) via a MMIO path 2050; If address date is inequality, then this test signal is changeed reaching a upstream component control module 203 (step 35); Read the test signal of finishing after commentaries on classics passes by low speed bus 24 ends again and carry out follow-up test procedure (step 36).
Chip is done transmission as signal in response to some more special situation between two display cards or Frame Grabber of a display card, therefore have path (for example: a pci bus is to the path of another pci bus (peer-to-peer)).Method of testing of the present invention is promptly tested signal in the bus end input one of a low speed low frequency, make test signal through path thus and by chip computing and processing, export this test signal via the bus end of another low speed low frequency again and finish the test of this chip at last.Thus, the test of chip will need not brought in the input test signal by the bus of high-speed high frequency, and this can solve along with the host side bus speed constantly promotes, and tester table just must constantly be eliminated the problem of changing.Also can solve simultaneously the problems such as distortion that gaps between their growth rates between the bus end of bus end at a high speed and low speed cause chip testing result to be measured more and more greatly.
In addition, in the time of can not providing enough data to come in the initialization chip 20 register when the ROMSIP finite capacity, the commentaries on classics location function that can be provided by unit of testing and controlling 205, change to reach downstream components control module 204 with one from the configuration cycle of low speed bus 24 input, and then finish the writing of a plurality of content of registers of these chip 20 initializing sets and be resolved.And invention can be widely used in the design and test of various integrated circuit (IC) chip, the especially design of core logic chipset and test, so those skilled in the art can do various modifications under the prerequisite that does not break away from claim of the present invention.
Claims (13)
1. a chip is applied to a computer system, and this chip one end connects a high-speed bus, and the other end connects a low speed bus, and this chip comprises:
One unit of testing and controlling has a default address date, the outside signal that reception is transmitted by this low speed bus, and whether decision is compared the address date of this outside signal and should be preset address date according to a controlling signal;
One low speed bus control module is connected in this low speed bus, in order to control the transmission of this low speed bus end signal;
One high-speed bus control module is connected in this high-speed bus, in order to control the transmission of this high-speed bus end signal;
One upstream component control module is connected to this high-speed bus control module and this unit of testing and controlling, in order to transmit this outside signal to this high-speed bus; And
One downstream assembly control module is connected to this high-speed bus control module and this unit of testing and controlling, in order to transmit this outside signal to this low speed bus.
2. chip as claimed in claim 1, wherein when this controlling signal was disabled, this chip was a normal manipulation mode, the address date of this outside signal is not compared with this default address date.
3. chip as claimed in claim 1, wherein when this controlling signal is activation, this chip is a test pattern, make the address date of this outside signal compare with this default address date, wherein if coming to the same thing of comparison then makes this outside signal be sent to this downstream components control module via memory mapping output input path; Wherein if the difference as a result of comparison then makes this outside signal be sent to this upstream component control module.
4. chip as claimed in claim 3, wherein rewrite the address date of this outside signal, make this outside signal to be sent to this downstream components control module via this memory mapping output input path, this outside signal can be a configuration cycle, the address date in this configuration cycle is identical with this default address date, this configuration cycle is sent to this downstream components control module via this memory mapping output input path, in order to this chip of initialization.
5. chip as claimed in claim 1 wherein utilizes the value that is pre-stored among the ROMSIP to insert this default address date.
6. a chip detecting method is applied in the computer system, and this chip one end links a high-speed bus, and the other end links a low speed bus, and this method of testing comprises:
Import an outside signal to this chip by this low speed bus end;
Compare the address date and a default address date of this outside signal;
If the address date of this outside signal then utilizes memory mapping output to import the path and transmits this outside signal to this low speed bus end with should default address date identical;
Read this outside signal by this low speed bus end.
7. method as claimed in claim 6 wherein also comprises and utilizes ROMSIP or utilize this chip of configuration cycle initialization, should the outside signal be this configuration cycle wherein, and the address date in this configuration cycle is identical with this default address date.
8. method as claimed in claim 6 wherein also comprises and utilizes the ROMSIP setting should preset address date.
9. method as claimed in claim 6, wherein if the address date of this outside signal is inequality with this default address date, then the address date according to this outside signal transmits this outside signal to this high-speed bus end or this low speed bus end.
10. a chip operation method is applied in the computer system, and this chip one end links a high-speed bus, and the other end links a low speed bus, and this method of operating comprises:
This chip of initialization;
Import an outside signal to this chip by this low speed bus end; And
Judge that according to the state of a controlling signal this chip is a normal manipulation mode or a test pattern;
Wherein when this chip is test pattern, compare the address date and a default address date of this outside signal.
11. method as claimed in claim 10 wherein when this chip is normal manipulation mode, transmits this outside signal according to the address date of this outside signal.
12. method as claimed in claim 10 is when this chip is test pattern, if the address date of this outside signal is then imported the path via memory mapping output and transmitted this outside signal to this low speed bus end with should default address date identical; If the address date of this outside signal is with should default address date inequality, transmit this outside signal according to the address date of this outside signal.
13. method as claimed in claim 10 also comprises and utilizes ROMSIP or this chip of configuration cycle initialization, wherein the address date in this configuration cycle is identical with this default address date.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100022975A CN100489803C (en) | 2007-01-17 | 2007-01-17 | Chip and chip testing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100022975A CN100489803C (en) | 2007-01-17 | 2007-01-17 | Chip and chip testing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101008909A CN101008909A (en) | 2007-08-01 |
| CN100489803C true CN100489803C (en) | 2009-05-20 |
Family
ID=38697353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007100022975A Active CN100489803C (en) | 2007-01-17 | 2007-01-17 | Chip and chip testing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100489803C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103377103B (en) * | 2012-04-28 | 2017-10-03 | 珠海格力电器股份有限公司 | Method, device and system for testing stored data |
| CN112540282B (en) * | 2019-09-20 | 2024-11-12 | 台湾中华精测科技股份有限公司 | Test equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5606567A (en) * | 1994-10-21 | 1997-02-25 | Lucent Technologies Inc. | Delay testing of high-performance digital components by a slow-speed tester |
| CN1407467A (en) * | 2001-09-13 | 2003-04-02 | 深圳市中兴通讯股份有限公司上海第二研究所 | Bus-bus quick transmission devices |
| US6591369B1 (en) * | 1999-10-01 | 2003-07-08 | Stmicroelectronics, Ltd. | System and method for communicating with an integrated circuit |
| CN1614580A (en) * | 2004-11-26 | 2005-05-11 | 上海广电（集团）有限公司中央研究院 | Low-speed bus structure and its data transmission |
| CN1811726A (en) * | 2005-01-24 | 2006-08-02 | 惠普开发有限公司 | On-chip circuitry for bus validation |
-
2007
- 2007-01-17 CN CNB2007100022975A patent/CN100489803C/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5606567A (en) * | 1994-10-21 | 1997-02-25 | Lucent Technologies Inc. | Delay testing of high-performance digital components by a slow-speed tester |
| US6591369B1 (en) * | 1999-10-01 | 2003-07-08 | Stmicroelectronics, Ltd. | System and method for communicating with an integrated circuit |
| CN1407467A (en) * | 2001-09-13 | 2003-04-02 | 深圳市中兴通讯股份有限公司上海第二研究所 | Bus-bus quick transmission devices |
| CN1614580A (en) * | 2004-11-26 | 2005-05-11 | 上海广电（集团）有限公司中央研究院 | Low-speed bus structure and its data transmission |
| CN1811726A (en) * | 2005-01-24 | 2006-08-02 | 惠普开发有限公司 | On-chip circuitry for bus validation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101008909A (en) | 2007-08-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9575552B2 (en) | Device, method and system for operation of a low power PHY with a PCIe protocol stack | |
| US20100122003A1 (en) | Ring-based high speed bus interface | |
| CN108920173B (en) | Method, chip and communication system for configuring equalization time | |
| CN102176702A (en) | Test system and test method | |
| CN114297134A (en) | A chip architecture and signal integrity testing method | |
| CN110968352B (en) | Reset system and server system of PCIE equipment | |
| CN104407882A (en) | Board card device | |
| CN112041827A (en) | Automatic USB host detection and port configuration | |
| CN102053898A (en) | Test method for bus interface on PCIE slot of host and read-write test method thereof | |
| CN101907683B (en) | Automatic circuit testing structure of I2C module in digital baseband chip and method thereof | |
| US9032252B2 (en) | Debug barrier transactions | |
| CN100489803C (en) | Chip and chip testing method | |
| CN101232522A (en) | A kind of network card driving method | |
| CN113671360B (en) | I2C interface device testing method and device and I2C interface device | |
| CN109597651A (en) | A kind of serial ports and network interface module development approach based on MPC7410 processor | |
| US8694839B2 (en) | Method and system for testing chips | |
| TWM592995U (en) | Control system of accessing data for memory cards | |
| CN212229628U (en) | Slave device | |
| US20100191895A1 (en) | System, test apparatus and relay apparatus | |
| CN118354057A (en) | CX3 chip-based image sensor testing device and system | |
| CN116148627A (en) | Detection system and method for PCIe CEM connection interface in circuit board | |
| CN114660383A (en) | A universal load manager test board | |
| CN106326172A (en) | APB bus slave interface expansion circuit and use method thereof | |
| GB2443541A (en) | Serializer/De-serializer bus and controller for a ASIC with a method for testing the ASIC. | |
| CN101118268B (en) | System and method for testing external component interconnection extension slot |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |