CN100471051C - A Low Voltage Negative Feedback Transconductance Amplifier - Google Patents

Abstract

The invention is a low-voltage negative feedback transconductance amplifier, which is characterized in that it combines the advantages of current negative feedback, flip voltage follower and source-level attenuation, and overcomes the small input amplitude and poor linearity of traditional transconductance amplifiers. Not suitable for low voltage work and other disadvantages. The current negative feedback module of the present invention significantly increases the input amplitude of the transconductance amplifier, and the combination of the low-resistance node of the flipping voltage follower module and the source-level attenuation structure reduces the distortion caused by the traditional source-level attenuation structure. At the same time, the introduction of low-resistance nodes in the source-level attenuation gives greater design freedom to circuit design, unlike traditional structures that require a compromise between transconductance, bias current, and output resistance. At the same time, the maximum voltage drop of the circuit on the critical path is smaller than that of the traditional structure circuit, thus showing the potential of working at a lower voltage. This circuit has the characteristics of large input range, high linearity and suitable for low voltage operation.

Description

A Low Voltage Negative Feedback Transconductance Amplifier

technical field

The invention belongs to the design of ultra-large-scale integrated circuits in the field of microelectronics and solid-state electronics, and relates to a novel transconductance amplifier circuit, which can be used for analog signal processing circuits, Gm-C filters, analog-to-digital conversion circuits and variable gain design of amplifiers, etc.

Background technique

Transconductance amplifier is an important component module of analog circuit, widely used in analog signal processing circuit, Gm-C filter, analog-to-digital conversion circuit and variable gain amplifier. Recently, transconductance amplifiers have also been used in sampling mixer circuits working at intermediate frequencies or even radio frequencies. In these circuits, the linearity of the overall system is often determined by the transconductance amplifier. Although in the published literature, many methods to improve the linearity of transconductance amplifiers have been proposed, such as cross-coupled multi-channel differential input, source attenuation, substrate driving, balanced pseudo-differential structure, etc. Influenced by linearity and other factors, its total harmonic distortion (THD) is generally -40dB ~ -60dB, and its input amplitude is far below the power supply voltage.

Therefore, designing a high-performance transconductance amplifier with high linearity and large input amplitude, which can work at low voltage, has become one of the main problems that need to be solved urgently in the design of analog circuits.

Aiming at this situation, the present invention provides a novel transconductance amplifier circuit that combines the three technical advantages of current negative feedback, flip voltage follower and source-level attenuation.

Contents of the invention

The object of the present invention is to provide a transconductance amplifier circuit capable of overcoming the above disadvantages, having high linearity and large input amplitude, and capable of operating at low voltage.

The present invention uses a feedback resistor to form a current negative feedback. The function of this resistor is to force a part of the AC voltage to fall on this resistor through current feedback, significantly reducing the voltage applied to the input tube M1/M2, thereby reducing the generation of nonlinear terms, and at the same time reducing the linear input amplitude of the transconductance amplifier mentioned above the supply voltage level.

The complete expression of the transconductance of the transconductance amplifier is:

${\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; kg</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; kR</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>}$

Among them, g _m1 is the transconductance of the M1 tube, r _o1 is the output resistance of the M1 tube, g _m3 is the transconductance of the M3 tube, and k is the ratio of the bias current between the channel where the M1 tube is located and the channel where the M7 tube is located. R _in is the feedback resistor and R _S is the source attenuation resistor. Due to the use of a flipping voltage follower, the output resistance of this follower is:

${\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}$

The small output resistance can significantly eliminate the distortion introduced by the source attenuation structure. Since the voltage drop on the flip follower V _gs is a fixed voltage, the input signal is accurately transmitted from the gate of the input transistor M1/M2 to the source, without introducing distortion like the traditional structure, and improving the linearity Spend. Another benefit brought by this circuit is that the formula 1/r _o1 g _m3 <<g _m1 (kR _in +R _S /2) can be established more easily. Therefore, greater design freedom is given to the circuit design. Unlike the traditional structure, it is necessary to make a trade-off between the transconductance value, bias current, and output resistance. Therefore, the expression of this transconductance amplifier can be simplified as:

${\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; \&ap;</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; k</span>}}$

It can be seen that the transconductance value is completely controlled by the feedback resistance, the source decay resistance and the current ratio. Therefore, this circuit can achieve extremely high transconductance linearity. In addition, various transconductance values can be obtained by modifying the value of the feedback resistor R _in .

The present invention is characterized in that containing:

Four N-type MOS transistors: the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 form two flip voltage followers, in which the gate of the first MOS transistor M1 passes through the A node 11 is connected to the first feedback resistor R _inp , the other end of the first feedback resistor R _inp is connected to the first input voltage V _inp through the second node 110 , and the gate of the second MOS transistor M2 is connected to the second feedback resistor through the third node 21 Resistor R _inn , the other end of the second feedback resistor R _inn is connected to the second input voltage _Vinn through the fourth node 210; the first feedback resistor R _inp and the second feedback resistor R _inn force a part of the input voltage to be added to the second feedback resistor R inn through current feedback A feedback resistor R _inp and a second feedback resistor R _inn , thereby reducing the voltage applied to the first MOS transistor M1 and the second MOS transistor M2, reducing the generation of nonlinear terms, and at the same time increasing the input amplitude of the transconductance amplifier to the power supply voltage level; the source of the first MOS transistor M1 and the drain of the third MOS transistor M3 are connected to the fifth node 12; the source of the second MOS transistor M2 and the drain of the fourth MOS transistor M4 are connected to the first Six nodes 22; a source attenuation resistor R _S is connected between the fifth node 12 and the sixth node 22, so as to significantly reduce the distortion introduced by the source attenuation;

The current mirror consists of 8 N-type MOS transistors: the fifth MOS transistor M5, the sixth MOS transistor M6, the eleventh MOS transistor M11, the twelfth MOS transistor M12, the thirteenth MOS transistor M13, the fourteenth MOS transistor M14, The fifteenth MOS transistor M15 and the sixteenth MOS transistor M16 are composed of the thirteenth MOS transistor M13, the fifth MOS transistor M5, the sixth MOS transistor M6, and the fourteenth MOS transistor M14. The gates of the fifth MOS transistor M15 and the eleventh MOS transistor M11 are connected to the bias signal through the seventh node 15; the gates of the sixteenth MOS transistor M16 and the twelfth MOS transistor M12 are connected to the bias signal through the eighth node 25 signal, the gates of the thirteenth MOS transistor M13 and the fifth MOS transistor M5 are connected to the ninth node 23 with the gate of the fourth MOS transistor M4 and the drain of the second MOS transistor M2, and the fourteenth MOS transistor M14 and The gate of the sixth MOS transistor M6 is simultaneously connected to the gate of the third MOS transistor M3 and the drain of the first MOS transistor M1 to the tenth node 13, and the source of the fifteenth MOS transistor M15 is connected to the thirteenth MOS transistor M13 The drain of the MOS transistor M11 is connected to the eleventh node 18, the source of the eleventh MOS transistor M11 and the drain of the fifth MOS transistor M5 are connected to the twelfth node 17, the source of the twelfth MOS transistor M12 is connected to the sixth MOS transistor M12 The drain of the transistor M6 is connected to the thirteenth node 27, the source of the sixteenth MOS transistor M16 and the drain of the fourteenth MOS transistor M14 are connected to the fourteenth node 28; The drains of the twelve MOS transistors M12 are respectively connected to the first node 11 and the third node 21 in turn;

The current source load circuit is composed of 6 P-type MOS tubes: the seventh MOS tube M7, the eighth MOS tube M8, the ninth MOS tube M9, the tenth MOS tube M10, the seventeenth MOS tube M17, and the eighteenth MOS tube M18 , wherein the sources of the seventh MOS transistor M7, the eighth MOS transistor M8, the ninth MOS transistor M9, the tenth MOS transistor M10, the seventeenth MOS transistor M17, and the eighteenth MOS transistor M18 are connected to the power supply V _dd , The gates of the seventh MOS transistor M7, the eighth MOS transistor M8, the ninth MOS transistor M9, the tenth MOS transistor M10, the seventeenth MOS transistor M17, and the eighteenth MOS transistor M18 are connected to the fifteenth node 14, The fifteenth node 14 is externally connected with a bias circuit to provide the quiescent DC current of the current source load circuit, the drains of the seventh MOS transistor M7 and the tenth MOS transistor M10 are respectively connected to the first node 11 and the third node 21 in turn, and the tenth node The drain of the seventh MOS transistor M17 and the drain of the fifteenth MOS transistor M15 are connected to the sixteenth node 19 to form the second output node i _on , the drain of the eighteenth MOS transistor M18 and the drain of the sixteenth MOS transistor M16 The drain is connected to the seventeenth node 29 to form the first output node i _op ;

Two P-type MOS transistors: the nineteenth MOS transistor Mp8 and the twentieth MOS transistor Mp9, the sources of the two MOS transistors are connected to the power supply V _dd , and the gates are connected to the eighteenth node 16, and the eighteenth node 16 is the voltage feedback point of the common mode feedback circuit, the drain of the nineteenth MOS transistor Mp8 is connected to the drain of the eighth MOS transistor M8 in the current source load circuit, and then connected to the drain of the first MOS transistor M1 through the tenth node 13 connected; the drain of the twentieth MOS transistor Mp9 is connected to the drain of the ninth MOS transistor M9 in the current source load circuit and then connected to the drain of the second MOS transistor M2 in the flipping voltage follower through the ninth node 23, so that After converting the voltage signal fed back from the common mode feedback circuit into a current signal, the common mode point of the current source load circuit is adjusted.

The invented transconductance amplifier combines the advantages of current negative feedback, reverse voltage follower and source-level attenuation, and overcomes the shortcomings of traditional transconductance amplifiers such as small input amplitude, poor linearity, and unsuitability for low-voltage operation. This circuit has been tested by simulation, under the 0.18 micron CMOS process, under the power supply voltage of 1.5V. Differential input 2V peak-to-peak amplitude and 100MHz frequency signal, its total harmonic distortion (THD) is about -79dB, and the power consumption is only more than 200 microwatts.

In addition, the maximum voltage drop of the circuit on the critical path is only V _gs +2V _dsat , thus showing the potential to work at lower voltages. After testing, this circuit can work very well under the power supply voltage of 1.2V in 0.18 micron CMOS process. And the power supply voltage of the circuit still has room for further reduction.

Description of drawings

Fig. 1. circuit diagram of transconductance amplifier of the present invention.

Detailed ways

Technical solution of the present invention refers to Fig. 1. Figure 1 is a circuit structure diagram of a high linearity large input amplitude low voltage transconductance amplifier. 3 resistors R _inp , R _inn , R _S , of which the feedback resistors are R _inp and R _inn , one end of the feedback resistor is connected to the input, the other end is connected to the gate of M1\M2, and the source attenuation resistor is R _S , which is connected to M1 and between the M2 tube source stage. Four N-type MOS transistors M1, M2, M3, M4 form two reverse voltage followers. The current source load is composed of 6 P-type MOS tubes: M7, M8, M9, M10, M17, M18. The current source is composed of 8 N-type MOS transistors: M5, M6, M11, M12, M13, M14, M15, M16. Two P-type MOS transistors Mp8 and Mp9 convert the feedback voltage signal fed back from the common-mode feedback circuit into current signal, adjusts the output common-mode point of the circuit.

The specific connection relationship of the low-voltage negative feedback transconductance amplifier is as follows: node 110 and node 210 are two signal input nodes. One end of the feedback resistor R _inp is connected to the node 110 , and the other end is connected to the node 11 . One end of the feedback resistor R _inn is connected to the node 210 , and the other end is connected to the node 21 . The sources of the transistors M7, M8, M9, M10, M17 and M18 are connected to the power supply, the gates are connected to the node 14, and the node 14 is externally connected with a bias circuit to provide the quiescent DC current of the circuit. The drains of transistors M17 and M18 are connected to node 19 and node 29 respectively. Node 19 and node 29 are the output nodes of the whole circuit. The sources of the transistors Mp8 and Mp9 are connected to the power supply voltage, the gates are connected to the node 16 , and the drains are respectively connected to the nodes 13 and 23 . Node 16 is the voltage feedback point of the common mode feedback circuit. The gate of the transistor M1 is connected to the node 11 , the source is connected to the node 12 , and the drain is connected to the node 13 . The gate of the transistor M2 is connected to the node 21 , the source is connected to the node 22 , and the drain is connected to the node 23 . One end of the source attenuation resistor R _S is connected to node 12 and the other end is connected to node 22 . The drain of transistor M3 is connected to node 12 , the gate is connected to node 13 , and the source is grounded. The drain of transistor M4 is connected to node 22 , the gate is connected to node 23 , and the source is grounded. Gates of transistors M11 and M15 are connected to node 15 . The voltage at node 15 comes from the bias circuit. The drain of the transistor M11 is connected to the node 11 , and the source is connected to the node 17 . The drain of transistor M15 is connected to node 19 , and the source is connected to node 18 . The sources of the transistors M5 and M13 are grounded, and the gates are connected to the node 23 . The drain of transistor M5 is connected to node 17 . The drain of transistor M13 is connected to node 18 . Gates of transistors M12 and M16 are connected to node 25 . The voltage at node 25 comes from the bias circuit. The drain of the transistor M12 is connected to the node 21 , and the source is connected to the node 27 . The drain of transistor M16 is connected to node 29 and the source is connected to node 28 . The sources of transistors M6 and M14 are grounded, and the gates are connected to node 13 . The drain of transistor M6 is connected to node 27 . The drain of transistor M14 is connected to node 28 .

Feedback resistors R _inp and R _inn force a part of the AC voltage to be added to this resistor through current feedback, thereby reducing the voltage applied to the input tube M1/M2, reducing the generation of nonlinear terms, and at the same time reducing the input amplitude of the transconductance amplifier raised to a level above the supply voltage. The transistors M1 , M2 , M3 , and M4 constitute a structure composed of two inversion followers plus a source attenuation resistor R _S , resulting in two low-impedance output nodes 12 , 22 . The low output resistance can significantly reduce the distortion introduced by the source attenuation structure. Since the voltage drop on the flip follower V _gs is a fixed voltage, the input signal is accurately transmitted from the gate of the input transistor M1/M2 to the source, unlike the traditional structure that introduces distortion due to the unfixed V _gs . The circuit's maximum voltage drop on the critical path is only V _gs +2V _dsat , showing the potential of the circuit to operate at lower voltages. The combination of the above various technologies realizes a high-performance low-voltage negative feedback transconductance amplifier circuit with high linearity, large input range, and suitable for low-voltage operation.

Claims (1)

1. low voltage negative feedback transconductance amplifier is characterized in that containing:

4 N type metal-oxide-semiconductors: first metal-oxide-semiconductor (M1), second metal-oxide-semiconductor (M2), the 3rd metal-oxide-semiconductor (M3), the 4th metal-oxide-semiconductor (M4) has constituted two turnover voltage followers, and wherein the grid of first metal-oxide-semiconductor (M1) connects the first feedback resistance (R through first node (11) _Inp), the first feedback resistance (R _Inp) the other end through Section Point (110) meet the first input voltage (V _Inp), the grid of second metal-oxide-semiconductor (M2) connects the second feedback resistance (R through the 3rd node (21) _Inn), the second feedback resistance (R _Inn) the other end meet the second input voltage (V through the 4th node (210) _Inn); First feedback resistance (the R _Inp), the second feedback resistance (R _Inn) force the part of input voltage to be added in the first feedback resistance (R by current feedback _Inp), the second feedback resistance (R _Inn) on, thereby reduce to be added in voltage on first metal-oxide-semiconductor (M1), second metal-oxide-semiconductor (M2), reduce the generation of nonlinear terms, simultaneously the input range of trsanscondutance amplifier is brought up to the level of supply voltage; The drain electrode of the source class of first metal-oxide-semiconductor (M1) and the 3rd metal-oxide-semiconductor (M3) is connected in the 5th node (12); The drain electrode of the source class of second metal-oxide-semiconductor (M2) and the 4th metal-oxide-semiconductor (M4) is connected in the 6th node (22); Between the 5th node (12) and the 6th node (22), connecting a source class damping resistance (R _S), the distortion of being introduced with the decay of remarkable minimizing source class;

Current mirror is by 8 N type metal-oxide-semiconductors: the 5th metal-oxide-semiconductor (M5), the 6th metal-oxide-semiconductor (M6), the 11 metal-oxide-semiconductor (M11), the 12 metal-oxide-semiconductor (M12), the 13 metal-oxide-semiconductor (M13), the 14 metal-oxide-semiconductor (M14), the 15 metal-oxide-semiconductor (M15), the 16 metal-oxide-semiconductor (M16) constitute, the source class ground connection of the 13 metal-oxide-semiconductor (M13), the 5th metal-oxide-semiconductor (M5), the 6th metal-oxide-semiconductor (M6), each pipe of the 14 metal-oxide-semiconductor (M14) wherein, the grid of the 15 metal-oxide-semiconductor (M15) and the 11 metal-oxide-semiconductor (M11) is connected offset signal through the 7th node (15) jointly; The grid of the 16 metal-oxide-semiconductor (M16) and the 12 metal-oxide-semiconductor (M12) is connected offset signal through the 8th node (25) jointly, the grid while of the 13 metal-oxide-semiconductor (M13) and the 5th metal-oxide-semiconductor (M5) and the grid of the 4th metal-oxide-semiconductor (M4), the drain electrode of second metal-oxide-semiconductor (M2) is connected in the 9th node (23), the grid while of the 14 metal-oxide-semiconductor (M14) and the 6th metal-oxide-semiconductor (M6) and the grid of the 3rd metal-oxide-semiconductor (M3), the drain electrode of first metal-oxide-semiconductor (M1) is connected in protelum point (13), the source electrode of the 15 metal-oxide-semiconductor (M15) and the drain electrode of the 13 metal-oxide-semiconductor (M13) are connected in the 11 node (18), the drain electrode of the source class of the 11 metal-oxide-semiconductor (M11) and the 5th metal-oxide-semiconductor (M5) is connected in the 12 node (17), the drain electrode of the source class of the 12 metal-oxide-semiconductor (M12) and the 6th metal-oxide-semiconductor (M6) is connected in the 13 node (27), and the source electrode of the 16 metal-oxide-semiconductor (M16) and the drain electrode of the 14 metal-oxide-semiconductor (M14) are connected in the 14 node (28); In addition, the drain electrode of the 11 metal-oxide-semiconductor (M11) and the 12 metal-oxide-semiconductor (M12) links to each other with the 3rd node (21) with first node (11) respectively successively;

The current source load circuit is by 6 P type metal-oxide-semiconductors: the 7th metal-oxide-semiconductor (M7), the 8th metal-oxide-semiconductor (M8), the 9th metal-oxide-semiconductor (M9), the tenth metal-oxide-semiconductor (M10), the 17 metal-oxide-semiconductor (M17), the 18 metal-oxide-semiconductor (M18) constitute, wherein, the source electrode of the 7th metal-oxide-semiconductor (M7), the 8th metal-oxide-semiconductor (M8), the 9th metal-oxide-semiconductor (M9), the tenth metal-oxide-semiconductor (M10), the 17 metal-oxide-semiconductor (M17), each pipe of the 18 metal-oxide-semiconductor (M18) meets power supply (V _Dd), the 7th metal-oxide-semiconductor (M7), the 8th metal-oxide-semiconductor (M8), the 9th metal-oxide-semiconductor (M9), the tenth metal-oxide-semiconductor (M10), the 17 metal-oxide-semiconductor (M17), the grid of each pipe of the 18 metal-oxide-semiconductor (M18) is connected in the 15 node (14), the external biasing circuit of the 15 node (14) is to provide the static direct current electric current of current source load circuit, the drain electrode of the 7th metal-oxide-semiconductor (M7) and the tenth metal-oxide-semiconductor (M10) links to each other with the 3rd node (21) with first node (11) respectively successively, the drain electrode of the 17 metal-oxide-semiconductor (M17) and the drain electrode of the 15 metal-oxide-semiconductor (M15) are connected in the 16 node (19), constitute the second output node (i _On), the drain electrode of the 18 metal-oxide-semiconductor (M18) and the drain electrode of the 16 metal-oxide-semiconductor (M16) are connected in the 17 node (29), constitute the first output node (i _Op);

2 P type metal-oxide-semiconductors: the 19 metal-oxide-semiconductor (Mp8) and the 20 metal-oxide-semiconductor (Mp9), the source class of these 2 metal-oxide-semiconductors meets power supply (V _Dd), and grid connects the 18 node (16) after linking to each other, the 18 node (16) is the Voltage Feedback point of common mode feedback circuit, and the drain electrode of the 19 metal-oxide-semiconductor (Mp8) links to each other with the drain electrode of the 8th metal-oxide-semiconductor (M8) in the current source load circuit after protelum point (13) links to each other with the drain electrode of first metal-oxide-semiconductor (M1); The drain electrode of the 20 metal-oxide-semiconductor (Mp9) links to each other with the drain electrode of the 9th metal-oxide-semiconductor (M9) in the current source load circuit after the drain electrode of second metal-oxide-semiconductor (M2) in the 9th node (23) and the turnover voltage follower links to each other, so that will convert the common-mode point of regulating the current source load circuit behind the current signal from the voltage signal that common mode feedback circuit feeds back to.

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