CN100462932C - Low power SRAM backup repair architecture - Google Patents

Abstract

A Static Random Access Memory (SRAM) cell power architecture. The structure can reduce the power caused by the storage unit of the failed memory array, thereby reducing the power of the whole chip. A circuit for controlling a low reference Voltage (VSS) to a six transistor memory storage unit by an NMOS transistor. A VSS enable signal (VSSEN) circuit decodes which region is verified as having failed. Thus, during the normal interval, the VSSEN signal can disable a defective cell or a local cell by turning off the VSS circuit by turning off the NMOS transistor. Alternatively, during the standby interval, the VSSEN signal may enable a standby cell or a local cell by turning on the NMOS transistor to enable the VSS path.

Description

Low Power Static Random Access Memory Backup Repair Architecture

technical field

The present invention relates to a static random access memory (Static Random Access Memory, SRAM), especially to a power structure of an SRAM storage unit.

Background technique

The main design of SRAM is aimed at minimizing the power consumed by memory array storage cells (cells). Many solutions have been proposed, including reducing the power consumed by the faulty memory storage unit, thereby reducing the power consumed by the entire chip.

U.S. Patent No. 5,703,816 provides a method to reduce the standby current (standby) of faulty storage cells in SRAM by replacing failed columns with redundant columns of memory storage cells before packaging. current). The patent provides a device for shutting down a precharge circuit transistor pair that supplies current to a bit line pair and a memory cell power line circuit for a faulty row of a memory cell array.

US Patent No. 6,175,938 discloses a structure for reducing standby current caused by process defects. After the spare memory cell replaces the failed memory cell, the polysilicon fuses on the V _DD path of each bit line are disconnected to reduce the standby current of the failed memory cell.

US Patent No. 6,097,647 discloses a method, which uses electrical isolation to cut off the irreparable memory storage unit from the power line and the ground line. The method also allows the functioning sub-array of memory storage cells to continue to operate while eliminating the excess standby current of a failed memory storage cell.

These low-power memory array storage cells are composed of static complementary metal-oxide semiconductor (Complementary Metal-Oxide Semiconductor, CMOS) flip-flop (flip-flop) circuits, using a pair of mutually coupled inverters as storage elements . The static power consumption of CMOS flip-flops is actually very small, and the main consumption is caused by contact leakage current. In the circuit including the storage cells of the memory array, power consumption is very critical. For low power specifications, a few fault memory cells are sufficient to generate enough current to exceed the chip's power specification.

Therefore, there is a need for a mechanism that can selectively disable faulty memory cells, thereby reducing leakage current and overall chip power.

Contents of the invention

The main purpose of the present invention is to provide a mechanism to effectively minimize the current caused by a faulty memory cell in a low power SRAM array. A secondary object of the present invention is to provide a device that can be used to detect which storage unit or which region of storage units has a leakage path in the SRAM memory. In order to achieve the above object, the present invention provides a SRAM memory storage unit with a backup repair structure. In this structure, the SRAM memory storage unit is connected to a high reference voltage and a low reference voltage, and has a cutting device, which can cut off the connection between the low reference voltage and the SRAM memory storage unit. According to a kind of SRAM memory storage unit that backup repair structure is arranged according to the present invention, comprise:

A SRAM memory storage unit connected to a high reference voltage and a low reference voltage; characterized in that it also includes

A cut-off device can cut off the connection between the low reference voltage and the SRAM memory storage unit, wherein the device includes:

A low reference voltage start VSSEN circuit including an NMOS transistor, the circuit also includes:

an enable/disable control logic 10 whose output signal EN is connected to the drain terminal of the device 14;

a decoder 12, the output signal TMEN of which is connected to the drain terminal of means 18;

An inverter 16, the output signal TESTMOD is connected to the gate terminal of device 14 and device 18, and the source terminal of device 14 and device 18 is connected to signal VSSEN.

The present invention also provides a method for reducing leakage current generated by faulty storage cells in an SRAM array, the method comprising the following steps:

a: connecting a plurality of SRAM memory storage units in an SRAM array to a high reference voltage and a low reference voltage;

b: test whether the SRAM array has a fault storage unit;

c: when a defective storage unit in the SRAM array is detected, the faulty storage unit is replaced by a normal backup storage unit; and

d: cut off the connection between the low reference voltage and the faulty storage unit by changing the low reference voltage signal, thereby reducing the leakage current from the faulty storage unit, and keeping the overall power structure of the chip unchanged.

The low reference voltage path is controlled by an enable signal (VSSEN), which is used to isolate faulty memory cells under the conditions specified by the array test. The enable signal is also used in low-power SRAMs to decode which memory cells or which bank cells are enabled and which faulty cells are disconnected. Cutting off the path of the faulty storage cell to the low reference voltage and replacing the faulty storage cell with a normal backup storage cell can reduce the power generated by the faulty storage cell, and the faulty backup storage cell can also be disabled (disabled), thereby reducing Chip current and power. Through this method, the leakage current is minimized, thereby reducing the power consumed by the entire chip.

As for the detailed structure of the present invention, application principle, function and effect, then can obtain complete understanding with reference to the explanation that following accompanying drawing is done:

Description of drawings

Fig. 1 is a standard six-transistor (6T) SRAM memory cell structure in the prior art;

Fig. 2 is a six-transistor SRAM storage unit structure of the present invention, wherein a low reference voltage start signal (VSSEN) is attached

FIG. 3 is a block diagram illustrating how to decode the low reference voltage enable signal (VSSEN) to disable a faulty memory cell in the normal memory cell area and activate a memory cell used to replace the faulty memory cell in the spare memory cell area. unit;

Figure 4 is a circuit diagram showing how the enable/disable control logic works for a normal memory storage unit in a low-power SRAM;

5 is a circuit diagram showing how the enable/disable control logic completes the action for the backup memory storage unit in a low-power SRAM;

6 is a diagram illustrating how multiple memory storage cells are connected to a low reference voltage enable signal (VSSEN);

Fig. 7 is a flowchart of the operation of the present invention.

Explanation of reference numerals: WL: word line; BL, BLB: bit line pair; N1-N4, P1, P2: transistor; N11-N14, P11, P12: transistor; 10 control logic; 12 decoder; 14 transistor device ( CMOS switch); 16 inverter; 18 transistor device (CMOS switch); 20 transistor device; 22 transistor device; 24 inverter; 26 fuse; 21 transistor device; 23 transistor device; 25 inverter; 27 inverter ; 29 fuse; 30-n0 memory storage unit row; 40-46 operation flow chart of the present invention.

Detailed ways

Please refer to FIG. 1, which is a standard six-transistor SRAM memory cell. For an ultra-low power SRAM with 8M bit capacity, when its word line (word line, WL) is closed, the standby current of the memory storage unit is less than 20 microamperes at 85°C, and the standby current at room temperature is about Between 1 and 2 microamperes.

Access devices N3 and N4 provide a switchable path for data to and from the storage unit. Except when reading or writing, the word line WL selection signal is usually kept at a low potential state. Two word lines BL, BLB provide the data path. Selection of wordlines and bitlines is done by decoders. Assume that the stored logic "1" is defined as the left side of the flip-flop is in a high potential state, that is to say, N2 is in a closed state.

The operation procedure of the memory storage unit in FIG. 1 is as follows: the word line WL is in a low potential state in the standby state, and N4 and N3 are turned on when receiving a high reference voltage. One of the bit lines BL or BLB is forced to be in a low potential state, while the other bit line remains in a high potential state, so as to complete the writing operation. For example, to write a logic "1", the bit line BLB is forced to a low state. The memory storage cell is designed such that the drains of N1 and N2 can be brought below the threshold voltage. Then N2 is turned off, and the drain voltage of N2 rises due to the current flowing from P2 to N4; N1 is turned on, the word line WL can return to the normal standby low potential, and the memory storage unit writes "1" at the same time.

Please refer to FIG. 2 , which shows the structure of the six-transistor SRAM storage unit of the present invention, wherein a low reference voltage enable signal (VSSEN) is attached. When the memory storage unit does not detect a fault in it, VSSEN is kept at a high potential, and the NMOS transistor included in it is in a conductive state; and the storage unit is activated to read a logic "1", the bit The line pair BLB, BL is initially in a high potential state under a high reference voltage (VCC). When the memory storage cell is selected, the current flows through N11 and N13 to the low reference voltage (VSS), and flows through P12 and N14 to the word line BL. N11 remains on. To read a logic "0", when the memory cell is selected, current flows through N12 and N14 to the low reference voltage VSS, and flows through P11 and N13 to the word line BLB. N12 remains on. When a fault is detected in a memory cell, VSSEN goes low and its NMOS transistor becomes non-conductive, disabling the cell from the memory.

After the memory is manufactured, it is usually tested for the presence of any faulty memory cells. The prior art requires all sub-arrays to be tested. If a memory cell or a region of memory cells is detected to be faulty during testing, the entire subarray is replaced. However, the present invention can narrow the scope to the rows of bit line pairs, that is, only the rows of bit line pairs will be deleted. Please refer to FIG. 3 , which illustrates how to decode VSSEN. Signal EN is an output of control logic 10 and is connected to the drain terminal of device 14 . Signal TMEN is the output of decoder 12 and is connected to the drain terminal of device 18 . Signal TESTMODE is the output of inverter 16 , the output of which is connected to the drain (gate) terminals of device 14 and device 18 . The source terminals of device 14 and device 18 are connected to signal VSSEN. When it is detected that the current exceeds the preset current specification, if the array storage unit is in the normal storage unit interval, it will be replaced by a backup storage unit; and if the array storage unit is in the spare storage unit interval, the array storage unit will be prohibited. storage unit. During the interval of normal memory cells, the signal EN is in a state of high potential except when the memory cell is replaced by a spare memory cell. In the interval of the spare storage unit, the signal EN is in a low potential state except that the storage unit is used to replace a faulty storage unit.

Please refer to FIG. 4 and FIG. 5 , which respectively show how the fuse is used to set the high and low potentials of OUTB and OUT, thereby setting the high and low potentials of the signal EN in FIG. 3 . FIG. 4 shows that if the storage unit in the normal storage unit interval has a fault, the fuse 26 will be burned to disable the storage unit, that is, VSSEN will be at a low potential. EN (OUTB for normal memory cells) is the output of inverter 24 and also the drain of device 22 . If the memory cell is a faulty memory cell, blow fuse 26 connected to the source of device 20 and device 22 so that INITIALB through inverter 24 is inverted to EN. FIG. 5 shows that the storage unit is activated by burning the fuse 29, that is, the VSSEN is at a high potential, and the normal storage unit can be replaced by the spare storage unit. EN (OUT for the spare memory cell) is the output of inverter 27 . The input of the inverter 27 is the output of the inverter 25, which is also the drain terminal of the device 23. If the memory cell is to be used, the fuse 29 connected to the source of the device 21 and the device 23 makes the INITIALB pass to become en. According to the above method, the unused array storage cells will be disabled, so there will be no impact on the standby current. The prior art requires cutting off the two power supply paths of VDD and VSS. However, if the method of the present invention is applied, as long as the VSS power supply path is cut off, only relatively few transistors are needed, so that the power consumption of the chip and the cost of circuit design can be minimized.

Please refer to FIG. 6, which shows that if a faulty memory cell is found, the memory cell row including the faulty memory cell is deleted from the array, and then a normal spare memory cell row is added. In this approach, a low reference voltage enable signal (VSSEN) is connected to each memory cell row, ie, 30 to n0, making the present invention simpler than the prior art.

Please refer to FIG. 7 , which is an operation flowchart of the present invention. According to the present invention, the method comprises the following steps,

40: providing an SRAM of an array of SRAM storage cells, and each storage cell is connected to a high reference voltage and a low reference voltage;

42: Detect whether the SRAM array has a defective storage unit;

44: When a defective storage unit in the SRAM array is detected, the faulty storage unit is replaced by a normal spare storage unit;

46: Disable the fault storage unit by changing the low reference voltage signal, so as to cut off the low reference voltage path.

Thus, the leakage current of the faulty memory cell is reduced without affecting the power structure of other parts of the chip.

However, the above description is only a preferred embodiment of the invention, and is not intended to limit the implementation scope of the invention. That is, all equivalent changes and modifications made in the patent scope of the present invention are covered by the patent scope of the present invention.

Claims (9)

1. A kind of SRAM storage unit with backup repair structure, comprising: A SRAM memory storage unit connected to a high reference voltage and a low reference voltage; characterized in that it also includes A cut-off device can cut off the connection between the low reference voltage and the SRAM memory storage unit, wherein the device includes: A low reference voltage start-up circuit including an NMOS transistor, the circuit also includes: an enable/disable control logic (10) whose output signal (EN) is connected to the drain terminal of the device (14); a decoder (12) whose output signal (TMEN) is connected to the drain terminal of the device (18); An inverter (16), its output signal (TESTMOD) is connected to the gate terminal of device (14) and device (18), the source terminal of device (14) and device (18) is connected to low reference voltage start signal . 2. the SRAM memory storage unit that backup repair structure is arranged as claimed in claim 1, is characterized in that starting described startup/prohibition control logic comprises: means (20), (21); Fuses (26), (29); means (22), (23); The inverters (24), (25) are used to respectively set the high and low potentials of the signal (EN). 3. The SRAM memory storage unit with backup repair structure as claimed in claim 1, characterized in that: said cut-off device can cut off the connection between the low reference voltage and the SRAM memory storage unit to reduce the voltage from the storage unit. leakage current. 4. The SRAM memory storage unit with a backup repair structure as claimed in claim 1, wherein said cut-off device can selectively enable or disable an array storage unit area according to the result of detecting the faulty storage unit. 5. A SRAM array with a backup repair structure, comprising: a plurality of SRAM memory storage cells connected to a high reference voltage and a low reference voltage; a word line decoder connected to the word lines of the plurality of storage units; A bit line selector connected to the bit lines of the plurality of storage cells, characterized in that it also includes: A cut-off device can cut off the connection between the low reference voltage and the SRAM memory storage unit, wherein the device includes: A low reference voltage start-up circuit including an NMOS transistor, the circuit also includes: an enable/disable control logic (10) whose output signal (EN) is connected to the drain terminal of the device (14); a decoder (12) whose output signal (TMEN) is connected to the drain terminal of the device (18); An inverter (16), its output signal (TESTMOD) is connected to the gate terminal of device (14) and device (18), the source terminal of device (14) and device (18) is connected to low reference voltage start signal , to disable the faulty storage unit in the normal storage unit section, and activate the storage unit used to replace the faulty storage unit in the spare storage unit section. 6. The SRAM array with a backup repair structure as claimed in claim 5, wherein the cut-off device is a VSS enable (VSSEN) circuit comprising an N-type complementary metal-oxide-semiconductor (NMOS) transistor. 7. The SRAM array with backup repair structure as claimed in claim 5, characterized in that: said cut-off device can be used to cut off the connection between the low reference voltage and the storage cells of one or more rows, so as to reduce the Leakage current from the row or rows of storage cells. 8. The SRAM array with a backup repair structure as claimed in claim 5, wherein said cut-off device can selectively enable or disable a storage unit area of the array according to the result of detecting the faulty storage unit. 9. A method for reducing the leakage current caused by the fault memory array storage unit in the SRAM array, comprising the steps of: a: connecting a plurality of SRAM storage cells in an SRAM array to a high reference voltage and a low reference voltage; b: Test whether the SRAM array has a faulty storage unit; c: replacing the faulty storage unit with a normal backup storage unit when a defective storage unit in the SRAM array is detected; and d: The failure storage unit is prohibited by the change of the low reference voltage signal, so as to reduce the leakage current from the failure storage unit, so that the overall power structure of the chip remains unchanged.

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