CN100461446C - 在拉伸应变绝缘体上SiGe上的应变SiMOSFET - Google Patents
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Abstract
本发明提供了一种用作形成高性能金属氧化物半导体场效应晶体管器件的模板的半导体结构，提供了一种包括绝缘体上SiGe衬底，该衬底包含位于绝缘层顶上的拉伸应变SiGe合金层；和在所述拉伸应变SiGe合金层顶上的应变Si层。还提供了一种形成所述拉伸应变SGOI衬底已经上述异质结构的相应方法。该方法通过提供直接在绝缘层顶上的拉伸应变SiGe合金层，消除了对应变Si层和下面层中Ge含量的偏好。
Description
发明领域
本发明涉及一种用作形成高性能金属氧化物半导体场效应晶体管(MOSFET)器件的模板的半导体结构，尤其涉及一种包含在拉伸应变绝缘体上SiGe(SGOI)上的应变Si层的异质结构。本发明还提供了一种形成本发明的半导体异质结构的方法。
发明背景
短语“应变硅互补金属氧化物半导体(CMOS)”主要指的是在具有弛豫硅-锗(SiGe)合金层上的薄应变硅(应变Si)层的衬底上制造的CMOS器件。应变Si层中电子和空穴的迁移率已经显示出比体式硅层中更高，且具有应变Si沟道的MOSFET已经试验证明，与在普通的(未应变的)硅衬底上制造的器件相比，显示出增强的器件性能。潜在的性能改善包括增加器件的驱动电流和跨导，以及增加缩放操作电压的能力，而没有牺牲电路速度，以便降低功耗。
应变Si层是在晶格常数大于硅的材料形成的衬底上生长的硅中诱发产生双轴拉伸应力的结果。锗的晶格常数大约比硅大4.2％，SiGe合金的晶格常数与锗的浓度成线性关系。结果，含有原子百分比为50％的锗的SiGe合金的晶格常数约比硅的晶格常数大1.02倍。
Si在这种SiGe衬底上的外延生长将产生承受拉伸应变的Si层，其中下面的SiGe衬底基本上没有应变，或“弛豫”。实现了用于MOSFET应用的应变Si沟道结构的优点的结构和工艺在共同转让的Chu等的美国专利US6059895中公开，它公开了一种形成在SiGe层上有应变Si沟道的CMOS器件的技术。
完全实现应变Si CMOS技术的全部优点的困难是弛豫SiGe层在应变Si层下的存在。如上所述，Si沟道中的应变取决于SiGe合金层的晶格常数。因此，为增加应变和迁移率，需要Ge含量增加的SiGe。然而，在CMOS器件的制造过程中使用高Ge含量(约35原子％或更大)在化学方面存在问题。尤其是，具有高Ge含量的SiGe层可能与多个加工步骤互相作用，比如热氧化，沉积扩散，硅化物形成和退火，所以在CMOS的制造过程中难以保持材料的完整性，且可能最后限制可实现的器件性能提升和器件产量。
共同转让的Rim的美国专利US6603156公开了一种直接在绝缘体上硅衬底的绝缘层顶上形成应变Si层的方法。在＇156专利中公开的方法通过从所述结构完全去除SiGe合金层克服了现有技术中的缺点。虽然＇156专利提供了针对应变Si/弛豫SiGe异质结构的问题的替代例，但仍然需要提供一种消除对应变Si层中高应变和下面的SiGe合金层中Ge含量的偏爱的方法。这种方法将可以继续使用应变Si/SiGe异质结构技术。
发明内容
本发明提供了一种用作形成高性能金属氧化物半导体场效应晶体管(MOSFET)器件的模板的半导体结构。更准确地说，本发明提供了一种异质结构，该结构包含在拉伸应变的绝缘体上SiGe(SGOI)上的应变Si层。在更宽的方面，本发明的结构包含：
绝缘体上SiGe衬底，包含位于绝缘层顶上的拉伸应变SiGe合金层，其中键合界面位于所述拉伸应变SiGe合金层和所述绝缘层之间，衬底位于所述绝缘层下方；和
在所述拉伸应变SiGe合金层顶上的应变Si层。
本发明还提供了一种形成所述拉伸应变的SGOI衬底以及上述异质结构的方法。本发明的方法通过提供直接在绝缘层上的拉伸应变的SiGe合金层，消除了对应变Si层中高应变和下面层中Ge含量的偏爱。
准确地说，且在宽泛的方面，本发明的方法包含步骤：
形成第一多层结构，所述结构包含位于弛豫SiGe合金层上方的拉伸应变SiGe合金层，其中所述拉伸应变SiGe合金含有比所述弛豫SiGe合金层更低的Ge含量；
使所述第一多层结构与在与所述弛豫SiGe合金层相对的表面上的第二多层结构的绝缘层键合，其中键合界面位于所述拉伸应变SiGe合金层和所述绝缘层之间；
去除所述弛豫SiGe合金层。
在一些实施例中，应变Si层可以包括在第一多层结构中，该结构含有拉伸应变SiGe合金层和弛豫SiGe合金层。在这一实施例中，应变Si层位于拉伸应变SiGe合金层和弛豫SiGe合金层之间。在该实施例中，且在去除了弛豫SiGe合金层之后，在拉伸应变绝缘体上SiGe衬底上形成应变Si层时不再需要加工步骤。
在另一实施例中，拉伸应变SiGe合金层直接在弛豫SiGe合金层顶上形成。在该实施例中，在去除了弛豫SiGe合金层之后，应变Si在拉伸应变SiGe合金层顶上形成。
在一些实施例中，在键合之前，至少一个第二半导体层可以在拉伸应变SiGe合金层顶上形成。该实施例可以形成多层异质结构。
在完成上述加工步骤之后，至少一个场效应晶体管(FET)可以在应变Si层顶上形成。
附图说明
图1A-1C是示出了在拉伸应变绝缘体上SiGe(SGOI)衬底上形成含有应变Si层的结构时使用的基本加工步骤的示图(剖面图)。
图2是示出了在图1A-1C中提供的结构顶上形成的FET的示图(剖面图)。
图3是示出了在可以使用图1A-1C所示的加工步骤制成的替代机构顶上形成的FET的示图(剖面图)。
具体实施方式
现在将通过参照本发明的附图更详细地描述本发明，本发明提供了在拉伸应变绝缘体上SiGe衬底上的应变Si层以及制造方法。在没有按比例绘出的附图中，相同和/或对应的元件用相同的附图标记来表示。
现在参照图1A-1C，它们示出了在拉伸应变绝缘体上SiGe衬底上形成应变Si层的本发明中可以采用的基本加工步骤。准确地说，图1A示出了第一多层结构10，该结构包含弛豫SiGe合金层，Si1-yGey层12，位于弛豫SiGe合金层12的表面上的可选应变Si层14，和位于可选应变Si层14上的拉伸应变SiGe合金层，Si1-xGex层16。当在图1A所示的结构中没有可选应变Si层14时，拉伸应变SiGe合金层16直接在弛豫SiGe合金层12的表面上。
在上述化学式中且根据本发明，x小于y，所以拉伸应变SiGe合金层16含有比弛豫SiGe合金层12中更多的硅。因此，拉伸应变SiGe合金16具有与弛豫SiGe合金层12的晶格常数不同的晶格常数。尤其是，拉伸应变SiGe合金层16的晶格常数小于弛豫SiGe合金层12的晶格常数。注意的是弛豫SiGe合金层12的晶格常数通常也大于应变Si层14的晶格常数。
图1A中所示的第一多层结构10通过首先提供弛豫SiGe合金层12作为衬底而形成，所述合金层中形成应变Si14和/或拉伸应变SiGe合金层16。应变Si层14是可选的，不是必须在第一多层结构10中存在。弛豫SiGe合金层12的功能是诱发双轴拉伸应力，该应力在层14和/或层16中产生所需级别的应变。因为对于SiGe合金来说，锗浓度[Ge]和晶格常数之间的关系是线性的，所以在层14和/或层16中诱发的应变量可以通过SiGe合金层12中锗的量调整。
弛豫SiGe合金层12可以通过公知的方法形成，例如外延生长，Czhochralski生长等。因为SiGe合金层具有比硅更大的晶格常数，层14和16承受双轴拉伸，而下面的SiGe合金层12基本上保持没有应变，或是“弛豫的”。在本发明中采用的弛豫SiGe合金层12的厚度可以根据在形成所述合金层中使用的方法变化。然而，通常弛豫SiGe合金层12具有约50至约5000nm的厚度，更典型的是约200至约3000nm的厚度。
在提供了弛豫SiGe合金层12之后，应变Si层14可以任选地在弛豫SiGe合金层12的表面上形成。应变Si层14通过任何普通的外延生长工艺形成。应变Si层14的厚度通常约2至约40nm，更典型的是约10至25nm。在本发明中形成的应变Si层14通常具有比Si的自然晶格常数大约0.01至4.2％的面内晶格常数。
接着，在应变Si层14的表面上，比如图1A所示，或当没有应变Si层14时，直接在弛豫SiGe合金层12的表面(未示出)上形成拉伸应变SiGe合金层16。拉伸应变SiGe合金层16可以通过任何方法形成，包括例如外延生长。本发明此时形成的拉伸应变SiGe合金层16通常具有约5至300nm的厚度，更典型的是约10至100nm的厚度。拉伸应变SiGe合金层16通常含有约1-99原子％的Ge的Ge含量，但Ge含量小于弛豫SiGe合金层12中的Ge含量。
虽然在图1A-1C的工艺流程图中没有示出，但本发明此时可以在拉伸应变SiGe合金层16顶上形成一或多个可选的第二半导体层。所述一或多个可选半导体层可以利用本领域技术人员公知的普通沉积工艺形成，包括例如外延生长，化学气相沉积，蒸发，等离子增强的化学气相沉积等。本发明此时可以形成的一或多个可选半导体层的说明性示例包括，但不限于：Si，SiGe，Ge，GaAs，InAs，InP或其他III/V和II/VI族化合物半导体，包括多层。所述一或多个可选的第二半导体层的厚度可以根据所采用的第二半导体材料的数目变化。通常，所述一或多个第二半导体层具有约5至约300nm的总厚度，更典型的是约10至约100nm。所述一或多个可选的第二半导体层的存在可以形成含有多个异质结构层的结构。图3示出了第二半导体材料的存在。在该图中，第二半导体材料用附图标记26标出。
在提供了图1A所示的第一多层结构10之后，第二多层结构18(见图1B)形成，它包括在衬底22上的绝缘层20，所述衬底至少最初用作绝缘层20的搬运晶片。在下面更为明显，可以预见在绝缘层20和衬底22之间或在衬底的背面(与绝缘层20相对)上包括多种材料形成的一或多个层。
绝缘层20包含氧化物、氮化物、氮氧化物或其任何组合。可以用作绝缘层20的材料的说明性示例包括，但不限于：二氧化硅(硅石，SiO2)，氮化硅(SiN)，氧化铝(矾土；Al2O3)，氮氧化硅，氧化铪(二氧化铪，HfO2)，氧化锆(锆土，ZrO2)，和掺杂的氧化铝。可取的是，绝缘层20是氧化物。绝缘层20的厚度通常约1至约1000nm，更典型的是约10至约300nm的厚度。绝缘层20在衬底22的表面上使用普通的沉积工艺形成，比如CVD，PECVD，蒸发化学溶液沉积，原子层沉积等。或者，绝缘层20可以通过热氧化，热氮化或其组合在衬底22顶上形成。
在本发明中采用的衬底22由任何半导体材料形成，包括例如Si，SiGe，Ge，GaAs，InAs，InP或其他III/V和II/VI化合物半导体。衬底22也可由层状半导体形成，比如Si/SiGe或预成形的绝缘体上硅(SOI)或绝缘体上SiGe(SGOI)衬底。衬底22的厚度对本发明来说无关紧要。
应当注意的是用作层12，14，16，22的半导体材料可以具有相同的晶向或它们可以具有不同的晶向。
第二多层结构18与第一多层结构10键合，从而提供图1B所示的键合结构24。准确地说，第二多层结构18的绝缘层20的暴露上表面键合在多层结构10的拉伸应变的SiGe合金层16的暴露上表面上。
两个多层结构之间的键合包括任何普通键合方法，包括半导体-绝缘体键合。例如，上述两个多层结构的键合可以在本发明中通过首先使两结构互相密切接触；然后可选地向接触的结构施加外力而完成。所述两个多层结构可以在接触之后在能够增加两结构之间的键合能的条件下可选地退火。退火步骤可以在有或没有外力时完成。键合通常在标称室温下在最初接触步骤中完成。标称室温指的是约15℃至约40℃的温度，更优选的是约25℃。虽然通常在这些温度下完成键合，但也可以想到标称值以上的其他温度。
在键合之后，键合结构24可以再次退火，从而提高键合强度，改善界面特性。再次退火温度通常在约900°至约1300℃，更典型的是约1000°至约1100℃的退火温度。在上述温度范围内进行多个时间段的退火，可以从约1小时至约24小时。退火气氛可以是O2，N2，Ar或低真空，有或没有外部粘结力。也可以想到上述退火气氛的混和，有或没有惰性气体。虽然经常使用高温退火(如上所述)，也可以使用低温退火(小于900℃)，也可以实现良好的机械和电学性能。
在形成图1B中所示的键合结构24之后，从所述结构去除弛豫SiGe层12，从而露出下面的应变Si层14，如果有的话，或拉伸应变SiGe合金层16，如果应变Si层14不存在的话。图1C示出了在去除弛豫SiGe合金层12之后露出应变Si层14的结构。
弛豫SiGe合金层12通过比如化学-机械抛光(CMP)，晶片劈裂(比如可以从LETI得到的SmartCut工艺)，对硅具有选择性的化学蚀刻工艺，或这些技术的组合方法完全去除。当存在应变Si层14时，完全去除驰豫SiGe层12的优选方法是选择性化学蚀刻工艺，比如HHA(过氧化氢，氢氟酸，醋酸)蚀刻，该工艺择优地蚀刻SiGe合金层12。当驰豫SiGe合金层12直接接触拉伸应变的SiGe合金层16时，通常进行CMP或晶片劈裂。如果使用SmartCut工艺，那么该工艺所需的氢注入步骤可以在本发明的工艺中多个时点进行。
在事先不存在应变Si层14的实施例中，应变Si层14可以在本发明此时通过外延生长在露出的拉伸应变SiGe合金层16顶上形成。
在形成应变Si-SGOI结构之后，一或多个场效应晶体管(FET)可以在应变Si层14的表面顶上形成，提供图2和3所示的结构。在这些附图中，为清楚起见，衬底22已经省略，附图标记50指的是FET区，附图标记52指的是栅电介质，附图标记54指的是栅极导体，附图标记56指的是侧壁分隔层。FET50利用本领域技术人员公知的普通CMOS加工步骤在应变Si层14顶上形成。栅极电介质52的材料(氧化物，氮化物，氮氧化物或其组合)，栅极导体54(多晶Si，金属，金属合金，硅化物或其组合)，侧壁分隔层56(氧化物，氮化物，氮氧化物或其组合)是本领域技术人员公知的。应变Si层14的在栅极区域50下面的部分用作器件沟道。源极/漏极延伸部分和扩散区域(未示出)可以通过普通的离子注入和退火在应变Si层14内形成。硅化物触点和/或凸起的源极/漏极区域也可以通过本领域技术人员公知的普通方法形成。在上述加工步骤之后，也可以在图2和3所示的结构上进行普通的线后端(BEOL)加工。在图2和3中所示的示例性结构是相同的，除了在拉伸应变SiGe合金层16和绝缘层20之间有第二半导体层26之外。
强调的是上述本发明的方法消除了应变Si层14中高应变和下面的拉伸应变SiGe合金层16中Ge含量的偏爱。在图2和3所示的结构中，在应变Si层14下面的拉伸应变SiGe合金层16用作应变Si层14的模板。
虽然已经参照优选实施例具体示出和描述了本发明，但本领域的技术人员应当理解，可以在形式和细节上作出前述和其他变化，而没有脱离本发明的主旨和范围。所以，本发明不限于所述和所示的确切形式和细节，而是落入所附权利要求的主旨和范围内的。
Claims (25)
1.一种半导体结构，包含：
绝缘体上SiGe衬底，包含位于绝缘层顶上的拉伸应变SiGe合金层，其中键合界面位于所述拉伸应变SiGe合金层和所述绝缘层之间，衬底位于所述绝缘层下方；和
在所述拉伸应变SiGe合金层顶上的应变Si层。
2.如权利要求1所述的半导体结构，其特征在于，所述绝缘层包含氧化物、氮化物、氮氧化物或其任何组合。
3.如权利要求2所述的半导体结构，其特征在于，所述绝缘层是氧化物。
4.如权利要求1所述的半导体结构，其特征在于，所述绝缘层具有1至1000nm的厚度。
5.如权利要求1所述的半导体结构，其特征在于，所述拉伸应变SiGe合金层包含1.0至99原子％的Ge。
6.如权利要求1所述的半导体结构，其特征在于，所述拉伸应变SiGe合金层具有5至300nm的厚度。
7.如权利要求1所述的半导体结构，其特征在于，还包含至少一个在所述拉伸应变SiGe合金层和所述绝缘层之间的第二半导体材料。
8.如权利要求7所述的半导体结构，其特征在于，所述至少一个第二半导体材料包含Si，SiGe，Ge，GaAs，InAs，InP或其他III/V和II/VI族化合物半导体。
9.如权利要求1所述的半导体结构，其特征在于，所述衬底包含Si，SiGe，Ge，GaAs，InAs，InP或其他III/V和II/VI族化合物半导体。
10.如权利要求1所述的半导体结构，其特征在于，还包含至少一个位于所述应变Si层上的场效应晶体管。
11.一种形成半导体结构的方法，包含如下步骤：
形成第一多层结构，所述结构包含位于弛豫的SiGe合金层上方的至少一层拉伸应变的SiGe合金层，其中所述拉伸应变的SiGe合金含有比所述弛豫SiGe合金层更低的Ge含量；
使所述第一多层结构与在与所述弛豫SiGe合金层相反的表面上的第二多层结构的绝缘层键合，其中键合界面位于所述拉伸应变SiGe合金层和所述绝缘层之间；
去除所述弛豫SiGe合金层。
12.如权利要求11所述的方法，其特征在于，所述第一多层结构还包括在所述拉伸应变SiGe合金层和所述驰豫SiGe合金层之间的应变Si层。
13.如权利要求11所述的方法，其特征在于，所述拉伸应变SiGe合金通过外延生长形成。
14.如权利要求12所述的方法，其特征在于，所述应变Si层承受双轴拉伸应变。
15.如权利要求11所述的方法，其特征在于，所述键合包含使所述第一和所述第二多层结构接触。
16.如权利要求15所述的方法，其特征在于，还包含在所述接触过程中对所述第一和所述第二多层结构施加外力。
17.如权利要求15所述的方法，其特征在于，所述接触过程发生在15℃至40℃的温度或大于40℃的温度下。
18.如权利要求15所述的方法，其特征在于，还包含在所述接触之后的退火步骤。
19.如权利要求11所述的方法，其特征在于，所述去除所述驰豫SiGe合金层的过程包含化学机械抛光，晶片劈裂，化学蚀刻或其组合。
20.如权利要求11所述的方法，其特征在于，还包含在所述的去除所述驰豫SiGe合金层之后在所述拉伸应变SiGe合金的顶上形成应变Si层。
21.如权利要求20所述的方法，其特征在于，还包含在所述应变Si层上形成至少一个场效应晶体管。
22.如权利要求12所述的方法，其特征在于，还包含在所述的去除所述驰豫SiGe合金层之后在所述应变Si层上形成至少一个场效应晶体管。
23.如权利要求11所述的方法，其特征在于，所述第二多层结构至少包括衬底。
24.一种形成半导体结构的方法，包含如下步骤：
形成第一多层结构，所述结构包含位于弛豫的SiGe合金层上方的拉伸应变的SiGe合金层和应变Si层，其中所述拉伸应变的SiGe合金含有比所述弛豫SiGe合金层更低的Ge含量；
使所述第一多层结构与在与所述弛豫SiGe合金层相反的表面上的第二多层结构的绝缘层键合，其中键合界面位于所述拉伸应变SiGe合金层和所述绝缘层之间；
去除所述弛豫SiGe合金层，露出所述应变Si层的表面。
25.如权利要求24所述的方法，其特征在于，还包含在所述应变Si层的所述露出表面上形成至少一个场效应晶体管。
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Also Published As
| Publication number | Publication date |
|---|---|
| US7507989B2 (en) | 2009-03-24 |
| TW200618277A (en) | 2006-06-01 |
| TWI344209B (en) | 2011-06-21 |
| US8017499B2 (en) | 2011-09-13 |
| US20060001088A1 (en) | 2006-01-05 |
| US20070155130A1 (en) | 2007-07-05 |
| US7217949B2 (en) | 2007-05-15 |
| US20080042166A1 (en) | 2008-02-21 |
| JP2006019725A (ja) | 2006-01-19 |
| CN1716629A (zh) | 2006-01-04 |
| US7485518B2 (en) | 2009-02-03 |
| JP4959153B2 (ja) | 2012-06-20 |
| US20080220588A1 (en) | 2008-09-11 |
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