CN100460940C - Method for Improving Electromagnetic Interference of Liquid Crystal Display and Timing Controller - Google Patents

Abstract

The invention discloses a method for improving electromagnetic interference of a liquid crystal display. In the point-to-point transistor transistor logic interface between a timing controller and a source driver, the timing controller is used to provide a first frequency signal and a second frequency signal, and the first frequency The phase of the signal is different from that of the second frequency signal. The timing controller transmits a plurality of first image data to the source driver according to the first frequency signal, and transmits a plurality of second image data to the source driver according to the second frequency signal.

Description

Method for Improving Electromagnetic Interference of Liquid Crystal Display and Timing Controller

technical field

The invention relates to the technical field of liquid crystal displays, in particular to a method suitable for improving electromagnetic interference of liquid crystal displays.

Background technique

Generally speaking, the transistor-transistor logic (TTL) transmission interface between the timing controller and the source driver in a thin-film-transistor liquid crystal display (TFT LCD) will cause serious power failure due to the need for more data buses to transmit images. Power consumption and electromagnetic interference (ElectromagneticInterfering, EMI) phenomenon.

FIG. 1 is a block diagram of a conventional transistor-transistor logic interface transmission timing controller 1 . In order to improve the power consumption and electromagnetic interference between the timing controller 1 and the source driver, the timing controller 1 shown in FIG. 1 transmits the image data to the source driver using a dual port transmission method. If the grayscale resolution is 8 bits, 48 data bus lines (Data Bus Lines) (8bit x 3RGB x 2Dual port = 48) are required. In addition, in order to correspond to two sets of input low-voltage differential signals (LVDS), The output terminal of the timing controller 1 includes two sets of data buses, namely ETDA[47:0] and ODTA[47:0].

FIG. 2 is a block diagram of a conventional point-to-point transistor-transistor logic (PPTTL) interface transmission timing controller 2, which can improve the problem of utilizing too many data buses in FIG. 1 . In FIG. 2 , the timing controller 2 transmits the image data to the source driver in a point-to-point transmission manner. If the number of source drivers used by the display panel module is 10, only 30 data buses are required (10 sourcedriver ICs x 3 RGB=30). In addition, the data bus line required by the point-to-point transmission mode has nothing to do with the display gray scale (6/8 bit), so it can show the advantages of the point-to-point transmission mode even more when applied to high-end display systems. Although the point-to-point transistor-transistor logic transmission method can effectively reduce the number of used data bus lines, for large-sized display panels, the data deformation caused by the point-to-point transistor-transistor logic transmission method is more serious.

FIG. 3 is a schematic diagram of a conventional panel module using a dual-port transmission mode. In FIG. 3 , the display panel 3 is divided into a first display part 31 and a second display part 32, and the timing controller transmits the image data to the source driver through a dual-port transmission mode, so that the source driver can transfer the image The data is transmitted to the first display part 31 and the second display part 32 respectively (transmission on both sides), and by reducing the frequency signal CLK, the power consumption and electromagnetic interference problems are improved.

FIG. 4 is a timing diagram of a conventional dual-port transmission method. In FIG. 4 , the dual-port transmission method utilizes a set of frequency signals CLK1 to respectively control the transmission of two sets of image data, for example, the first sampling waveform controls the transmission of image data A and image data B. Therefore, the frequency signal can be halved by using the dual-port transmission method to transmit the image data. However, the size of the current display panel is getting larger and larger, which greatly improves the resolution of the display panel, which also increases the frequency signal, so the use of dual-port transmission to transmit image data still cannot effectively solve the problem of power consumption and Electromagnetic Interference Problems.

Contents of the invention

The object of the present invention is to provide a method for improving the electromagnetic interference of a liquid crystal display, which can achieve better power consumption and electromagnetic interference performance characteristics.

In order to achieve the above object, the present invention provides a method for improving the electromagnetic interference of a liquid crystal display, the method comprising the following steps: (A) receiving several image data according to the fifth frequency signal; (B) providing the first frequency signal and The second frequency signal, the frequencies of the first frequency signal and the second frequency signal are smaller than the fifth frequency signal, and the phase of the first frequency signal is different from the phase of the second frequency signal; and (C) transmitting according to the first frequency signal A plurality of first image data, and a plurality of second image data are transmitted according to the second frequency signal, the first image data and the second image data are all from the image data.

In order to achieve the above object, the present invention provides a method for improving the electromagnetic interference of a liquid crystal display, which is applicable to a liquid crystal display panel module, and the method includes the following steps: (A) receiving several image data according to a fifth frequency signal ; (B) using a timing controller to provide a first frequency signal and a second frequency signal to several source drivers, the frequency of the first frequency signal and the second frequency signal is lower than the fifth frequency signal, and the first frequency signal The phase of the second frequency signal is different from that of the second frequency signal; and (C) the timing controller transmits a plurality of first image data to the source driver with the first frequency signal, and the timing controller also transmits a plurality of first image data with the second frequency signal Two image data to the source driver.

In one embodiment of the present invention, in step (C), the timing controller also transmits a plurality of third image data to the source driver with a first frequency signal, and the phase of the first image data is the same as that of the third image data The phases of the image data are different. In addition, in another embodiment of the present invention, the timing controller also transmits a plurality of fourth image data to the source driver with a second frequency signal, and the phase of the second image data is the same as the phase of the fourth image data different.

In another embodiment of the present invention, in the step (B), the timing controller further provides a third frequency signal and a fourth frequency signal, and the frequency of the third frequency signal and the fourth frequency signal is lower than that of the fifth frequency signals, and the phases of the first frequency signal, the second frequency signal, the third frequency signal, and the fourth frequency signal are all different. In another embodiment of the present invention, in this step (C), the timing controller also transmits several fifth image data with the third frequency signal, and the timing controller transmits several sixth image data with the fourth frequency signal data.

In order to achieve the above object, the present invention provides a timing controller for a liquid crystal display panel module, electrically connected to several source drivers, used in a liquid crystal display panel module, including: a receiving unit, according to the fifth frequency signal Receiving several image data; a data processing logic unit electrically connected to the receiving unit and the source driver; and a multi-phase frequency signal generating unit electrically connected to the receiving unit and the data processing logic unit to provide a first frequency signal and a second frequency signal , the frequencies of the first frequency signal and the second frequency signal are smaller than the fifth frequency signal, and the phase of the first frequency signal is different from the phase of the second frequency signal; wherein, the data processing logic unit transmits a first The image data is sent to the source driver, and a piece of second image data is transmitted to the source driver according to the second frequency signal.

In an embodiment of the present invention, the data processing logic unit further transmits a plurality of third image data to the source driver with the first frequency signal, and the phase of the first image data is different from that of the third image data. In addition, in another embodiment of the present invention, the data processing logic unit also transmits a plurality of fourth image data to the source driver with a second frequency signal, and the phase of the second image data is different from that of the fourth image data.

In another embodiment of the present invention, the polyphase frequency signal generation unit also provides a third frequency signal and a fourth frequency signal, the frequencies of the third frequency signal and the fourth frequency signal are lower than the fifth frequency signal, and the first frequency signal The phase of the second frequency signal, the phase of the third frequency signal and the phase of the fourth frequency signal are all different.

In another embodiment of the present invention, the data processing logic unit also transmits a plurality of fifth image data with a third frequency signal, and the data processing logic unit transmits a plurality of sixth image data with a fourth frequency signal.

From the above, it can be seen that the method for improving the electromagnetic interference of the liquid crystal display in the present invention can indeed solve the problems of power consumption and electromagnetic interference in the prior art.

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

Description of drawings

Fig. 1 is the block diagram of the timing controller of known transistor-transistor logic interface transmission;

Fig. 2 is the block diagram of the timing controller of known point-to-point transistor transistor logic interface transmission;

FIG. 3 is a schematic diagram of a known panel module using a dual-port transmission mode;

FIG. 4 is a known sequence diagram utilizing a dual-port transmission mode;

Figure 5a is a functional block diagram of a preferred embodiment of the present invention;

Figure 5b is a block diagram further showing the internal functions of the timing controller;

Fig. 6 is a sequence diagram of the first embodiment;

Fig. 7 is the timing diagram of the second embodiment;

Fig. 8 is a timing diagram of the third embodiment.

Among them, reference signs:

Timing Controller 1, 2, 5 Display Panel 3

The first display part 31 The second display part 32

Internal oscillation frequency signal generation unit 51 Spread spectrum frequency signal unit 52

Multi-phase frequency signal generating unit 53 Data processing logic unit 54

Line Buffer Unit 55 Data Latch Logic Unit 56

Low voltage differential signal receiving unit 57

Source Driver 61, 62, 63

Frequency signal 611, 612, 613, 614

Image data 621, 622, 623, 624, 625, 626

Detailed ways

For a preferred embodiment of the present invention, please refer to the functional block diagram shown in FIG. 5 a , which includes a timing controller 5 and several source drivers 61 , 62 , 63 . In addition, the timing controller 5 is electrically connected to the source drivers 61 , 62 , 63 .

Fig. 5b further shows the internal functional block diagram of the timing controller 5, which includes an internal oscillation frequency signal generating unit 51, a spread spectrum frequency signal unit (Spread Spectrum CLK Unit) 52, and a multi-phase frequency signal generating unit (Multi-Phase CLK Generator) 53 . A data processing logic unit 54 , a line buffer unit 55 , a data latch logic unit 56 and a low voltage differential signal receiving unit 57 .

Both the internal oscillation frequency signal generating unit 51 and the low voltage differential signal receiving unit 57 are electrically connected to the spread spectrum frequency signal unit 52 . The low voltage differential signal receiving unit 57 is also electrically connected to the data latch logic unit 56 . The spread spectrum frequency signal unit 52 is electrically connected to the multiphase frequency signal generating unit 53 . Both the multi-phase frequency signal generation unit 53 and the data latch logic unit 56 are electrically connected to the data processing logic unit 54 . The data processing logic unit 54 is electrically connected to the line buffer unit 55 . In addition, the multi-phase frequency signal generation unit 53 and the data processing logic unit 54 are electrically connected to the source drivers 61 , 62 , 63 respectively.

The above-mentioned low-voltage differential signal receiving unit 57 receives several pieces of image data, and then transmits the image data to the data latch logic unit 56 for temporary storage, while the CLK frequency signal is transmitted to the spread spectrum frequency signal unit 52. In this embodiment , Spread spectrum frequency signal unit 52 comprises a phase-locked loop (Delay Locked Loop) (not shown in the figure), more precisely, the phase-locked loop of the present embodiment is a phase-locked loop (PLL), and it controls a delay circuit (not shown in the figure) to compare several frequency signals with different phases with the CLK frequency signal to synchronize the phase of the output frequency signal with the frequency signal, and then, the frequency signal synchronized with CLK is transmitted to the above-mentioned multi-phase frequency signal generation Unit 53, which provides an array of frequency signals with different phases to these source drivers 61, 62, 63 according to the frequency signal synchronized with CLK, and the above-mentioned data processing logic unit 54 according to the different phase frequencies from the multi-phase frequency signal generation unit 53 The signal outputs several pieces of image data to these source drivers 61 , 62 , 63 .

Next, please refer to the timing diagram of the first embodiment shown in FIG. 6 , and for its description, please refer to FIG. 5 a and FIG. 5 b together.

In FIG. 6, the low-voltage differential signal receiving unit 57 of the timing controller 5 receives several pieces of image data according to the CLK frequency signal, and the multi-phase frequency signal generating unit 53 provides frequency signals 611, 612 to these source drivers 61, 62 , 63, and the data processing logic unit 54 of the timing controller 5 outputs image data 621, 622 to these source drivers 61, 62, 63, wherein the frequencies of the frequency signal 611 and the frequency signal 612 are less than the CLK frequency signal, and the frequency signal 611 Different from the phase of the frequency signal 612 , the timing controller 5 uses a phase offset method to make the phase of the frequency signal 611 and the frequency signal 612 different.

If the phases of the frequency signal 611 and the frequency signal 612 are the same, the electromagnetic interference waveforms generated on the upper and lower edges of each frequency waveform will be accumulated, that is, when the frequency waveforms of the frequency signals 611 and 612 are switched, Because the frequency signal 611 is affected by the noise generated by the frequency signal 612, and accumulates electromagnetic interference energy, similarly, for the frequency signal 612, it is also affected by the noise generated by the frequency signal 611 when the frequency waveform is switched, and accumulates Electromagnetic interference energy, which will cause serious electromagnetic interference problems. Therefore, in this embodiment, the timing controller 5 provides frequency signals 611 , 612 with different phases, so as to reduce the accumulated energy of electromagnetic interference, so that the problem of electromagnetic interference can be improved. In addition, the timing controller 5 transmits the image data 621 to the source drivers 61 , 62 , 63 with the frequency signal 611 , and transmits the image data 622 to the source drivers 61 , 62 , 63 with the frequency signal 612 . It should be noted here that since the phases of the frequency signal 611 and the frequency signal 612 are different, the phases of the image data 621 and the image data 622 are also different accordingly. In this way, the energy problem accumulated by electromagnetic interference can be dispersed, and the power consumption and electromagnetic interference problems of the power supply can be improved.

FIG. 7 is a timing diagram of the second embodiment of the present invention. For its description, please refer to FIG. 5a and FIG. 5b together.

The operation of this embodiment is similar to the above-mentioned first embodiment, except that the multi-phase frequency signal generation unit 53 of the timing controller 5 provides frequency signals 611, 612, and the data processing logic unit 54 of the timing controller 5 outputs image data 621 , 622, 623, 624 to these source drivers 61, 62, 63, wherein the image data 621 is in a different phase from the image data 623, and the image data 622 is in a different phase from the image data 624.

Thereby, the timing controller 5 can transmit image data 621, 623 to these source drivers 61, 62, 63 through the frequency signal 611, and transmit image data 622, 624 to these source drivers 61, 62 through the frequency signal 612. , 63, to improve power consumption and electromagnetic interference problems.

FIG. 8 is a timing diagram of the third embodiment of the present invention. For its description, please refer to FIG. 5a and FIG. 5b together.

The operation of this embodiment is similar to the above-mentioned first embodiment, the multiphase frequency signal generating unit 53 of the timing controller 5 provides a plurality of frequency signals 611, 612, 613, 614, and its data processing logic unit 54 outputs image data 621 , 622, 625, 626 to these source drivers 61, 62, 63, wherein the frequencies of the frequency signal 611, the frequency signal 612, the frequency signal 613 and the frequency signal 614 are all less than the CLK frequency signal, and the frequency signal 611, the frequency signal 612, The phases of the frequency signal 613 and the frequency signal 614 are different.

Thereby, the timing controller 5 can transmit the image data 621 to these source drivers 61, 62, 63 through the frequency signal 611, transmit the image data 622 to these source drivers 61, 62, 63 through the frequency signal 612, and transmit the image data 622 to these source drivers 61, 62, 63 through the frequency signal 612. The signal 613 transmits the image data 625 to these source drivers 61 , 62 , 63 , and the frequency signal 614 transmits the image data 626 to these source drivers 61 , 62 , 63 . In addition, since the phases of the frequency signals 611, 612, 613, 614 are all different, the phases of the image data 621, 622, 625, 626 are also different accordingly. In this way, the problems of power consumption and electromagnetic interference can be improved.

It can be seen from the above description that the present invention achieves better power consumption and electromagnetic interference characteristics by changing the frequency signal and the phase change of the data.

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding changes All changes and modifications should belong to the scope of protection of the appended claims of the present invention.

Claims (16)

1. A method for improving the electromagnetic interference of liquid crystal display, applicable to a point-to-point transistor transistor logic interface in a liquid crystal display panel module, is characterized in that, the method may further comprise the steps: (A) receiving a plurality of image data according to a fifth frequency signal; (B) using a timing controller to provide a first frequency signal and a second frequency signal to several source drivers, the frequency of the first frequency signal and the second frequency signal is lower than the fifth frequency signal, and the first frequency signal the phase of the first frequency signal is different from the phase of the second frequency signal; and (C) The timing controller transmits a plurality of first image data to the source drivers with the first frequency signal, and the timing controller also transmits a plurality of second image data to the source drivers with the second frequency signal , the first image data and the second image data are all from the image data. 2. The method according to claim 1, wherein in the step (C), the timing controller also transmits a plurality of third image data to the source drivers with the first frequency signal, and the first The phase of an image data is different from the phases of the third image data. 3. The method according to claim 1, wherein in the step (C), the timing controller also transmits a plurality of fourth image data to the source drivers with the second frequency signal, and the first The phases of the second image data are different from those of the fourth image data. 4. The method according to claim 1, wherein in the step (B), the timing controller also provides a third frequency signal and a fourth frequency signal, the third frequency signal and the fourth frequency signal The frequency of the frequency signal is smaller than the fifth frequency signal, and the phases of the first frequency signal, the second frequency signal, the third frequency signal and the fourth frequency signal are all different. 5. The method according to claim 4, wherein, in the step (C), the timing controller also transmits a plurality of fifth image data with the third frequency signal. 6. The method according to claim 5, wherein in the step (C), the timing controller also transmits a plurality of sixth image data by the fourth frequency signal. 7. A timing controller for a liquid crystal display panel module, which is electrically connected to several source drivers with a point-to-point transistor logic interface, it is characterized in that the timing controller includes: A receiving unit, receiving a plurality of image data according to a fifth frequency signal; a data processing logic unit electrically connected to the receiving unit and the source drivers; and A multi-phase frequency signal generating unit, electrically connected to the receiving unit and the data processing logic unit, to provide a first frequency signal and a second frequency signal, the frequencies of the first frequency signal and the second frequency signal are lower than the frequency of the first frequency signal Five frequency signals, and the phase of the first frequency signal is different from the phase of the second frequency signal; Wherein, the data processing logic unit transmits a piece of first image data to the source drivers according to the first frequency signal, and transmits a piece of second image data to the source drivers according to the second frequency signal. 8. The timing controller according to claim 7, wherein the data processing logic unit also transmits a plurality of third image data to the source drivers with the first frequency signal, and the phase of the first image data The phases of these third image data are different. 9. The timing controller according to claim 7, wherein the data processing logic unit also transmits a plurality of fourth image data to the source drivers with the second frequency signal, and the phase of the second image data The phases of these fourth image data are different. 10. The timing controller according to claim 7, wherein the multi-phase frequency signal generating unit further provides a third frequency signal and a fourth frequency signal, the third frequency signal and the fourth frequency signal The frequency is lower than the fifth frequency signal, and the phases of the first frequency signal, the second frequency signal, the third frequency signal and the fourth frequency signal are all different. 11. The timing controller according to claim 10, wherein the data processing logic unit also transmits a plurality of fifth image data with the third frequency signal, and the data processing logic unit transmits with the fourth frequency signal A number of sixth image data. 12. The timing controller according to claim 7, further comprising a data latch logic unit electrically connected between the receiving unit and the data processing logic unit, and the data latch logic unit The image data received by the receiving unit is temporarily stored. 13. The timing controller according to claim 12, wherein the data latch logic unit is a memory. 14. The timing controller according to claim 12, wherein the data latch logic unit is a latch register. 15. The timing controller according to claim 12, wherein the data latch logic unit is a buffer. 16. The timing controller according to claim 7, further comprising: A spread spectrum frequency signal generating unit, which is electrically connected to the multi-phase frequency signal generating unit; and An internal oscillation frequency signal generation unit, which is electrically connected to the spread spectrum frequency signal generation unit; Wherein, the fifth frequency signal is input to the spreading frequency signal generating unit.

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