CN100440294C - Liquid crystal display unit with input pixel data readjusting circuit - Google Patents

Abstract

The present invention provides a liquid crystal display (LCD) panel unit with a plurality of source drivers, which are functionally divided into first and second source driver groups assigned to the first half and second half of the LCD panel, respectively. two and a half. In order to drive the LCD panel correctly regardless of whether the format of the input pixel data is different, a pixel data readjustment circuit for readjusting the format of the input pixel data to a predetermined data format is provided. The data readjustment circuit is before the first and second source driver groups, and its function is, for example, to receive 2N channels (N is a natural number) of pixel data, and readjust the 2N channels of pixel data according to a predetermined data format The readjusted N channels of pixel data are provided to the first source driver group, and the readjusted N channels of pixel data are provided to the second source driver group.

Description

Liquid crystal display unit with input pixel data readjustment circuit

field of invention

The present invention relates generally to an active matrix addressable liquid crystal display (LCD) unit, and more particularly to a unit having pixel data reordering circuitry for reordering incoming pixel data into a predetermined format for correct Drives the LCD panel.

related technology

LCDs have been widely used in various electronic devices such as television receivers, personal computers, personal digital assistants (PDAs), mobile phone terminals, image monitors, and the like. Among them, the active matrix addressing LCD has been widely used, and it has a plurality of active elements (switching elements), correspondingly assigned to each pixel electrode, for controlling the voltage applied to it. Such active elements are typically thin film transistors (TFTs). Active matrix addressable LCD has outstanding features such as high resolution, wide viewing angle, high contrast ratio, and multiple gray levels.

With the continuous development of LCD manufacturing technology, the LCD panel becomes larger and larger, while maintaining or increasing the pixel density, which is the current development trend. As a result, the number of pixels per line continues to increase, increasing the need for higher clock frequencies. However, with the increase of the clock frequency, the traditional LCD device encounters the difficulty that the manufacturing cost of the source driver is higher and higher, and the problem of EMI (Electromagnetic Interference) becomes more and more prominent.

To solve the above-mentioned problems, it has been proposed to divide the source drivers into two groups and supply pixel data to them in parallel. It is therefore possible to halve the clock frequency. Such proposals are disclosed in Japanese Patent Application Nos. 5-210359 and 10-207434.

Before describing the present invention, the conventional art disclosed in the aforementioned Japanese Patent Application No. 5-210359 will be briefly described by referring to FIG. 1 .

FIG. 1 is a block diagram showing an LCD panel 2 and its periphery. Around the LCD panel 2 there are multiple source drivers 3 for driving the thin film transistors in the array in the LCD panel 2 . The source drivers 3 are divided into two groups: one group 3L is assigned to the left half of the liquid crystal display panel 2 , and the other group 3R is assigned to the right half of the liquid crystal display panel 2 . One channel of pixel data is provided to the interface 4. Here, the input pixel data is divided into two channels of pixel data S1 and S2 by using the clock signal CK1. This clock signal CK1 is also supplied to the frequency divider 5, the clock rate of the clock signal CK1 is reduced by half, and the halved clock frequency (rate) is issued as the clock signal CK2.

The two channels of pixel data S1 and S2 are provided to the controller 6 by using the clock signal CK2, and these data are respectively provided as S1U and S2U to the source driver groups 3L and 3R. In addition, the controller 6 prepares a sampling start signal SP using the pixel data S1 or S2, and supplies this signal SP to the source driver at the front of each group of drivers 3L and 3R. Thus, pixel data S1U and S2U are displayed in parallel. As described above, this prior art is characterized in that the source drive clock frequency can be halved. This means that it is possible to drive a large LCD panel without increasing the clock frequency, alleviating EMI problems at the same time.

As mentioned above, in the prior art mentioned above, a single channel of pixel data is divided into two channels of pixel data to be provided to the left and right source drivers 3L and 3R. Meanwhile, LCD panel manufacturers often make the LCD panel 2, the interface 4, and the controller 6 into one unit. Therefore, an LCD device manufacturer purchasing such an LCD panel unit is forced to prepare pixel data in a format determined long ago by the LCD panel manufacturer reluctantly, which reduces the degree of freedom in circuit design. It is not uncommon for LCD device manufacturers to wish to provide multiple channels of pixel data in different data formats to LCD panel units. However, the prior art mentioned above cannot satisfy these needs of users. The other prior art, Published Japanese Patent Application No. 10-207434, also suffers from the same difficulties mentioned above.

Brief description of the invention

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an LCD panel unit employing an improved circuit for re-scaling incoming multiplexed pixel data into a data format for driving two different sets of source drivers.

Briefly, for these purposes, the following techniques are employed in which multiple source drivers are provided for a liquid crystal display (LCD) panel unit, functionally dividing them into a first group and a second source driver group , assigned to the first and second half of the LCD panel, respectively. In order to be able to drive the LCD panel regardless of the different format of the input pixel data, a pixel data readjustment circuit for readjusting the data format of the input pixel data to a predetermined data format is provided. This data readjustment circuit is in front of the first and second source driver groups, and its function is to receive 2N channels (N is a natural number) of pixel data, and readjust the order of the 2N channels of pixel data according to a predetermined data format, At the same time, the readjusted N channels of pixel data are provided to the first source driver group, and the readjusted N channels of pixel data are provided to the second source driver group.

In one aspect, the present invention relates to a liquid crystal display (LCD) unit comprising: a liquid crystal display (LCD) panel; functionally divided into first and second source driver groups and assigned to the LCD panel respectively. A plurality of source drivers of the half and the second half; and a pixel data readjustment circuit in front of the first and second source driver groups, the pixel data readjustment circuit receives 2N paths (N is a natural number) of pixel data, Readjust the order of the 2N channels of pixel data according to the predetermined data format, use the readjusted first group of N channels of pixel data for the first source driver group, and use the readjusted second group of N channels of pixel data for the second source driver group.

Brief description of the drawings

Features and advantages of the present invention will become apparent from the following description, while referring to the accompanying drawings, in which like elements or parts are designated by like numerals, wherein:

Figure 1 is a block diagram, which schematically illustrates the traditional layout of the LCD panel and its peripheral units, which has been mentioned in the opening description;

Fig. 2 is a block diagram schematically illustrating the LCD panel unit in the first embodiment of the present invention;

FIG. 3A is a block diagram illustrating details of the pixel data rescaling circuit shown in FIG. 2;

FIG. 3B is a block diagram illustrating a specific example of the block diagram shown in FIG. 3A;

Each of FIGS. 4A to 4D is a timing diagram for describing how the circuit shown in FIG. 3A works;

Each of FIGS. 5-7 is a timing diagram for further describing how the circuit shown in FIG. 3A works;

Fig. 8 illustrates part of the source driver of the LCD panel shown in Fig. 2;

FIG. 9 is a block diagram schematically illustrating a pixel data readjustment circuit in a second embodiment of the present invention;

Fig. 10 is a block diagram illustrating a part of the source driver used in the second embodiment of the present invention;

Each of Figures 11A-11F is a timing diagram illustrating how the second embodiment of the present invention works;

Each of Figures 12A to 12C is a timing diagram illustrating a third embodiment of the present invention; and

Each of Figs. 13A to 13C is a timing chart illustrating the fourth embodiment of the present invention.

preferred embodiment

A first embodiment of the present invention will be described below with reference to FIGS. 2-8. Referring first to FIG. 2 , a pixel data readjustment circuit (or unit) 10 directly related to the present invention is provided in a timing controller 11 . The circuit 10 is located on one edge (periphery) of a liquid crystal display (LCD) panel 14 in front of a plurality of source drivers 12 . As is well known in the art, the LCD panel 14 is provided with an array of active elements (switching elements), each typically in the form of a thin film transistor (TFT), located on a source (or data) line. Near the crossing point of the gate line (extending from the gate driver 16), as shown in FIG. 2 . When the turn-on voltage is input on the gate line, the thin film transistor is turned on, and the data voltage is applied to the pixel electrode 17 through the turned on thin film transistor.

According to the first embodiment, the plurality of source drivers 12 are divided into two groups (sections) 12L and 12R. One group 12L is assigned to the left half of the liquid crystal display panel 14 , and the other group 12R is assigned to the right half of the liquid crystal display panel 14 . The grayscale voltage generator 18 provides a plurality of grayscale voltages to be supplied to the source driver 12 . The gray level can be, for example, 8 levels, 16 levels, 32 levels, ... or 256 levels, according to the sub-pixel data provided by the pixel data readjustment circuit 10 (that is, red (R), green (G) and blue (B ) data), select one of them. Grayscale itself is well known in the art, therefore further description of it will be omitted to simplify the description.

Two pixel data inputs 1 and 2 are provided to the pixel data re-scaling circuit 10 through two pixel data channels (or paths) 20 and 22, and the sequence of the supplied pixel data is re-sequenced to correctly drive the pixels divided into two groups 12L and 12R source drivers 12.

The function of the timing controller 11 is to extract a start signal (horizontal synchronization signal) 23 from one of the pixel data 1 and 2, and supply this signal 23 to the two source driver groups 12L and 12R. Alternatively, the above-mentioned start signal can be prepared in a suitable circuit in front of the controller 11, and then provided to the timing controller 11 simultaneously with the pixel data 1 and 2. In addition, the timing controller 11 also generates a gate driver control signal. The generation of these signals (ie, the generation of the start signal and the gate driver control signal) is well known in the art, it is not directly related to the present invention, and thus a detailed description thereof is omitted for simplicity.

Referring now to Figures 3A and 3B, the pixel data rescaling controller 10 is shown in detail. As shown, the controller 10 includes a data phase adjuster 24, two memories 26 and 28, each of which includes a plurality of line memories (not shown in FIG. 3A), four switches 30a-30d and switch controller 32 . The controller 32 controls the switching operations of the respective switches 30a to 30d using the switch control data previously supplied to it from the outside. FIG. 3B shows an example of data phaser 24 , which in this particular case includes two flip-flops 34 and 36 . Obviously, the operations of the controller 10 in FIG. 3A , such as writing data into or reading data from the memories 34a-34d, and phase data control, etc., are all performed under the control of the clock signal. However, in order to simplify the drawing, the application of these clock signals is not shown in FIG. 3A.

Referring to FIGS. 3A-3B , 4A-4D and 5-7 , the working process of the pixel data readjustment circuit 10 will be introduced below. Three formats of pixel data input 1 and 2 are shown in Figs. 4A-4C, wherein assuming that the number of pixel data on a horizontal line is 2M, they are respectively numbered as 0, 1, 2, ..., 2M-1 . As we all know, except for the control bits, the number of bits of each pixel data is equal to three times the number of grayscale bits (that is, R, G, and B). In FIGS. 4A-4D , clock signal A is used to control the processing of each pixel data, and clock signal B is shifted (or delayed) by 1/2 cycle relative to clock signal A. FIG. 4D shows the data format of the outputs 1 and 2 output from the pixel data readjustment circuit 10 . In other words, pixel data inputs 1 and 2 should be rescaled as shown in Figure 4D.

If pixel data inputs 1 and 2 are provided to circuit 10 using the data format shown in FIG. 4A, there is no need to reorder the pixel data at all. In this way, the switch controller 32 sets the switches 30a and 30b according to the switch control data previously provided to it so as to directly select the pixel data inputs 1 and 2, while setting the switch 30d to output the outputs of the switches 30a and 30b as the pixel data outputs 1 and 2 . Here, the control switch 30c is not required.

Switch controller 32 sets switch 30c to provide pixel data input 1 to memory 26 and sets switches 30a and 30b to select memory 26 and 28 when pixel data inputs 1 and 2 respectively take the format shown in FIG. 4B. output. In addition, the switch 30d is controlled so as to alternately select the pixel data stored in the memories 26 and 28 so as to readjust the pixel data so that they take the data format shown in FIG. 4D. Data in this case will be described in more detail below with reference to FIGS. 5 to 7 .

Referring to FIG. 4C, pixel data inputs 1 and 2 are arranged exactly as shown in FIG. 4B. However, input 2 is delayed by 1/2 clock cycle relative to input 1. At this time, the switch controller 32 controls the switch 30c to select the data phase adjuster 24 to delay the data input 1 by 1/2 clock cycle, so that the two phases of the pixel data inputs 1 and 2 are the same. The data phase adjuster 24 can adopt a relatively simple conventional circuit as shown in FIG. 3B. When the falling edge of the clock signal A arrives, the pixel data is sent to the flip-flop 34, after that, the pixel data stored in the flip-flop 34 is sent to the next flip-flop 36 at the rising edge of the clock signal A, providing When it is given to the flip-flop 36, the clock signal A is reversed, and the data input 1 is delayed by 1/2 cycle. The remaining operations shown in FIG. 4C are the same as described with reference to data format 2 of FIG. 4B.

Referring to FIGS. 5-7, there are shown timing diagrams for discussing memory read/write operations, and the data arrangement of data inputs 1 and 2 as shown in FIG. 4B. As described above, each of the memories 26 and 28 has a plurality of line memories, and when the number of pixel data inputs is 2 as described above, its number is 4 (that is, 8 in total). Assume that there are line memories 1-4 and 5-8 in the memories 26 and 28, respectively.

FIG. 5 shows the memory write operation of the first row of data in data inputs 1 and 2. FIG. As shown in the figure, the first half pixel data 0, 2, ..., M-2 on the first line of input 1 are continuously written into line memory 1, and similarly, the pixel data of the first line of input 2 The first half is written consecutively to line memory 2 . Subsequently, the second half of the pixel data M, M+2, ..., 2M-2 in the first line of input 1 is continuously written into the line memory 3, and in a similar manner, the pixel data M in the first line of input 2 The second halves of +1, M+3, . . . , 2M-1 are stored in line memory 4 consecutively. During these operations, no data writing/reading operations are performed on the remaining line memories 5-8. Furthermore, the pixel data readjustment circuit 10 does not have any data output (FIGS. 2 and 3A).

FIG. 6 shows a memory write operation of data inputs 1 and 2 for the second row of data, and a memory read operation for data inputs 1 and 2 of the first row of data. Except that the used line memory is different, the writing operation of the second line data into the line memory 5-8 is carried out in exactly the same way. As such, further descriptions would necessarily be repetitive, so they are omitted for simplicity. Simultaneously with the writing operation of the second row, the pixel data of the first row already stored in the row memories 1-4 are read out from the row memories 1-4, as shown in FIG. 6 . Therefore, the pixel data realignment circuit 10 is able to realign the first row of data of the inputs 1 and 2, and generate the data outputs 1 and 2 according to the predetermined format shown in FIG. 4D.

FIG. 7 shows the memory write operation of data input 1 and 2 for the third row of data, and simultaneously shows the memory read operation of the second row of data. These operations can be easily understood from the aforementioned description.

FIG. 8 schematically illustrates a part of each source driver 12L and 12R. The start signal (that is, the horizontal synchronization signal) is applied to the first stage of each shift register L1 and R1, and then the start signal is shifted to the right or translated, and then according to the shift pulse (not shown in the figure) respectively Applied to the next shift register L2 and R2. The thus shifted start signal is supplied to the corresponding stages of latches LL1, LL2, . . . and RL1, RL2, . Each of these latches has multiple stages whose number is equal to the number of the corresponding shift register. The latches LL1, LL2, RL1, RL2, etc. successively latch pixel data of outputs 1 and 2 generated from the pixel data readjustment circuit 10 according to a start signal and a clock signal (ie, clock signal A). All the pixel data on one line are stored in the latches LL1, LL2, ..., RL1, RL2, ... After that, the gray level voltage is determined with the latched pixel data, and then the gray level voltage is applied to The corresponding active element is, for example, a well-known thin film transistor in the prior art.

Next, a second embodiment of the present invention will be described with reference to FIGS. 9, 10 and 11A to 11F. The pixel data reordering circuit 110 (FIG. 9) in the second embodiment receives four pixel data inputs 1-4 and generates four pixel data outputs 1 after reordering the input data into a predetermined order. ~4. Thus, the difference between the second embodiment and the first embodiment lies in the number of input and output data.

As shown in FIG. 9 , four pixel data inputs 1 - 4 , which can take the different formats illustrated in FIGS. 11A - 11E , are provided to the data rescaling circuit 110 . Generally, the circuit 110 includes a data phase adjuster 124 with switches therein, a memory cell 126 with switches therein, a switch 130d, and a switch controller 132 to which switch control data is provided from an external circuit. Since the second embodiment is an extension of the first embodiment, the second embodiment will be described with reference to the first embodiment.

Pixel data outputs 1-4 to be generated from circuit 110 are shown in FIG. 11F and are applied to source driver groups 112L and 112R shown in FIG. 10 . Pixel data outputs 1~2 and 3~4 are assigned to the left half and right half of the LCD panel, respectively.

FIG. 10 shows a portion of each of the source drivers 112L and 112R, and this figure corresponds to FIG. 10 . As shown in Figure 8, a start signal (that is, a horizontal synchronization signal) is provided to the first stage of each shift register L1' and R1', after which this start signal is translated (shifted) to the right, and then According to the clock signal (clock signal A), it is respectively supplied to the next shift registers L2' and R2'. As described above, since the pixel data outputs 1 to 2 and 3 to 4 are assigned to the source drivers 112L and 112R, respectively, it is possible to latch two consecutive pixel data at a time. Therefore, the number of stages of each shift register L1', R1', etc. can be halved. The synchronization signal thus shifted is supplied to consecutive two stages of latches LL1', LL2', ..., RL1', RL2', .... Therefore, a pair of pixel data of each data output 1-2 and 3-4 from the circuit 110 will be latched at the same time. Subsequent operations are the same as those already described with reference to FIG. 8 .

If pixel data inputs 1-4 are provided to circuit 110 in the format shown in FIG. 11A, there is no need to reorder the pixel data for inputs 1-4 as in FIG. 11F. In this case, the switch controller 132 controls only the switch 130d so that the data inputs 1-4 pass through it. The switch 130d corresponds to the switch 13d shown in FIG. 3A. Obviously, the switch controller 132 does not control the switch unit 124s in the data phase adjuster 124 . The switch unit 124s allows the data input provided to it to pass through, as will be described below. Furthermore, in the above situation, the switch controller 132 does not control the switch unit 126s in the memory unit 126 . The switch unit 126s functions as the switch 30c of FIG. 3A.

When pixel data inputs 1-4 take the format shown in FIG. 11B, switch controller 132 sets switch 124s to provide data inputs 1-4 through data phaser 124, since there is no need for data inputs 1 and 2 to perform data phase adjustment. phase delay. Although not shown in FIG. 9, in fact the memory unit 126 has 16 line memories, which is doubled in number compared to the first embodiment because the data input is doubled. How to adjust the order of data input 1-4 can be understood by referring to FIGS. 5-7. That is, the difference between the first embodiment and the second embodiment is that the numbers of input data and output data are doubled.

In the case of pixel data inputs 1-4 in the format shown in FIG. 11C, switch controller 132 sets switch 124s to provide data inputs 1-4 to data phase adjuster 124 because inputs 1-2 must be delayed by 1/2 clock cycle. It should be noted that inputs 3-4 do not undergo any data phasing. The thus delayed data inputs 1-2 and the undelayed inputs 3-4 are provided to the memory unit 126 together. Subsequent operations are the same as those performed on data inputs 1 to 4 shown in FIG. 11B.

With respect to pixel data inputs 1 to 4 in the format of FIG. 11D , operations for reordering the data are substantially the same as those performed for data inputs 1 to 4 shown in FIG. 11B . The difference between these two cases (FIGS. 11D and B) is that the line memory to be selected by the switch 130d under the control of the clock signal is different.

When the pixel data input 1-4 adopts the format shown in Figure 11E, the switch controller 132 sets the switch 124s to provide the data input 1-4 to the data phase adjuster 124, because the input 1-2 must be delayed by 1/2 Clock cycle, as in the case of Fig. 11C. The thus delayed data inputs 1-2 are supplied to the memory unit 126 together with the undelayed inputs 3-4. Subsequent operations are the same as those performed for data inputs 1 to 4 shown in Fig. 11D.

A third embodiment of the present invention will be described below with reference to Figs. 12A to 12C. When testing and/or troubleshooting an LCD panel in the laboratory or in the quality control department, it is sometimes necessary to check the left and right halves of the LCD panel with the same data. Also, displaying the same data on the left and right halves of the board under test is sometimes sufficient to check the operation of the display board. For this purpose, according to the third embodiment, the pixel data rescaling circuit 10 or 110 is used to display the same pixel data on the left half and the right half of the LCD panel.

In FIG. 12A, only pixel data 1 is supplied to the circuit 10, while FIG. 12C illustrates the output of the circuit 10. In this case, the line memories 1 and 2 mentioned in the first embodiment store the same pixel data 0, 1, 2, ..., M-1 of the first half of the first line of the input 1, where Thereafter, the circuit 10 controls the switches 30a, 30b, and 30d, thereby generating pixel data shown in FIG. 12C. In this way, the same data is supplied to the source driver groups 12L and 12R. The same discussion applies to the case where only the data input 2 shown in Figure 12B is provided to the circuit 10. It goes without saying that the data rescaling circuit 110 can be used to receive individual pixel data, producing the data shown in Fig. 12C.

A fourth embodiment of the present invention will be described below with reference to Figs. 13A to 13C. When testing and/or troubleshooting an LCD panel in a lab or quality control department, it is sometimes necessary to examine an entire row while displaying half of the pixel data normally assigned to the panel. This is achieved by displaying each pixel data in two adjacent pixel units. This technique is preferred when examining gray level variations across the entire horizontal line of high pixel density panels, as gray level variations can be minimized.

FIG. 13A shows that only pixel data 1 is supplied to the circuit 10 , while FIG. 13C shows the output of the circuit 10 . In this case, line memories 1 and 2 store the same pixel data 0, 1, 2, . The pixel data shown in 13C is generated so that the same pixel data is supplied to the two adjacent source drivers 12 of each of the source driver groups 12L and 12R. This discussion applies equally to the case where only data input 2 is provided to circuit 10 as shown in FIG. 13B. Clearly, the data rescaling circuit 110 can be used to receive individual pixel data to produce the data shown in Figure 13C.

As mentioned above, some preferred embodiments have been described under the assumption that the number of data inputs and outputs per pixel is 2 and 4. However, the present invention can also be used in the case where the number of each data input and output is 2N (N is a natural number greater than 2). Also, the data phase adjustment need not be performed in the data readjustment circuit 10 (or 110), in which case the phase adjuster 24 (or 124) follows the switch 30d (130d).

Four preferred embodiments and some of their modifications are given above. However, for those skilled in the art, there are other various improvements that will not depart from the protection scope of the present invention, and the scope of the present invention is only limited by the claims. Therefore, the embodiments and modifications presented here are only illustrative, not restrictive.

Claims (8)

1. A liquid crystal display (LCD) unit having a pixel data readjustment circuit, the pixel data readjustment circuit comprising: A plurality of pixel data inputs, the number of which is 2N (N is a natural number), and 2N channels of pixel data can be provided thereto; a data phase adjuster, used to eliminate the phase difference if there is a phase difference between the 2N channels of pixel data received at the pixel data input; storage means for storing 2N channels of pixel data received at a plurality of pixel data inputs, wherein if there is a phase difference, the memory is operatively connected to receive the output of the data phase adjuster; first switching means for selectively reading pixel data stored in the storage means; and The second switching device, which follows the first switching device, is used to readjust the order of the pixel data according to the predetermined data format, and provide the readjusted first group of N pixel data to the first half of the LCD panel. a source driver group, and provide the readjusted second group of N channels of pixel data to the second source driver group assigned to the other half of the LCD panel. 2. A liquid crystal display (LCD) unit having a pixel data readjustment circuit, the pixel data readjustment circuit comprising: A plurality of pixel data inputs, the number of which is 2N (N is a natural number), and 2N channels of pixel data can be provided thereto; a storage device for storing 2N paths of pixel data received at a plurality of pixel data inputs, first switching means for selectively reading pixel data stored in the storage means; and The second switching device, which follows the first switching device, is used to readjust the order of the pixel data according to the predetermined data format, and provide the readjusted first group of N pixel data to the first half of the LCD panel. a source driver group, and provide the readjusted second group of N pixel data to the second source driver group assigned to the other half of the LCD panel, Wherein, if there is a phase difference between the first and second sets of N channels of pixel data output by the second switching device, the phase difference is eliminated before being provided to the LCD panel. 3. A liquid crystal display (LCD) unit having a pixel data readjustment circuit, the pixel data readjustment circuit comprising: A plurality of pixel data inputs, the number of which is 2N (N is a natural number), and a single channel of pixel data can be provided thereto; storage means for storing a single channel of pixel data received at one of the plurality of pixel data inputs; The switching device is used to selectively read the pixel data stored in the storage device and generate two channels of pixel data, each channel of pixel data is the same as a single channel of pixel data, and one of the two channels of pixel data is provided to the A first source driver group assigned to one half of the LCD panel, and the other of the two channels of pixel data is provided to a second source driver group assigned to the other half of the LCD panel. 4. A liquid crystal display (LCD) unit having a pixel data readjustment circuit, the pixel data readjustment circuit comprising: A plurality of pixel data inputs, the number of which is 2N (N is a natural number), and a single channel of pixel data can be provided thereto; storage means for storing a single channel of pixel data received at one of the plurality of pixel data inputs; switching means for selectively reading pixel data stored in the storage means, and generating two-way pixel data by duplicating each of the single-way pixel data, one of the two-way pixel data being supplied to A first source driver group assigned to one half of the LCD panel, and the other of the two channels of pixel data is provided to a second source driver group assigned to the other half of the LCD panel. 5. A method for readjusting 2N road (N is a natural number) pixel data provided to a liquid crystal display (LCD) unit, comprising the following steps: (a) receiving 2N channels of pixel data at a plurality of pixel data inputs whose number is 2N (N is a natural number); (b) If there is a phase difference between the 2N paths of pixel data received in step (a), then eliminate the phase difference; (c) storing 2N paths of pixel data received at a plurality of pixel data inputs, wherein, if there is a phase difference between the 2N paths of pixel data, the phase difference has been eliminated in step (b); (d) selectively reading the pixel data stored in step (c); and (e) Readjust the order of the pixel data according to the predetermined data format, provide the readjusted first group of N pixel data to the first source driver group allocated to half of the LCD panel, and provide the readjusted first group of N pixel data to the half of the LCD panel. Two sets of N-way pixel data are provided to a second source driver set assigned to the other half of the LCD panel. 6. A method for readjusting 2N road (N is a natural number) pixel data provided to a liquid crystal display (LCD) unit, comprising the following steps: (a) receiving 2N channels of pixel data at a plurality of pixel data inputs whose number is 2N (N is a natural number); (b) storing 2N paths of pixel data received at a plurality of pixel data inputs; (c) selectively reading the pixel data stored in step (b); and (d) Readjust the order of the pixel data according to the predetermined data format, provide the readjusted first group of N pixel data to the first source driver group allocated to half of the LCD panel, and provide the readjusted No. Two groups of N-way pixel data are provided to the second source driver group assigned to the other half of the LCD panel, Wherein, if there is a phase difference between the first and second sets of N channels of pixel data generated in step (d), the phase difference is eliminated before being provided to the LCD panel. 7. A method for readjusting the single-channel pixel data provided to a liquid crystal display (LCD) unit, comprising the following steps: (a) receiving single channel pixel data; (b) storing the single channel pixel data received in step (a); (c) selectively reading the single path of pixel data stored in step (b), so that two paths of pixel data are generated, each path of pixel data is the same as the single path of pixel data, and one path of the two paths of pixel data is provided to A first source driver group assigned to one half of the LCD panel, and the other of the two channels of pixel data is provided to a second source driver group assigned to the other half of the LCD panel. 8. A method for readjusting the single-channel pixel data provided to a liquid crystal display (LCD) unit, comprising the following steps: (a) receiving single channel pixel data; (b) storing the single channel pixel data received in step (a); (c) selectively reading the one-way pixel data stored in step (b) so that two-way pixel data is generated by duplicating each of the one-way pixel data, one of which is supplied to a first source driver group assigned to one half of the LCD panel, and the other of the two channels of pixel data is provided to a second source driver group assigned to the other half of the LCD panel.

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