JP3661324B2 - Image display device, image display method, display drive device, and electronic apparatus using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image display device such as an active matrix liquid crystal display device, an image display method, a display drive device, and an electronic apparatus using the same.
[0002]
[Background Art and Problems to be Solved by the Invention]
For example, in an active matrix liquid crystal display device, an operation of writing data to the liquid crystal layer of each pixel is performed by dot sequential driving via a plurality of switching elements such as TFTs (thin film transistors) connected to one scanning signal line. ing.
[0003]
By the way, in order to respond to the recent demands for multimedia, for example, when displaying a natural image such as a video signal on a personal computer (PC) or an engineering work station (EWS), for example, there are a large number of 256 gradations. A response to gradation is desired.
[0004]
In order to realize this multi-gradation correspondence with a conventional digital driver, the number of input signals is increased by a number of bits. For example, in the case of 256 gradation color display, the number of input signals is 3 (R, G, B) × 8 bits = 24.
[0005]
On the other hand, with an analog driver, only three input signals are required for color display, and one input signal is required for monochrome display. Further, the gradation characteristics of digital drivers are discrete, whereas the gradation characteristics of analog drivers are continuous, which is advantageous for display based on normal video signals.
[0006]
By the way, in the active matrix liquid crystal display device, it is necessary to sample and hold data in an image signal by a TFT switch or the like for the above-described dot sequential driving. At this time, there arises a problem that switching characteristics such as TFT cannot sufficiently follow the frequency of the input image signal. In the case of a display device with a built-in driver, the capability of the sample-and-hold TFT is lower than in the case of a display device using an external driver, and the problem becomes more prominent. Further, in the case of a high-definition display device having a large number of pixels, the above problem becomes more noticeable because the frequency of the input image signal becomes high.
[0007]
Therefore, as shown in FIG. 38, a technique has been proposed in which the input image signal is phase-expanded into, for example, six parallel signals, the data length per pixel is increased, and the signal frequency input to the liquid crystal panel is decreased. (Japanese Patent Application No. 6-316988).
[0008]
By this phase development, for example, even if the frequency characteristics of the TFT as the sample hold switch are not sufficient, the data length per pixel can be increased and the resolution can be increased.
[0009]
As shown in FIG. 38, the data length of each of the phase expansion signals that are expanded in six phases and output in parallel is the length of six cycles of the reference clock.
[0010]
When this is sampled by a sample hold switch such as a TFT, for example, a sampling period set by a sampling period signal input to the gate of the TFT is initially set to 8 reference clock cycles as shown in FIG. Tried to set to length.
[0011]
This is because a sufficient sampling period is set for the data length in the phase expansion signal in consideration of the followability of switching of the TFT. Further, the sampling period signal having this sampling period can be easily generated by using only the shift register.
[0012]
However, according to the experiment of the present inventor, as schematically shown in FIG. 39, for example, when the arrow 1 is to be displayed on the screen 2, a ghost 3 indicated by a broken line is generated at the subsequent stage of the arrow 1 in the scanning direction. Turned out to be.
[0013]
In addition, in order to eliminate display unevenness due to the bias of voltage applied to the liquid crystal and to prevent deterioration of the liquid crystal due to direct current applied to the liquid crystal, polarity inversion driving is performed to invert the polarity of the voltage applied to the liquid crystal at a predetermined timing. Yes. The polarity inversion drive is a drive in which a voltage having a different polarity (positive or negative polarity) is applied to one end of the liquid crystal with reference to a potential applied to the other end of the liquid crystal. In addition, the polarity in this specification means the polarity of the voltage applied to the both ends of a liquid crystal. For polarity inversion driving, in the active matrix type, the potential applied to the common electrode facing the pixel electrode across the liquid crystal is changed, or the intermediate potential of the voltage amplitude of the image signal applied to the pixel electrode is used as a reference. As described above, the potential level of the image signal is changed.
[0014]
Here, a so-called line inversion in which polarity inversion is performed every time a scanning signal line is selected, or a polarity inversion driving method in which dot inversion is combined with this is known. In this case, even when, for example, the same black is written sequentially on two pixels connected to the same data signal line and connected to different scanning signal lines, each black image data signal is used for polarity inversion driving. The level is different. At this time, since the data signal line itself has a parasitic capacitance, it takes time to change the potential of the data signal line from the positive black potential to the negative black potential.
[0015]
According to the prior art, since a sufficient sampling period is set for the data length in the phase expansion signal, it is possible to secure a sufficient time for charging and discharging the data signal line. However, since the above-mentioned ghost problem cannot be solved, there is room for improvement in the setting of the sampling period. At the same time, it is necessary to charge and discharge the data signal line until the data potential becomes the data potential during the sampling period. .
[0016]
Therefore, an object of the present invention is to reduce or prevent ghosts while phase-expanding an input image signal, and to secure a sufficient time for charging / discharging the data signal line, Another object of the present invention is to provide an image display device, an image display method, a display drive device, and an electronic apparatus using the same, which can improve the image quality by supplying a voltage faithful to the pixel data to the pixel.
[0017]
Another object of the present invention is to enable display driving while reducing or preventing ghosts even when dot-sequential driving cannot follow sample-and-hold operation as the dot clock speeds up, and is a voltage that is faithful to the pixel data of the image signal. It is to provide an image display device, an image display method, a display drive device, and an electronic apparatus using the same, which can improve the image quality by supplying a pixel to the pixel.
[0018]
[Means for Solving the Problems]
The image display device according to the present invention includes an image display unit in which pixels are arranged at pixel positions formed by intersections of a plurality of data signal lines and a plurality of scanning signal lines. The scanning signal line selection unit sequentially supplies scanning signals to the scanning signal lines. Here, the polarity of the voltage applied to the pixel is inverted and driven every predetermined period. The phase expansion means samples an image signal having data corresponding to each pixel position in time series, and outputs in parallel a plurality of phase expansion signals converted to a data length longer than the sampling period. A plurality of sampling means respectively connected to each of the data signal lines receives one of the plurality of phase expansion signals as an input, samples the data in the phase expansion signals, and outputs data to the data signal lines. Supply as a signal. The data signal line driving unit generates a sampling period signal having a sampling period shorter than the period corresponding to the data length of the phase expansion signal, and supplies the sampling period signal to the sampling switching unit.
[0019]
The plurality of precharge switching means are configured to detect the pixel based on pixel data sampled in the sampling period in a precharge period before the sampling period for supplying the data signal to each of the data signal lines. Each data signal line is precharged with the same polarity as the polarity of the voltage applied to.
[0020]
The present invention functions as follows in order to reduce or prevent ghost, which is one of the problems of the present invention.
[0021]
First, the present inventor analyzed that the cause of the ghost is that unnecessary components are mixed in the waveform supplied to the pixels via the sampling means as shown in FIG. As shown in FIG. 38, the mixing of unnecessary components into the waveform is that the data length of the phase expansion signal is 6 periods of the dot clock, whereas the sampling period is as long as 8 periods of the dot clock. It is due to that.
[0022]
Therefore, for example, in the case of the video n signal line in FIG. 38, the sampling period signals S / H (n), S / H (n + 6), and S / H (n + 12) each have an overlap period. Therefore, for example, at the initial stage of the sampling period of S / H (n + 6), even the data sampled by the sampling period signal S / H (n) is sampled by the sampling period signal of S / H (n + 6).
[0023]
The phenomenon in this case was observed and observed with a potential waveform supplied to the liquid crystal layer. As a result, depending on the writing capability of the sampling means, as shown in FIG. 40, an unnecessary component is mixed in the waveform under the influence of the data written by the arrow 1 once, and the level should be lowered originally. It has been found that the level becomes higher at the position corresponding to the ghost 3 in the figure.
[0024]
In the present invention, as symbolically shown in FIG. 9, FIG. 14, FIG. 18 and FIG. 22, the sampling period can always be set shorter than the data length of the phase expansion signal. And ghost can be reduced or prevented.
[0025]
As another object of the present invention, in order to charge / discharge the data signal line to the data potential within the sampling period, the present invention functions as follows.
[0026]
That is, in the precharge period before the sampling period for supplying the data signal to each data signal line, the same polarity as the voltage applied to the pixel based on the pixel data sampled in the sampling period The data signal lines are precharged. Therefore, since the potential of the data signal line has already reached the precharge potential in the precharge period, the data signal line may be charged / discharged until the data potential is changed from the precharge potential in the sampling period. In particular, as described above, in the present invention, the sampling period for sampling the potential of the phase expansion signal is shorter than that of the prior art. However, by performing precharging, the above-described charging / discharging is achieved even in this short sampling period. it can. Therefore, the image data can be accurately sampled during the sampling period, and the data signal line can be reliably charged / discharged with the sampled data potential, thereby improving the image quality.
[0027]
In the present invention, it is preferable that a plurality of sampling switching means and a plurality of precharge switching means are connected in parallel to one end of each of the data signal lines.
[0028]
Compared with the case where each switching means is connected to both ends of the data signal line, the circuit layout becomes easier.
[0029]
In this case, the data signal line driving unit generates a precharge period signal for turning on the plurality of precharge switching units over the precharge period based on the sampling period signal, and supplies the precharge period signal to the plurality of precharge switching units. It is preferable to do.
[0030]
In this way, the circuit for setting the sampling period and the precharge period is shared, the length of the line for the period signal can be shortened, and the delay of the period signal due to the parasitic capacitance of the line can be shortened. Thereby, the sampling period and the precharge period can be set almost as designed, and both periods can be prevented from overlapping due to signal delay.
[0031]
The phase expansion means of the present invention sequentially shifts the head position of the pixel data of the N phase expansion signals based on the reference clock, and outputs the N phase expansion signals to the N phase expansion signal lines in parallel. Can do. In this case, the data signal line driving means generates a sampling period signal that is set by sequentially shifting the start timing of the sampling period. As a result, the pixels connected to one scanning signal can be driven dot-sequentially. Further, the data signal driving means also uses a sampling period signal for setting a sampling period for one data signal line as a sampling period signal for setting a precharge period for another data signal line. This reduces the circuit scale of the data signal line drive circuit and facilitates circuit layout.
[0032]
In the present invention, the data signal line driving means has a plurality of stages for sequentially shifting the input signal, and the output signal of each stage is output at a timing at which the output signal of the next stage partially overlaps with the output signal. A plurality of AND circuits connected to each sampling switching means, wherein the two output signals whose signal phases overlap each other from the shift register are input, and the logical product is output to the sampling switching means as a sampling period signal And can have.
[0033]
More specifically, the shift register sequentially shifts and sends out an input signal having a pulse width that is 2K (K is a natural number) times one period of the reference clock. In the example of FIG. 8A, K = 4 and the pulse width of the input signal DX is eight times the period of the dot clock DC. In the example of FIG. 13, K = 3 and the pulse width of the input signal DX is six times the period of the dot clock DC. In the example of FIG. 17, K = 2, and the pulse width of the input signal DX is four times the period of the dot clock DC.
[0034]
Further, the AND circuit connected to each sampling switching unit receives two outputs having different shift amounts from the shift register, and outputs the logical product to the sampling switching unit as a sampling period signal.
[0035]
As a result, the AND circuit connected to the k (1 ≦ k ≦ total number of pixels on one scanning signal line) -th sampling switching means has the k-th and (k + K) -th in one horizontal scanning period. The sampling period based on the sampling period signal that is the output of the shift register and is the logical product of them is K times the period of the reference clock.
[0036]
In FIG. 7 showing an embodiment in which K = 4, for example, if k = 1, the first and fifth shift register outputs are input to the AND circuit 160a, and the sampling period is one of the dot clocks DC as shown in FIG. It is 4 (= K) times the period.
[0037]
In FIG. 12, which is an embodiment of K = 3, for example, if k = 1, the first and fourth shift register outputs are input to the AND circuit 160a, and the sampling period is one of the dot clocks DC as shown in FIG. It is 3 (= K) times the period.
[0038]
In FIG. 16, which is an embodiment of K = 2, for example, if k = 1, the first and third shift register outputs are input to the AND circuit 160a, and the sampling period is one of the dot clocks DC as shown in FIG. It is 2 (= K) times the period.
[0039]
In this case, the data signal line driving means supplies the sampling period signal generated based on the outputs of the plurality of AND circuits to the sampling switching means, and the sampling period signal is supplied to the sampling circuit to which the signal is supplied. This is supplied to a precharge switch not connected in parallel with the switch for use. As a result, the sampling period signal can also be used as the precharge period signal.
[0040]
In the present invention, the phase expansion means can output the N phase expansion signals in parallel to the N phase expansion signal lines by matching the heads of the pixel data of the N phase expansion signals. Thereby, as symbolically shown in FIG. 22, a plurality of pixels connected to one scanning signal line can be simultaneously driven by the total number N of phase development signal lines. In this case, the data signal line driving means supplies a common sampling period signal in which the sampling period start times coincide with each other to the N sampling switching means. Further, the data signal line driving means supplies the common sampling period signal as a common precharge period signal to the other N precharging switching means that are not in parallel with the N sampling switching means. . Thereby, the sampling period signal can also be used as the precharge period signal.
[0041]
Further, the data signal line driving means has a shift register that sequentially shifts and sends out the input signal for each period of the reference clock, and m (1 ≦ m ≦ total number of pixels on one scanning signal line / the phase expansion) (Total number of signal lines) The (3m-2) th shift register output in one horizontal scanning period is supplied as a sampling period signal to N sampling switching units connected to the data signal line that is driven at the same time. be able to. More specifically, this shift register sequentially shifts and sends out an input signal having a pulse width 2K (K is a natural number) times one period of the reference clock.
[0042]
In the example of FIG. 21, K = 4 and the pulse width of the input signal DX is eight times the period of the dot clock DC.
[0043]
In this way, at the time of m (1 ≦ m ≦ total number of pixels on one scanning signal line / total number of phase development signal lines) th simultaneous driving, the (3m−2) th shift register output in one horizontal scanning period is The sampling period input to the plurality of sampling switching means and set in the sampling switching means is K times one cycle of the reference clock.
[0044]
In the example of FIG. 20, for example, in m = 1st simultaneous driving, 3m−2 = 1st shift register output is input to N = 6 sampling switching means 106. Similarly, in m = 2 second simultaneous drive, 3m−2 = 4th shift register output is input to the next six sampling means 106, and in m = third simultaneous drive, 3m−2 = 7 The output of the first shift register is input to the next six sampling switching means 106. Further, the (3m-2) th shift register output can be supplied to other N precharge switching means connected to the (m + 1) th simultaneously driven data signal line. Thereby, the sampling period signal can also be used as the precharge period signal.
[0045]
In the present invention, the precharge period for all data signal lines may be set within the horizontal blanking period. Thus, the generation of the timing signal for setting the precharge period can be easily generated based on the horizontal synchronization signal.
[0046]
The image display unit of the present invention can be composed of a liquid crystal panel in which liquid crystal is interposed between a pair of substrates. In this case, the plurality of sampling switching means can be composed of a plurality of thin film transistors formed on one substrate. A sampling period signal from the data signal line driving means is supplied to the gate of each thin film transistor.
[0047]
Although the TFT has a limited writing capability, a sufficient sampling period can be secured by inputting a phase expansion signal having pixel data with a long data length, and the previous pixel data is not written during the sampling period. Therefore, unnecessary components are reduced from being mixed in the waveform, and ghosting can be effectively prevented.
[0048]
In the present invention, the first polarity image signal for driving the pixel with the first polarity with respect to the polarity reversal reference potential from the input image signal and the polarity opposite to the first polarity are provided before the phase expansion means. And a second polarity image signal for driving the pixel with the second polarity and outputting either one of the first and second polarity signals to the phase developing means. At this time, the phase development means outputs the first and second polarity phase development signals based on the first and second polarity image signals.
[0049]
Further, the polarity inversion means includes a first polarity inversion means for outputting one of the first and second polarity image signals, and a second polarity inversion means for outputting the other of the first and second polarity image signals. Can have.
[0050]
In the present invention, a plurality of polarity inversion means can be provided in the subsequent stage of the phase expansion means. In this case, the plurality of polarity inversion means includes a first polarity phase development signal for driving the pixel with a first polarity with respect to the polarity inversion reference potential from one of the plurality of phase development signals, and the first polarity. A second polarity phase development signal for driving the pixel with the second polarity of the opposite polarity is generated, and one of the first and second polarity phase development signals is output to the plurality of sampling units.
[0051]
Each of these polarity inversion means includes a first polarity inversion means for outputting one of the first and second polarity phase development signals, and a second polarity inversion means for outputting the other of the first and second polarity phase development signals. And can have.
[0052]
In the present invention, switching means for switching a plurality of phase development signals (or first and second polarity phase development signals) to supply to a plurality of sampling means, changing the development order in the phase development means, and controlling the development order. And a change control means for changing and controlling the supply destination of a plurality of phase development signals (or first and second polarity phase development signals) by the switching means. In this way, it is possible to prevent, for example, variations in DC offset components that occur for each phase development signal from being emphasized by the vertical lines of the screen.
[0053]
In the present invention, the scanning signal line is selected between the first precharge potential for precharging the data signal line with the first polarity and the second precharge potential for precharging the data signal line with the second polarity. It is possible to further provide precharge potential supply means for switching to each of the plurality of precharge switching means for switching.
[0054]
Thus, every time a scanning signal line is selected, the precharge potential can be switched between the first and second polarities.
[0055]
In the present invention, the first precharge line connected to the odd number of the plurality of precharge switching means, the second precharge line connected to the even number of the plurality of precharge switching means, Precharge potential supply means for switching to each time a scanning signal line is selected between the first precharge potential and the second precharge potential and supplying the scan signal line to the first and second precharge lines is further provided. it can. In this way, so-called polarity inversion driving for each dot becomes possible.
[0056]
In the present invention, the display driving device that drives the image display unit may be an external circuit for the image display unit.
[0057]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments in which the present invention is applied to an active matrix type liquid crystal display device will be specifically described below with reference to the drawings.
[0058]
(1) First embodiment
(Schematic configuration of the device)
FIG. 1 shows an overall outline of the liquid crystal display device according to the first embodiment. As shown in the figure, this liquid crystal display device is a small liquid crystal display device used as a light valve of an electronic device such as a liquid crystal projector, and is roughly divided into a liquid crystal panel block 10, a timing circuit block 20, and a data processing block 30. Is done.
[0059]
The timing circuit block 20 receives the clock signal CLK and the synchronization signal SYNC and outputs a predetermined timing signal.
[0060]
The data processing circuit block 30 includes a phase expansion circuit 32 and an amplification / inversion circuit 34. The phase development circuit 32 receives a single image signal (in this embodiment, black and white grayscale display and one image signal) Data, and develops pixel information into N phases (N = 6 phases in FIG. 1). The N-phase phase expansion signal is output in parallel. When the liquid crystal panel 100 in the liquid crystal panel block 10 is a color liquid crystal panel having color filters of three primary colors, three image signals R, G, and B are input to the phase expansion circuit 32, For example, six phase development signals can be generated from the three image signals. This N phase expansion will be described later.
[0061]
The amplification / inversion circuit 34 amplifies the N phase expansion signals to a voltage necessary for driving the liquid crystal panel, and inverts the polarity with reference to the polarity inversion reference potential as necessary. Note that the positions of the amplification / inversion circuit 34 and the phase expansion circuit 32 shown in FIG. 1 may be reversed. That is, the image signal may be amplified and inverted by the amplification / inversion circuit 34 and then phase-expanded by the phase expansion circuit 32.
[0062]
Since the output line of the data processing circuit block 30 of the present embodiment performs six-phase expansion, it is branched into six lines of Data1 to Data6 as shown in FIG.
[0063]
The liquid crystal panel block 10 includes a liquid crystal panel 100, a scanning side driving circuit 102, a data side driving circuit 104, and a precharge driving circuit 170 on the same circuit board. These drive circuits may be configured as external ICs separately from the liquid crystal panel substrate.
[0064]
On the liquid crystal panel 100, for example, a plurality of scanning signal lines 110 extending along the row direction in FIG. 1 and a plurality of data signal lines 112 extending along the column direction, for example, are formed. In this embodiment, the total number of scanning signal lines 110 is 492, and the total number of data signal lines 112 is 652. At the pixel position formed by the intersection of the lines 110 and 112, the switching element 114 and the liquid crystal layer 116 are connected in series to form a display element, which forms a pixel. A period during which the switching element 114 is turned on is referred to as a selection period, and a period during which the switching element 114 is turned off is referred to as a non-selection period. A storage capacitor (not shown) that holds the voltage supplied to the liquid crystal layer 116 via the switching element 114 in the selection period in the non-selection period is connected to the liquid crystal layer 116. In this embodiment, the switching element 114 is, for example, a three-terminal switching element, and is configured by, for example, a TFT. Not limited to this, a two-terminal switching element such as an MIM (metal-insulating layer-metal) element, an MIS (metal-insulating layer-semiconductor layer) element, or the like can be used. The liquid crystal panel 100 of the present embodiment is not limited to an active matrix liquid crystal display panel using two-terminal or three-terminal switching, but may be other various liquid crystal panels such as a simple matrix liquid crystal display panel. There may be. The liquid crystal panel 100 of the present embodiment has a first substrate on which scanning signal lines 110, data signal lines 112, and TFTs connected thereto are formed. The first substrate further includes a pixel electrode connected to the TFT and a storage capacitor having the pixel electrode as one electrode. The liquid crystal panel 100 further includes a second substrate that is disposed to face the first substrate and on which a common electrode is formed. Then, liquid crystal is sealed between the first and second substrates to form the liquid crystal panel 100. The liquid crystal layer at each pixel position is applied with an electric field by both electrodes with one end being a pixel electrode and the other end being a common electrode.
[0065]
The scanning side drive circuit 102 outputs a scanning signal in which a selection period for sequentially selecting the scanning signal lines 110 from the plurality of scanning signal lines 110a, 110b.
[0066]
The data side driving circuit 104 is a sample and hold switch disposed between the six phase development signal lines Data1 to Data6 that are output lines of the data processing circuit block 30 and the data signal lines 112a, 112b. A sampling period signal for driving the liquid crystal panel 100 in a dot sequential manner is output to 106.
[0067]
The first phase development signal line Data1 is connected to the first data signal line 112a via the sample hold switch 106a. Similarly, the second to sixth phase development signal lines Data2 to Data6 are connected to the second to sixth data signal lines 112b to 112f via the sample hold switches 106b to 106f, respectively. The first phase development signal line Data1 is also connected to the seventh data signal line 112g via the sample hold switch 106g. In the same manner, the first phase development signal line Data1 is connected to the data signal line 112 ahead by six. Similarly, the second to sixth phase development signal lines Data2 to Data6 are sequentially connected to the respective data signal lines that are an integral multiple of six than the second to sixth data signal lines 112b to 112f.
[0068]
The precharge drive circuit 170 turns on the precharge switches 172a, 172b,... At a predetermined timing, and turns the first precharge line 174a or the second precharge line 174b into the data signal lines 112a, 112b,. To precharge the data signal line 112. A first precharge potential PV1 and a second precharge potential PV2 are switched to the first and second precharge lines 174a and 174b each time a scanning signal line is selected via a switch 190. Supplied. In this embodiment, since dot inversion driving is performed, the odd-numbered data signal lines 172a, 172c... Are connected to the first precharge line 174a, and the even-numbered data signal lines 172b, 172d. It is connected to the charge line 174b. Details of this precharge operation will be described later.
[0069]
(N-phase deployment operation)
Next, the operation of N-phase expansion, for example, six-phase expansion, in the phase expansion circuit 32 in the data processing circuit block 30 will be described with reference to FIG.
[0070]
As shown in FIG. 2, the image signal input to the data processing circuit block 30 is an analog signal having data corresponding to each pixel of the liquid crystal panel 100 in time series. The phase expansion circuit 32 that performs six-phase expansion samples this image signal with a reference clock, for example, a dot clock DC. Then, the image signal is sampled, and six phase expansion signals converted to a data length longer than the sampling period are generated. In this embodiment, the dot clock DC is expanded to a data length that is an integral multiple of one period of the dot clock DC, and is expanded into six parallel phase expansion signals. In this sense, the phase expansion circuit 32 has a function of extending the data length and a function of serial-parallel conversion of a serial image signal into a parallel image signal. For example, the first phase development signal output to the first phase development signal line Data1 is, for example, data of the first, seventh, and thirteenth pixels of the image signal, each being 6 times the period of the dot clock DC. The data length is expanded. Similarly, data of 6 pixels ahead is sequentially expanded to the data length.
[0071]
Similarly, in the second phase development signal output to the second phase development signal line Data2, data of the second, eighth, and fourteenth pixels are expanded to the data length and output.
[0072]
In this embodiment, this expansion and expansion operation is performed using an analog interface IC, and an analog image signal is expanded into six phases.
[0073]
In the first embodiment, in the first to sixth phase development signals output to the first to sixth phase development signal lines Data1 to Data6, the head position of each pixel data is one of the dot clock DC. It is output in a state that is sequentially shifted by the period.
[0074]
(Description of specific examples of 6-phase expansion circuit and polarity inversion circuit)
3, 4, and 5 show specific examples of the 6-phase expansion circuit and the polarity inversion circuit. In FIG. 3, the phase expansion circuit 32 includes switches 500a to 500f, capacitors 502a to 502f, and buffers 504a to 504f. For example, sampling clocks SCLK1 to SCLK6 whose phases are shifted as shown in FIG. 6 are input to the switches 500a to 500f in a one-to-one correspondence. When each of the switches 500a to 500f is turned on by the clock, it samples data and charges the capacitors 502a to 502f in the subsequent stage with data charges. Each switch 500a to 500f holds the data potential while being turned off by the clock. Thereby, as shown in FIG. 6, a 6-phase expansion signal is obtained via the buffers 504a to 504f.
[0075]
Amplifying circuits 506a to 506f and polarity inversion circuits 508a to 508f are provided at the subsequent stage of each of the buffers 504a to 504f. An example of the amplifier circuit and the polarity inverting circuit is shown in FIGS.
[0076]
As shown in FIG. 4, the amplifier circuit is composed of, for example, a video amplifier (which may be an operational amplifier) 510. The polarity inverting circuit includes a polarity inverting unit 520 including resistors R1 and R2 and a first transistor TR1, a buffer 530 including a resistor R3 and a second transistor TR2, a resistor R4, and a third transistor TR3. And a switch SW1 that selectively selects the output of the buffers 530 and 540.
[0077]
For convenience of explanation, the case where the output of the video amplifier 510 is a rectangular wave as shown in FIG. 4 will be described. Here, the resistance values of the resistors R1 and R2 in FIG. 4 are substantially equal, and Vdd is 12V. In this case, the potentials at point A and point B in FIG. 4 are substantially line-symmetrical with respect to an intermediate potential, for example, 6 V, as shown in FIG. 4, for example. The potential at point A is, for example, 11V for the black level and 7V for the white level, and the potential at point B is, for example, 1V for the black level and 5V for the white level. As described above, the polarities of the two image signals appearing at the points A and B are inverted with reference to the polarity inversion reference potential between the black levels of both signals. In this embodiment, a signal appearing at the point B is a negative image signal, and a signal appearing at the point A is a positive image signal. Note that the reference potential for polarity inversion is the center potential of the power supply potential Vdd and the ground potential GND, that is, the amplitude center potential Vref of the analog image signal.
[0078]
A negative signal appearing at the point B is output to the terminal C via the buffer 540, and a positive signal appearing at the point A appears at the terminal D via the buffer 530. One of these positive polarity and negative polarity phase development signals is selected and output by the switch SW1 that is switched based on the polarity inversion timing signal.
[0079]
In this embodiment, as shown in FIG. 32, polarity inversion driving is performed for each dot in the extending direction of the scanning signal line, and polarity inversion driving is performed for each line in the extending direction of the data line signal line. The polarity inversion timing is determined so as to match this. Note that the case where precharge is necessary means that polarity inversion driving is performed at least for each line, and dot inversion is not indispensable.
[0080]
FIG. 5 shows another example of the amplifier circuits 506a to 506f and the polarity inversion circuits 508a to 508f shown in FIG. In FIG. 5, an amplifier circuit 510 and differential amplifier circuits 550 and 560 are provided. The level of the image signal input to the differential amplifier circuit 550 through the amplifier circuit 510 is set to a positive potential with respect to the amplitude center potential Vref described above, and is output from the differential amplifier circuit 550 to the terminal C. . Similarly, the level of the image signal input to the differential amplifier circuit 560 via the amplifier circuit 510 is set to a negative potential with respect to the above-described amplitude center potential Vref, and is supplied from the differential amplifier circuit 560 to the terminal D. Is output. The potentials of the terminals C and D are selected and output by switching the switch SW1 based on the polarity inversion timing signal.
[0081]
In the example of FIG. 3, since amplification and polarity inversion are performed after phase expansion, six systems of amplifier circuits 506a to 506f and six systems of polarity inversion circuits 508a to 508f are required. However, since the charge of the signal can be charged to the capacitors 502a to 502f at a stage where the signal amplitude before signal amplification is small, there is an advantage that the charging time is fast and the speed can be increased.
[0082]
(Data sampling configuration)
Next, details of the data side driving circuit 104 which is a characteristic configuration of the present embodiment will be described with reference to a circuit diagram of FIG. 7 and a timing chart of FIG.
[0083]
As shown in FIG. 7, the data side driving circuit 104 includes first to fourth column shift registers 120 to 150. Each of these shift registers 120 to 150 receives an input signal DX that is common shift data shown in FIG. As shown in FIG. 8A, the input signal DX is a signal that becomes HIGH over eight periods of the dot clock signal DC. Further, the first clock signal CLX1 shown in FIG. 7 and the first inverted clock signal thereof are input to the shift register 120 in the first column. As shown in FIG. 8A, the first clock signal CLX1 is repeatedly output with a pulse having a half pulse width of the input signal DX in a cycle of the pulse width of the input signal DX. Similarly, the second to fourth clock signals CLX2 to CLX4 and their inverted clock signals are input to the shift registers 130 to 150 in the second to fourth columns, respectively. The rising timings of the second to fourth clock signals CLX2 to CLX4 are sequentially shifted for each period of the dot clock DC from the rising timing of the first clock signal CLX1.
[0084]
Each of the shift registers 120 to 150 in each column includes a multi-stage master-slave clocked inverter. The first stage of the first shift register 120 will be described. The master first clocked inverter 121a and the inverter 121b are directly connected, and the feedback line connecting the input / output lines of the inverter 121b is connected to the slave line. A second clocked inverter 121c is connected. The master clocked inverter 121a inverts and outputs the input clock signal DX when the first clock signal CLX1 is HIGH. Similarly, the second clocked inverter 121c serving as a slave inverts and outputs the output signal of the inverter 121b when the first inverted clock signal / CLX1 is HIGH.
[0085]
The operation of the first stage in the shift register 120 in the first column will be described with reference to the timing chart of FIG. For reference, various signal waveforms output from the scanning side drive circuit 102 are shown in FIG.
[0086]
In the first half of the input clock signal DX being HIGH (for four periods of the dot clock DC), the first clock signal CLX1 is HIGH, and the LOW obtained by inverting the input signal DX is output as the output of the first clocked inverter 121a. Is output. This LOW signal is inverted by the inverter 121b, and as the first stage output of the first column shift register 120, first, only the first half of the input clock signal DX is HIGH as shown by SR1-OUT1 in FIG. Is output.
[0087]
In the second half of the input clock signal DX, the clock signal CLX1 becomes LOW, while the first inverted clock signal / CLX1 input to the slave second clocked inverter 121c becomes HIGH. The signal input to the second clocked inverter 121c is a HIGH signal from the inverter 121b. As a result, the output from the second clocked inverter 121c is a LOW signal obtained by inverting the input HIGH signal. This LOW signal is inverted by the inverter 121b. Therefore, the HIGH signal is also output in the second half of the first output signal SR1-OUT1 that is the output of the first stage in the shift register 120 in the first column.
[0088]
SR1-OUT1,... SR4-OUT1,... SR3-OUT2 in FIG. 8A indicate the outputs of the shift registers 120 to 150 in the first to fourth columns. Reference numerals SR1 to SR4 indicate the first to fourth columns of the shift register, and reference numerals OUT1, OUT2,... Indicate the outputs of the first, second,.
[0089]
As shown in FIG. 8A, the second to third output signals SR2-OUT1 to SR4-OUT1 are generated by the first stage operation of the shift registers 130 to 150 in the second column to the fourth column, as shown in FIG. Are output in a state of being sequentially shifted by one cycle of the dot clock DC from the rising edge of the output signal SR1-OUT1.
[0090]
The fifth output signal SR1-OUT2 is generated using the second-stage master-slave clocked inverter of the shift register 120 in the first column.
[0091]
When the output signals of the shift registers 120 to 150 in the first to fourth columns are output as they are to the sample and hold switches 106a, 106b,..., The conventional ghost phenomenon described with reference to FIGS.
[0092]
Therefore, in the first embodiment, NAND circuits 160a, 160b,..., Inverters 162a, 162b,... Are provided between the shift registers 120-150 in the first to fourth columns and the sample hold switches 106a, 106b. And are provided.
[0093]
The NAND circuit and the inverter function as a circuit that takes the logical product of two timing signals output from the shift register.
[0094]
A NAND circuit 160a provided in front of the sample and hold switch 106a connected to the first data signal line 112a includes a first output signal SR1-OUT1 from the first stage of the shift register 120 in the first column, and The fifth output signal SR1-OOT2 from the second stage is input. Accordingly, the sampling period signal SL1-Data1 obtained via the NAND circuit 160a and the inverter 162a at the subsequent stage is a logical product of the first output signal SR1-OUT1 and the fifth output signal SR1-OUT2. As shown in FIG. 8A, four periods of the dot clock DC are set as the sampling period.
[0095]
In FIG. 8A, SL1-Data1,... SL4-Data4,... Are applied to the gates of the TFTs of the sample hold switches 106a,. When the signal is represented by SL (n) -Data (m), m (m = 1 to 6) of the code Data (m) indicates the number of the phase development signal lines Data1 to 6 sampled by the signal. . The symbol SL (n) n indicates the order of the sampling period signals.
[0096]
In the previous stage of the sample hold switch 106b connected to the second data signal line 112b, the signal SR2-OUT1 from the first stage of the shift register 130 in the second column and the second stage of the NAND circuit 160b. The signal SR2-OUT2 is input. Therefore, the second sampling period signal SL2-Data2 obtained via the NAND circuit 160b and the subsequent inverter 162b is only one period of the dot clock DC than the first sampling period signal SL1-Data1. Although the rise is delayed, the sampling period is similarly a period of four cycles of the dot clock DC. The same applies to the data signal lines after the third data signal line.
[0097]
(About data sampling operation)
FIG. 9 shows the relationship between the phase expansion signals Data1 to Data6 input to each sample and hold switch 106 and the sampling period signal SL (n) -Data (m). FIG. 9 shows sampling period signals SL1-Data1, SL7-Data1, and SL13-Data1 for sampling the phase expansion signal Data1. As shown in FIG. 9, information having a data length corresponding to six periods of the dot clock DC is input to the first sample hold switch 106a to the source line of the TFTs constituting the sample hold switch 106a. On the other hand, the sampling period signal SL1-Data1 that has passed through the NAND circuit 160a and the inverter 162a is input to the gate of the TFT constituting the sample hold switch 106a. The sampling period signal Sl-Data1 has a sampling period (High period) in which the data length of the phase expansion signal is six periods of the dot clock signal, whereas one period is removed before and after that. ) Is set.
[0098]
By setting such a sampling period, even if the sample hold switch 106 is configured by a TFT and the writing capability of the TFT is limited, it is not affected by the previous data on the liquid crystal display, in other words, A liquid crystal display without ghosting can be performed.
[0099]
This is because the gate of the TFT constituting the sample hold switch 106 is opened by the high level of the sampling period signal after the image data on the phase development signal line is stabilized. In addition, the gate of the TFT is closed before the data on the phase development signal line changes. Further, the sample hold switches 106a, 106g, 106n,... Connected to the same phase development signal line Data1 open and close the gates as is apparent from the shift in the high level period of SL1-Data1, SL7-Data1, SL13-Data1. Driven at different timings, a plurality of gates are not opened simultaneously. Thus, by setting the sampling period only for the stable data region in the data length of the phase development signal, only stable data that is not affected by the previous data can be sent to the data signal line 112. it can. This data is written into the liquid crystal layer 116 and the storage capacitor via the switching element 114 that is turned on by the scanning signal from the scanning side driving circuit 102.
[0100]
In the same manner, stable data is sequentially sent to the corresponding data signal lines 112b, 112c,... Via the sampling switches 106b, 106c, and the first scanning signal line 110a via the switching element 114. Writing to the connected liquid crystal layer 116 is performed by dot sequential driving. Thereafter, the above-described data writing is repeatedly performed while the switching elements 114 connected to the second and subsequent scanning signal lines 110 are sequentially turned on by the scanning signal from the scanning side driving circuit 102.
[0101]
(About precharge operation)
In this embodiment apparatus, each data signal line has the same polarity as the voltage applied to the pixel based on the pixel data sampled in the sampling period before the above-described sampling period for each data signal line. Is precharged.
[0102]
The necessity of this precharge will be briefly described with reference to FIGS. First, the scanning signal line 110a is selected in the first selection period (TFT 114a is turned on), and the counter substrate electrode (common electrode) shown in FIG. 10A is used as a reference via the data signal line 112a to the liquid crystal cell 116a. Assuming that black display is performed by writing a negative black level potential B1. In the next selection period after one horizontal scan, the scanning signal line 110b is selected (TFT 114b is turned on), and the positive black level potential B2 is written to the liquid crystal cell 116b through the same data signal line 112a as the previous time. Displays black. In this case, since the polarity is inverted even in the same black display, the black level potentials B1 and B2 have the largest potential difference as shown in FIG.
[0103]
Therefore, in order to charge the parasitic capacitance C of the data signal line by the image signal itself, as shown by “R1” in FIG. _SAM In addition, the potential of the data signal line must be changed from the black level potential B1 to B2.
[0104]
However, in the present embodiment, as described above, the sampling period T is shorter than the conventional sampling period of FIG. _SAM It is difficult to change the data signal line from the black level potential B1 to B2 or vice versa.
[0105]
Therefore, the sampling period T shown in FIG. _SAM Precharge period T prior to _PRE Thus, the data signal line 112a is precharged at the second precharge potential PV2 having the same polarity as the voltage applied to the pixel by the image signal. In this way, the precharge period T _PRE In addition, the second precharge potential PV2 can be precharged in a relatively short time from the black level potential B1. Subsequent sampling period T _SAM Then, it is only necessary to change the second precharge potential PV2 to the black level potential B2. This precharge period T _PRE And sampling period T _SAM Since the amount of charge (discharge) of the parasitic capacitance C of the data signal line is small, charging / discharging can be performed in a short time.
[0106]
In this embodiment, a precharge period set by the precharge drive circuit 170 will be described with reference to FIG.
[0107]
FIG. 11 shows one horizontal scanning period H _n And the next horizontal scanning period H _{n + 1} Sampling period T of each data signal line in a period extending to _SAM Is shown. Precharge period T _PRE Is the sampling period T from the start of the horizontal scanning period _SAM It is set at any time until the start of.
[0108]
In order to set a common precharge period for each data signal line, a horizontal blanking period B _n , B _{n + 1} It should be set to…. This horizontal blanking period B _n , B _{n + 1} This is because the sampling period is not set for any of the data signal lines.
[0109]
As is apparent from FIG. 11, the sampling period can be used as it is for the other data signal lines as the precharge period to be set before the sampling period set for a certain data signal line. For example, the sampling period T of the data signal line 112a _SAM As indicated by a broken line in FIG. 11, a (n) is a sampling period T such as a data signal line 112e or 112f. _SAM e (n), T _SAM Precharge period T to be set before f (n) _PRE e (n), T _PRE It can also be used as f (n). Sampling period T of data signal line 112a _SAM a (n) is the sampling period T of the data signal lines 112e, 112d. _SAM e (n), T _SAM This is because it does not overlap with f (n). In this case, it is not necessary to provide the precharge circuit 170 separately from the data side driving circuit 104 shown in FIG. Details of an embodiment using one data line driving circuit functioning as the data side driving circuit 104 and the precharge driving circuit 170 will be described later in a third embodiment shown in FIGS.
[0110]
(2) Second embodiment
In the second embodiment, liquid crystal display driving is performed using a phase expansion signal having a data length corresponding to six periods of the dot clock and a sampling period signal having a sampling period corresponding to three periods of the dot clock. is there.
[0111]
As shown in FIG. 12, the data side drive circuit 104 includes first to third columns of shift registers 200 to 220. Each of the shift registers 200 to 220 receives an input signal DX as common shift data as shown in FIG. As shown in FIG. 13, the input signal DX is a signal that becomes HIGH over the six periods of the dot clock signal DC. Further, the first clock signal CLK1 and its first inverted clock signal / CKL1 shown in FIG. 13 are input to the shift register 200 in the first column. As shown in FIG. 13, the first clock signal CLK1 is repeatedly output with a pulse having a half pulse width of the input signal DX in a cycle of the pulse width of the input signal DX. Similarly, the second and third clock signals CLK2 and CLK3 and their inverted clock signals / CLK2 and / CLK3 are input to the shift registers 210 and 220 in the second and third columns, respectively. The rising timings of the second and third clock signals CLK2 and CLK3 are sequentially shifted for each period of the dot clock DC from the rising timing of the first clock signal CLK1.
[0112]
The shift registers 200 to 220 in each column are configured to include multi-stage master slave clocked inverters.
[0113]
The output signals SR1-OUT1,... SR3-OUT2 of the shift registers 200 to 220 in the first to third columns are as shown in FIG.
[0114]
A NAND circuit 160a provided in front of the sample and hold switch 106a connected to the first data signal line 112a has a first output signal SR1-OUT1 from the first stage of the shift register 200 in the first column, and The fourth output signal SR1-OUT2 from the second stage is input. Therefore, the sampling period signal SL1-Data1 obtained via the NAND circuit 160a and the inverter 162a at the subsequent stage is a logical product of the first output signal SR1-OUT1 and the fourth output signal SR4-OUT2. As shown in FIG. 13, three periods of the dot clock DC are set as the sampling period.
[0115]
Similarly, in the previous stage of the sample and hold switch 106b connected to the second data signal line 112b, the signal SR2-OUT1 from the first stage of the shift register 210 of the second column and the second stage shift register 210 are compared with the NAND circuit 160b. The signal SR2-OUT2 from the second stage is input. Therefore, the second sampling period signal SL2-Data2 obtained via the NAND circuit 160b and the subsequent inverter 162b is only one period of the dot clock DC than the first sampling period signal SL1-Data1. Although the rise is delayed, the sampling period is similarly a high period of three periods of the dot clock DC. The same applies to the data signal lines after the third data signal line.
[0116]
Note that the seventh sampling period signal SL7-Data1 in FIG. 13 is a signal for sampling the same phase development signal line Data1 as the first sampling period signal SL1-Data1. As apparent from FIG. 13, the sampling periods of both are set to be shifted.
[0117]
(About data sampling operation)
FIG. 14 shows the relationship between the phase expansion signals Data1 to Data6 input to each sampling switch 102 and the sampling period signal SL (n) -Data (m). FIG. 14 shows a waveform similar to FIG. For example, as shown in FIG. 14, information having a data length of six periods of the dot clock DC is input to the first sample hold switch 106a to the source line of the TFT constituting the sample hold switch 106a. On the other hand, the sampling period signal SL1-Data1 that has passed through the NAND circuit 160a and the inverter 162a is input to the gate of the TFT constituting the sample hold switch 106a. As shown in FIG. 14, the sampling period signal SL1-Data1 has three periods in which the data length of the phase expansion signal is six periods of the dot clock signal, and 1.5 periods are removed before and after the sampling period signal SL1-Data1. A sampling period of minutes is set. Therefore, as in the first embodiment, it is possible to write stable data that is not affected by the previous data.
[0118]
(About precharge operation)
In the second embodiment, the length of the sampling period is different from that of the first embodiment, so that the precharge period can be set in the same manner as in FIG.
[0119]
(3) Third embodiment
In the third embodiment, liquid crystal display driving is performed using a phase expansion signal having a data length corresponding to six periods of the dot clock and a sampling period signal having a sampling period corresponding to two periods of the dot clock.
[0120]
The difference from the first embodiment is that the data side drive circuit shown in FIGS. 1 and 7 is changed to that shown in FIGS. That is, in the third embodiment, the data side drive circuit 104 and the precharge drive circuit 170 shown in FIGS. 1 and 7 are changed to one data signal line drive circuit 180 shown in FIG. The data signal line driving circuit 180 is used both for setting the precharge period and setting the sampling period.
[0121]
(About the configuration of the data signal line drive circuit)
As shown in FIG. 16, the data signal line driving circuit 180 includes first and second columns of shift registers 300 and 310. As shown in FIG. 17, the input signal DX serving as shift data input in common to each of the shift registers 300 and 310 is a signal that becomes HIGH over four periods of the dot clock signal DC. Further, the first clock signal CLK1 and its first inverted clock signal shown in FIG. 16 are input to the shift register 300 in the first column. As shown in FIG. 17, the first clock signal CLK1 is repeatedly output with a pulse having a half pulse width of the input signal DX in a cycle of the pulse width of the input signal DX. Similarly, the second clock signal CLK2 and its inverted clock signal are input to the shift register 310 in the second column. The rising timing of the second clock signal CLK2 is shifted by one cycle of the dot clock DC from the rising timing of the first clock signal CLK1.
[0122]
Each of the shift registers 300 and 310 in each column includes a multi-stage master-slave clocked inverter.
[0123]
The output signals SR1-OUT1,... SR1-OUT4 of the shift registers 300, 310 in the first column and the second column are as shown in FIG.
[0124]
A NAND circuit 160a provided before the sample and hold switch 106a connected to the first data signal line 112a includes a first output signal SR1-OUT1 from the first stage of the shift register 300 in the first column, and The third output signal SR1-OUT2 from the second stage is input. Accordingly, the sampling period signal SL1-Data1 obtained via the NAND circuit 160a and the inverter 162a at the subsequent stage is a logical product of the first output signal SR1-OUT1 and the third output signal SR1-OUT2. As shown in FIG. 17, a period of two cycles of the dot clock DC is set as the sampling period.
[0125]
Similarly, in the previous stage of the sample and hold switch 106b connected to the second data signal line 112b, the signal SR2-OUT1 from the first stage of the shift register 310 in the second column and the second stage shift register 310 are compared with the NAND circuit 160b. The signal SR2-OUT2 from the second stage is input. Therefore, the second sampling period signal SL2-Data2 obtained via the NAND circuit 160b and the subsequent inverter 162b is only one period of the dot block DC than the first sampling period signal SL1-Data1. Although the rise is delayed, the sampling period is similarly a period of two cycles of the dot clock DC. The same applies to the data signal lines after the third data signal line.
[0126]
In the third embodiment, as shown in FIGS. 15 and 16, for example, one end of the data signal line 112a is connected in parallel with a sample hold switch 106a and a precharge switch 172a. The same applies to the other data signal lines.
[0127]
Further, in the third embodiment, as shown in FIG. 16, the sampling period signal SL1-Data1 obtained from the inverter 162a is inputted to the control terminal of the precharge switch 172d connected in parallel with the sampling switch 106d. As a result, the sampling period signal SL1-Data1 for the data signal line 112a is also used as a precharge period signal for the data signal line 172d. Thus, in the third embodiment, the sampling period signal for the nth data signal line is also used as the precharge period signal for the (n + 3) th data signal line.
[0128]
(About data sampling operation)
FIG. 18 shows the relationship between the phase expansion signals Data1 to Data6 input to each sampling switch 102 and the sampling period signal SL (n) -Data (m). FIG. 18 shows a waveform of a signal similar to that in FIG. For example, as shown in the figure, information having a data length corresponding to six periods of the dot clock DC is input to the first sample hold switch 106a to the source line of the TFT constituting the sample hold switch 106a. On the other hand, the sampling period signal SL1-Data1 that has passed through the NAND circuit 160a and the inverter 162a is input to the gate of the TFT constituting the sample hold switch 106a. The sampling period signal SL1-Data1 is set to a sampling period for two periods in which the data length of the phase expansion signal is six periods of the dot clock signal DC, but two periods before and after that are removed. ing. Therefore, as in the first and second embodiments, it is possible to write stable data that is not affected by the previous data.
[0129]
(About precharge operation)
A precharge operation performed before the data sampling will be described with reference to FIG. FIG. 19 shows a precharge period T set for each data signal line. _PRE And sampling period T _SAM Shows the relationship.
[0130]
As described above, the data signal line driving circuit 180 uses the sampling period set for the nth data signal line as the precharge period for the n + 3th data signal line. That is, as shown in FIG. 19, the sampling period set for the first data signal line 112a is also used as the precharge period for the fourth data signal line 112d. Similarly, the sampling period set for the second data signal line 112b is also used as a precharge period for the fifth data signal line 112e. Thus, since the sampling period signal can also be used as a precharge signal, a precharge switch and a sampling switch are connected in parallel to one end of the data signal line as shown in FIGS. It is only necessary to provide one data signal line driving circuit 180 for driving. Therefore, the circuit scale is reduced as compared with the case of FIG. 1, the circuit layout is facilitated, and the circuit board can be reduced in size.
[0131]
Here, an interval corresponding to one cycle of the dot clock DC shown in FIG. 18 is provided between the precharge period and the sampling period set for the same data signal line. Therefore, the sampled data potential can be supplied to the data signal lines that have been precharged by turning off the precharge switches 172a, 172b. In particular, even if a supply line for a precharge period signal for setting a precharge period is routed and a delay occurs due to the parasitic capacitance of the supply line, the precharge switch and the sampling switch are It is possible to prevent a situation in which they are turned on at the same time. If both switches are turned on at the same time, a potential other than the original data is sampled and the image quality is deteriorated, but this embodiment can prevent the adverse effects.
[0132]
Here, in FIG. 11 illustrating the setting of the precharge period in the first embodiment, the nth data signal is used in order to leave the same interval as that in the third embodiment between the precharge period and the sampling period. The sampling period for the line must be set as the precharge period for the n + 5th data signal line. In this regard, in the third embodiment, by making the length of the sampling period shorter than that in the first embodiment, the length of the precharge period signal line can be shortened, the circuit layout becomes simpler, and the pre- The delay of the charge period signal is also reduced.
[0133]
(4) Fourth embodiment
In the fourth embodiment, the dot sequential driving in the first and third embodiments is changed to the same number of phase expansions, for example, 6 pixel simultaneous driving. For example, in the case of an engineering workstation (EWS), the dot clock is increased in frequency (for example, 130 MHz), and the phase difference for dot sequential driving is 10 nsec or less. In this case, if the sample hold switch is a TFT, switching cannot be followed. Therefore, multiple simultaneous driving is effective in such a case. Hereinafter, the fourth embodiment will be described with reference to FIGS.
[0134]
(Configuration of data processing circuit block and phase expansion signal)
In the fourth embodiment, the first to sixth phase development signals output to the first to sixth phase development signal lines Data1 to Data6 are used for each pixel data in order to realize 6 pixel simultaneous writing. The head position of switching is coincident as shown in FIG.
[0135]
Therefore, in the fourth embodiment, the data processing block 30 shown in FIG. 20 has a sample hold circuit 36 added between the phase expansion circuit 32 and the amplification / inversion circuit 34. By the first sample and hold operation in the phase development circuit 32, as shown in FIG. 2, the head position of each pixel data of each phase development signal is shifted by one period of the dot clock DC. However, the sample hold circuit 36 at the subsequent stage collectively samples and holds again, so that the first to sixth phase output signal lines Data1 to Data6 output to the first to sixth phase development signal lines Data1 to Data6 as shown in FIG. In the phase development signal, the head positions of the respective pixel data coincide. A buffer memory can be used as the sample and hold circuit 36 in the subsequent stage. In addition, an amplification / inversion circuit 34 may be arranged before the phase expansion circuit 32.
[0136]
(Configuration and operation of data side drive circuit)
As shown in FIG. 20, the data side drive circuit 104 includes a shift register 400 in the first column. The input signal DX, the clock signal CLK, and its inverted clock signal, which are the shift data input to the shift register 400, are the input signal DX, the first clock signal CLX, and its inverted signal of the first embodiment shown in FIG. It is the same as the clock signal. That is, as shown in FIG. 21, the input signal DX is a signal that becomes HIGH over 8 periods of the dot clock signal DC. Further, as shown in FIG. 21, the clock signal CLK is repeatedly output with a pulse having a half pulse width of the input signal DX in a cycle of the pulse width of the input signal DX.
[0137]
The shift register 400 includes a multi-stage master-slave clocked inverter. The output signals SL1,... SL8 at each stage of the shift register 400 are as shown in FIG.
[0138]
In the fourth embodiment, the first output from the first stage of the shift register 400 is connected to the gates of the sample hold switches 106a to 106f connected to the first to sixth data signal lines 112a to 112f. The signal SL1 is input in common.
[0139]
Similarly, the fourth output signal SL4 from the fourth stage of the shift register 400 is common to the gates of the sample hold switches 106g to 106l connected to the seventh to twelfth data signal lines 112g to 112l. Is input. The same applies to the data signal lines after the thirteenth data signal line.
[0140]
As a result, as shown in FIG. 22, a period of four periods of the dot clock DC is set in common as a sampling period for a phase expansion signal having a data length of six periods of the dot clock DC. Accordingly, as in the first to third embodiments, it is possible to write stable data that is not affected by the previous data.
[0141]
In the fourth embodiment, the same input signal DX, clock signal CLX and its inverted clock signal as those in the first embodiment are used, but the corresponding signals in the second and third embodiments can be used. When the signal of the second embodiment is used, a period of three periods of the dot clock DC is set in common as a sampling period. Similarly, when the signal of the third embodiment is used, two periods of the dot clock DC are set in common as the sampling period.
[0142]
(About precharge operation)
The precharge timing in the fourth embodiment will be described with reference to FIG. In the fourth embodiment, the sampling period T of the six data signal lines 112 (g) to 112 (l) sampled simultaneously. _SAM Precharge period T set before 2 _PRE 2, the sampling period T of the six data signal lines 112 a to 112 h sampled simultaneously. _SAM 1 is also used. Alternatively, all data signal lines can be precharged within the horizontal blanking period.
[0143]
(5) Fifth embodiment
The fifth embodiment is a modification of the first to third embodiments. As shown in FIG. 24, the data processing circuit block 30 first performs amplification and polarity inversion, and then performs six-phase development. ing. In this case, as shown in FIG. 24, only one system of amplification / polarity inversion circuit 34 is required. Therefore, the circuit scale is reduced as compared with the case of FIG. 3, and the variation in the signal potential between the six phase development signal lines is reduced only by the DC offset of the six sample hold circuits. Note that the variation in the signal potential between the six phase development signal lines in the case of FIG. 3 becomes larger due to the addition of the gain variation in the six video amplifiers. The amplifier / polarity inverting circuit 34 shown in FIG. 24 may use the configuration shown in FIG. 5, and the same applies to the sixth and subsequent embodiments described below.
[0144]
(6) Sixth embodiment
The sixth embodiment is a modification of the fourth embodiment. As in the fifth embodiment, as shown in FIG. 25, the data processing circuit block 30 first performs amplification and polarity inversion, and then the six-phase operation. Deployment is in progress. In this case, as shown in FIG. 25, only one system of the amplification / polarity inversion circuit 34 is required. Therefore, the circuit scale is reduced as compared with the case of FIG. 3, and variations in the signal potentials of the six image signal lines are reduced.
[0145]
FIG. 26 is a timing chart for explaining the operation of the circuit of FIG. As described above, the output of the phase expansion circuit 32 in FIG. 25 corresponds to the first sample-hold output shown in FIG. The switches 550a to 550f provided in the sample hold circuit 36 of FIG. 25 are simultaneously turned on / off based on the second sample hold clock SCLK7 of FIG. As a result, the output positions of the buffers 554a to 554f in FIG. 25 coincide with the start positions of the respective pixel data as shown as the second sample hold output in FIG. The precharge operation can be performed in the same manner as in the fourth embodiment.
[0146]
(7) Seventh embodiment
The seventh embodiment shows a modification of FIG. 25. As shown in FIG. 27, two sample and hold circuits 36 and 38 are provided in the subsequent stage of the phase expansion circuit 32. FIG. 28 is a timing chart for explaining the operation of the circuit of FIG. The output of the phase expansion circuit 32 in FIG. 27 corresponds to the first sample hold output shown in FIG. The switches 550a to 550c provided in the sample hold circuit 36 of FIG. 27 are simultaneously turned on / off based on the sampling clock SCLK7 of FIG. As a result, the output positions of the buffers 554a to 554c in FIG. 27 coincide with each other at the head position of each pixel data as shown as the second sample hold output in FIG. The switches 550d to 550f provided in the sample hold circuit 36 of FIG. 27 are simultaneously turned on / off based on the sampling clock SCLK8 of FIG. As a result, the output positions of the buffers 554a to 554c in FIG. 27 coincide with each other at the head position of each pixel data as shown as the second sample hold output in FIG. The switches 560a to 560f provided in the sample-and-hold circuit 38 in the final stage of FIG. 27 are simultaneously turned on / off based on the sampling clock SCLK9 of FIG. As a result, the outputs of the buffers 564a to 564f in FIG. 27 coincide with the start positions of the respective pixel data as shown as the third sample hold output in FIG.
[0147]
In this way, in each data sampling, it is possible to always sample the portion that is not the end of the data area of the data length that has been expanded into six phases. Therefore, unnecessary components are prevented from being mixed into the waveform supplied to the display element of the liquid crystal panel, and the image quality is improved. The precharge operation in this case is also performed in the same manner as in the fourth embodiment.
[0148]
(8) Eighth embodiment
In the eighth embodiment, the polarity inversion driving for each dot and each line of the liquid crystal panel is possible, and the deviation of the signal variation among the six phase development signal lines is reduced.
[0149]
As shown in FIG. 29, first and second polarity inversion circuits 600 and 610 for inputting the output of the video amplifier 510 are provided. The circuit configurations of the first and second polarity inversion circuits 600 and 610 are the same as those in FIG. 4, and the last-stage switches are referred to as a first switch SW1 and a second switch SW2, respectively. The first and second switches SW1 and SW2 are driven so as to select different polarities in the case of dot inversion driving. When only line inversion is performed, the first and second switches SW1 and SW2 are driven so as to select the same polarity.
[0150]
The output of the first switch SW1 is input to the first, third, and fifth switches 500a, 500c, and 500e of the phase expansion circuit 34. The output of the second switch SW2 is input to the second, fourth, and sixth switches 500b, 500d, and 500f of the phase expansion circuit 34.
[0151]
Six types of sampling clocks SHCL1 to SHCL6 for driving the first to sixth switches 500a to 500f are prepared as shown in FIG. 30, and are generated by the timing generation circuit block 20 based on the select signals S1 to S6. In this apparatus, the supply of six types of sampling clocks SHCL1 to SHCL6 is selected and switched from the patterns of S1 to S6 based on horizontal synchronization and vertical synchronization of driving of the liquid crystal panel 10. For this purpose, a hex counter for counting the horizontal synchronizing signal is provided in the timing generation circuit 20. In other words, every time the hex counter counts, in other words, for each horizontal scan (1H) in which the scanning signal line 110 in FIG. 1 is newly selected, the select signals S1 to S6 are sequentially switched and output.
[0152]
Here, the phase expansion signal outputs of the buffers 504a to 504f which are the outputs of the phase expansion circuit 32 are abbreviated as V1 to V6, respectively. When the outputs V1 to V6 are rearranged at the pixel positions, the driving method shown in FIG. 31 can be considered.
[0153]
In FIG. 31, the first line is the select signal S1, the second line is the select signal S2, the third line is the select signal S3,... The sixth line is switched in accordance with the select signal S6, and this is repeated for the subsequent lines. Yes. In FIG. 31, + and − indicate the polarity of data, and so-called dot inversion drive as shown in FIG. 31 is possible by switching the first and second switches SW1 and SW2 by a signal from the timing generation circuit block 20. It becomes. 31 are represented by serial pixel data a1, a2,... (First line), b1, b2,... (Second line), they must be supplied to each pixel as shown in FIG.
[0154]
In the eighth embodiment, six phase development signal output lines 505a to 505f and six phase development signal supply lines Data1 to Data6 are provided so that the output of FIG. 31 is supplied to each pixel as shown in FIG. A connection switching circuit (rotation circuit) 700 is provided for switching the connection to. This switching needs to be performed in synchronism with the switching of the phase expansion sequence in the phase expansion circuit 34 described above, and is selected from the six patterns shown in FIG. 30 based on the signal from the timing generation circuit block 20. By this switching, the dot inversion driving shown in FIG. 32 can be realized.
[0155]
Here, according to the eighth embodiment, even if there is a variation in the gain of the amplifier, for example, in the middle of the six phase development signal lines, for example, even if the gain of a certain amplifier is high, it is bright as in the prior art. Since the pixels do not continue in the vertical direction of the liquid crystal panel 100 and are scattered in an oblique direction, it can be visually inconspicuous.
[0156]
(9) Ninth embodiment
An electronic apparatus configured using the image display devices of the above-described embodiments includes a display information output source 1000, a display information processing circuit 1002, a display driving circuit 1004, a display panel 1006 such as a liquid crystal panel, and a clock generator shown in FIG. A circuit 1008 and a power supply circuit 1010 are included. The display information output source 1000 is configured to include a memory such as a ROM and a RAM, a tuning circuit that tunes and outputs a television signal, and the like, based on a clock from the clock generation circuit 1008 corresponding to the timing circuit block 20 described above. Display information such as video signals. The display information processing circuit 1002 corresponds to the data processing circuit block 30 of each of the above-described embodiments, and processes and outputs display information based on the clock from the clock generation circuit 1008. The display information processing circuit 1002 can include a gamma correction circuit, a clamp circuit, and the like in addition to the above-described amplification / polarity inversion circuit, phase expansion circuit, rotation circuit, and the like. The drive circuit 1004 includes the above-described scan side drive circuit 102, data side drive circuit 104, precharge drive circuit 160, or data line drive circuit 180, and drives the liquid crystal panel 1006 to display. The power supply circuit 1010 supplies power to each of the circuits described above.
[0157]
As an electronic apparatus having such a configuration, a liquid crystal projector shown in FIG. 34, a personal computer (PC) and engineering workstation (EWS) corresponding to multimedia shown in FIG. 35, a pager shown in FIG. 36, a mobile phone, a word processor, Examples include a television, a viewfinder type or a monitor direct view type video tape recorder, an electronic notebook, an electronic desk calculator, a car navigation device, a POS terminal, and a device equipped with a touch panel.
[0158]
The liquid crystal projector shown in FIG. 34 is a projection type projector using a transmissive liquid crystal panel as a light valve, and uses, for example, a three-plate prism type optical system. In FIG. 34, in the projector 1100, the projection light emitted from the lamp unit 1102 of the white light source is divided into three primary colors R, G, and B by a plurality of mirrors 1106 and two dichroic mirrors 1108 inside the light guide 1104. And led to three active matrix liquid crystal panels 1110R, 1110G, and 1110B that display images of the respective colors. The light modulated by the respective liquid crystal panels 1110R, 1110G, and 1110B is incident on the dichroic prism 1112 from three directions. In the dichroic prism 1112, the red R and blue B lights are bent by 90 °, and the green G light travels straight, so that images of the respective colors are synthesized, and a color image is projected onto a screen or the like through the projection lens 1114.
[0159]
A personal computer 1200 shown in FIG. 35 includes a main body 1204 provided with a keyboard 1202 and a liquid crystal display screen 1206.
[0160]
A pager 1300 shown in FIG. 36 includes a liquid crystal display substrate 1304, a light guide 1306 provided with a backlight 1306a, a circuit substrate 1308, first and second shield plates 1310 and 1312, and two elastic conductors in a metal frame 1302. It has a body 1314, 1316 and a film carrier tape 1318. The two elastic conductors 1314 and 1316 and the film carrier tape 1318 connect the liquid crystal display substrate 1304 and the circuit substrate 1308.
[0161]
Here, the liquid crystal display substrate 1304 is obtained by enclosing liquid crystal between two transparent substrates 1304a and 1304b, and thereby at least a liquid crystal display panel is configured. A driving circuit 1004 shown in FIG. 33 or a display information processing circuit 1002 can be formed on one transparent substrate. A circuit that is not mounted on the liquid crystal display substrate 1304 is an external circuit of the liquid crystal display substrate, and can be mounted on the circuit substrate 1308 in the case of FIG.
[0162]
Since FIG. 36 shows the configuration of the pager, the circuit board 1308 is necessary. However, when a liquid crystal display device is used as a component for an electronic device and a display driving circuit or the like is mounted on a transparent substrate, the minimum unit of the liquid crystal display device is a liquid crystal display substrate 1304. . Alternatively, a liquid crystal display substrate 1304 fixed to a metal frame 1302 as a housing can be used as a liquid crystal display device which is a component for electronic equipment. Further, in the case of the backlight type, a liquid crystal display device can be configured by incorporating a liquid crystal display substrate 1304 and a light guide 1306 provided with a backlight 1306a in a metal frame 1302. Instead of these, as shown in FIG. 37, a TCP in which an IC chip 1324 is mounted on a polyimide tape 1322 having a metal conductive film formed on one of two transparent substrates 1304a and 1304b constituting a liquid crystal display substrate 1304. (Tape Carrier Package) 1320 can be connected to be used as a liquid crystal display device which is one component for electronic equipment.
[0163]
In addition, this invention is not limited to the said Example, A various deformation | transformation implementation is possible within the range of the summary of this invention. For example, the present invention is not limited to those applied to driving the above-described various liquid crystal panels, but can also be applied to an image display device using electroluminescence, a plasma display device, a CRT, or the like. The number of phase expansion, the data length of the phase expansion signal and the length of the sampling period corresponding to the number of phase expansion signals, or the setting position and length of the precharge period can be variously modified other than the above embodiments.
[0164]
In the above embodiment, the analog image signal is phase-expanded and sampled and held, but the capacity for phase expansion and sampling in the embodiment can be a digital memory. In this case, the digital image signal is converted as parallel 4-bit data into data 1-1 to 1-4,..., Data6-1 to 6-4, and the data 1-1 to 1-4 are converted into the same sampling period. Sampling is performed by a latch circuit according to a signal. The output of the latch circuit is D / A converted or pulse width modulated, output to the data signal line, and supplied to the liquid crystal layer 116 via the switching element 114.
[0165]
In the above-described embodiments, the example in which the TFT is used as the switching element of the pixel has been described. However, the switching element may be a two-terminal element such as an MIM. In this case, since the two-terminal element and the liquid crystal layer are connected in series between the scanning signal line and the data signal line to configure the pixel, the voltage difference between the two signal lines is supplied to the pixel.
[0166]
In the above embodiment, the TFT is used as a switching element, and the substrate on which the liquid crystal panel element is formed is a glass or quartz substrate, but a semiconductor substrate can be used instead. In this case, not a TFT but a MOS transistor serves as a switching element.
[0167]
[Brief description of the drawings]
FIG. 1 is a schematic explanatory diagram of an active matrix liquid crystal display device according to a first embodiment of the present invention.
FIG. 2 is a schematic explanatory diagram for explaining a six-phase deployment drive.
FIG. 3 is a circuit diagram showing a circuit configuration example of a data processing circuit block in FIG. 1;
4 is a circuit diagram showing a specific example of the amplifier / polarity inverting circuit shown in FIG. 3; FIG.
FIG. 5 is a circuit diagram showing another specific example of the amplifier / polarity inversion circuit shown in FIG. 3;
FIG. 6 is a timing chart showing the operation of the phase expansion circuit of FIG. 3;
FIG. 7 is a circuit diagram illustrating details of a data side driving circuit according to the first embodiment;
8A is a timing chart of the data side driving circuit shown in FIG. 7, and FIG. 8B is a timing chart of the scanning side driving circuit.
FIG. 9 is a characteristic diagram showing the relationship between the data length of the phase expansion signal and the sampling period in the first embodiment.
FIGS. 10A and 10B are schematic explanatory diagrams for explaining a precharge operation. FIGS.
FIG. 11 is a schematic explanatory diagram for explaining a precharge period in the first embodiment;
FIG. 12 is a circuit diagram showing details of a data side driving circuit according to a second embodiment of the present invention.
FIG. 13 is a timing chart of the data side processing circuit shown in FIG. 12;
FIG. 14 is a characteristic diagram showing the relationship between the data length of the phase expansion signal and the sampling period in the second embodiment.
FIG. 15 is a schematic explanatory diagram for explaining a precharge period in the second embodiment;
FIG. 16 is a circuit diagram showing details of a data signal line driving circuit according to a third embodiment of the present invention.
FIG. 17 is a timing chart of the data signal line driver circuit shown in FIG. 16;
FIG. 18 is a characteristic diagram showing the relationship between the data length of the phase expansion signal and the sampling period in the third embodiment.
FIG. 19 is a schematic explanatory diagram for explaining a precharge period in the third embodiment;
FIG. 20 is a circuit diagram showing details of a data side driving circuit and a data processing circuit block according to a fourth embodiment of the present invention.
FIG. 21 is a timing chart of the data side driving circuit shown in FIG. 20;
FIG. 22 is a characteristic diagram showing the relationship between the data length of the phase expansion signal and the sampling period in the fourth embodiment.
FIG. 23 is a schematic explanatory diagram for explaining a precharge period in the fourth embodiment;
FIG. 24 is a circuit diagram showing a configuration example of a data processing circuit block according to a fifth embodiment of the present invention.
FIG. 25 is a circuit diagram showing a configuration example of a data processing circuit block according to a sixth embodiment of the present invention.
FIG. 26 is a timing chart showing a phase expansion operation in the circuit of FIG.
FIG. 27 is a circuit diagram showing a configuration example of a data processing circuit block according to a seventh embodiment of the present invention.
28 is a timing chart showing a phase expansion operation in the circuit of FIG. 27. FIG.
FIG. 29 is a circuit diagram showing a configuration example of a data processing circuit block according to an eighth embodiment of the present invention.
30 is a schematic explanatory diagram for explaining the types of sampling period signals input to the phase expansion circuit shown in FIG. 29 and the line connection state switched by the connection switching circuit correspondingly. .
FIG. 31 is a schematic explanatory diagram in which the buffer output shown in FIG. 29 at the time of polarity inversion driving for each dot is rearranged to pixel positions.
FIG. 32 is a schematic explanatory diagram showing the polarity of pixel data in the polarity inversion driving for each dot achieved by the driving of FIG. 31;
FIG. 33 is a block diagram of an electronic apparatus according to a ninth embodiment of the present invention.
FIG. 34 is a schematic explanatory diagram of a projector to which the present invention is applied.
FIG. 35 is an external view of a personal computer to which the present invention is applied.
FIG. 36 is an exploded perspective view of a pager to which the present invention is applied.
FIG. 37 is a schematic perspective view showing an example of a liquid crystal display device including an external circuit.
FIG. 38 is a schematic explanatory diagram for explaining a problem at the time of phase expansion.
FIG. 39 is a schematic explanatory diagram for explaining the generation of a ghost when an image is displayed using the phase development signal of FIG.
40 is a waveform diagram in which the ghost of FIG. 39 is generated and schematically shows the voltage waveform supplied to the liquid crystal layer.
[Explanation of symbols]
10 LCD panel block
20 Timing circuit block
30 data processing blocks
32 phase expansion circuit
34 Amplification / Inversion Circuit
36 Sample hold circuit
100 LCD panel
102 Scanning side drive circuit
104 Data side drive circuit
106 Sample hold switch
110 Scanning signal line
112 Data signal line
114 Switching element
116 Liquid crystal layer
120-150 shift register
170 Precharge drive circuit
172a, b Precharge switch
174a, b First and second precharge lines
180 Data signal line driving circuit
300, 310 shift register

Claims (7)

An image display unit in which pixels are arranged at pixel positions formed by intersections of a plurality of data signal lines and a plurality of scanning signal lines;
Scanning signal line selection means for sequentially supplying scanning signals to the scanning signal lines;
In an image display device having
An image signal having pixel data corresponding to each of the pixel positions in time series is sampled, and N phase expansion signals converted to a time length longer than the sampling period are applied to N phase expansion signal lines. Phase expansion means for outputting in parallel;
Each of the N phase expansion signals is connected to each of the data signal lines, and one of the N phase expansion signals is input. The pixel data in the phase expansion signal is sampled during a sampling period, and the data signal line is A plurality of sampling switching means supplied as:
A data signal switching means for supplying a sampling period signal corresponding to the sampling period shorter than a period corresponding to the time length of the phase expansion signal to the sampling switching means;
A plurality of precharge switching means for precharging each data signal line during a precharge period prior to the sampling period for supplying the data signal to each data signal line;
Have
The plurality of sampling switching means and the plurality of precharge switching means are connected in parallel to one end side of each of the data signal lines,
The phase expansion means outputs the N phase expansion signals in parallel to the N phase expansion signal lines so as to match the switching positions of the pixel data of each of the N phase expansion signals,
The data signal line driving means includes:
It has a shift register that sequentially shifts and sends out the input signal by one cycle of the reference clock,
A common sampling period signal is generated so as to match the start timing of the sampling period based on the output signal of the shift register, and supplied to the plurality of sampling switching means,
A common precharge period signal is generated so as to match the start timing of the precharge period based on the output signal of the shift register, and supplied to the plurality of precharge switches,
m (1 ≦ m ≦ total number of pixels on one scanning signal line / total number of phase development signal lines) N sampling switching units connected to the data signal line to be driven simultaneously are connected to one horizontal line. A (3m-2) th shift register output in a scanning period is supplied as a sampling period signal;
The (3m-2) th shift register output is supplied to other N precharge switching means connected to the (m + 1) th simultaneously driven data signal line. apparatus. In claim 1,
The image display unit is a liquid crystal panel in which liquid crystal is interposed between a pair of substrates,
The plurality of sampling switching means is composed of a plurality of thin film transistors formed on one of the substrates,
The image display device, wherein the sampling period signal from the data signal line driving means is supplied to the gate of each thin film transistor. In claim 1 ,
The image display unit is a liquid crystal panel in which a liquid crystal is interposed between a pair of substrates, and a voltage applied to one end of the pixel via the data signal line and a voltage applied to the other end of the pixel Is applied to the liquid crystal at the pixel position, and the polarity of the electric field applied to the liquid crystal is reversed and driven.
A first polarity image signal for driving the pixel with a first polarity with respect to a polarity inversion reference potential, and a first polarity having a polarity opposite to the first polarity, from an input image signal before the phase development means A second polarity image signal for driving the pixel with a polarity of 2, and outputting either one of the first or second polarity image signal to the phase expansion means based on a polarity inversion timing signal Means are further provided,
The image display apparatus, wherein the phase expansion means phase-expands the first and second polarity image signals and outputs first and second polarity phase expansion signals. In claim 1 ,
The image display unit is a liquid crystal panel in which a liquid crystal is interposed between a pair of substrates, and a voltage applied to one end of the pixel via the data signal line and a voltage applied to the other end of the pixel Is applied to the liquid crystal at the pixel position, and the polarity of the electric field applied to the liquid crystal is reversed and driven.
A first polarity phase development signal for driving the pixel with a first polarity with respect to a polarity inversion reference potential from one of the N phase development signals and a first polarity after the phase development means And a second polarity phase development signal for driving the pixel with a second polarity opposite to that of the first polarity, and outputting one of the first and second polarity phase development signals based on a polarity inversion timing signal An image display device, further comprising polarity reversing means for performing the above operation. In any one of Claims 1 thru | or 4 ,
A first precharge potential that precharges the data signal line with the first polarity, and a second precharge potential that precharges the data signal line with the second polarity. An image display device, further comprising precharge potential supply means for switching to each of the plurality of precharge switching means for selection. An image display unit in which pixels are arranged at pixel positions formed by intersections of a plurality of data signal lines and a plurality of scanning signal lines;
Scanning signal line selection means for sequentially supplying scanning signals to the scanning signal lines;
In the image display device that is driven by inverting the polarity of the voltage applied to the pixel at a predetermined period with respect to the polarity inversion reference potential,
An image signal having pixel data corresponding to each of the pixel positions in time series is sampled, and N phase expansion signals converted to a time length longer than the sampling period are applied to N phase expansion signal lines. Phase expansion means for outputting in parallel;
Each of the N phase expansion signals is connected to each of the data signal lines, and one of the N phase expansion signals is input. The pixel data in the phase expansion signal is sampled during a sampling period, and the data signal line is A plurality of sampling switching means supplied as:
A data signal line driving means for supplying a sampling period signal corresponding to the sampling period shorter than a period corresponding to the time length of the phase development signal to the sampling switching means;
A plurality of precharge switching means for precharging each data signal line during a precharge period prior to the sampling period for supplying the data signal to each data signal line;
Have
The plurality of sampling switching means and the plurality of precharge switching means are connected in parallel to one end side of each of the data signal lines,
A first precharge line connected to an odd number of the plurality of precharge switching means;
A second precharge line connected to an even number of the plurality of precharge switching means;
A first precharge potential that precharges the data signal line with a first polarity with respect to a polarity inversion reference potential, and a first precharge potential that precharges the data signal line with a second polarity with respect to the polarity inversion reference potential. A precharge potential supply means for switching the precharge potential of 2 each time the scanning signal line is selected and supplying the precharge potential to the first and second precharge lines;
An image display device further comprising: An electronic apparatus comprising the image display device according to claim 1 .

Images