CN100412934C - Active matrix display device and driving method thereof - Google Patents

Abstract

An active matrix display device uses amorphous silicon drive transistors to drive current through the LED display elements. The first and second capacitors are connected in series between the gate and the source of the driving transistor, and data input to the pixel is provided to a node between the first and second capacitors. The second capacitor is charged to the pixel data voltage, and the threshold voltage of the driving transistor is stored on the first capacitor. This pixel arrangement allows the threshold voltage to be stored on the first capacitor, and this storage can be done each time the pixel is addressed, thereby compensating for age-related changes in the threshold voltage.

Description

Active matrix display device and driving method thereof

The present invention relates to active matrix display devices, in particular (but not exclusively) to active matrix electroluminescent display devices having a thin film switching transistor associated with each pixel.

Matrix display devices employing electroluminescent, light-emitting display elements are well known. The display elements may comprise, for example, organic thin film electroluminescent elements using polymer materials, or light emitting diodes (LEDs) using conventional III-V semiconductor compounds. Recent developments in organic electroluminescent materials, especially polymeric materials, have shown that they can actually be used in video display devices. These materials typically include one or more layers of semiconducting conjugated polymers sandwiched between a pair of electrodes, one of which is transparent and the other has a material suitable for injecting holes or electrons into the polymer layer.

Polymer materials can be fabricated using CVD processing or simply by spin-coating techniques using solutions of soluble conjugated polymers. Inkjet printing can also be used. Organic electroluminescent materials exhibit diode-like I-V properties, thereby providing both display and switching functions, and can be used in passive type displays. Alternatively, these materials may be used in active matrix display devices in which each pixel includes a display element and a switching means for controlling the current flow through the display element.

Such display devices have current driven display elements such that conventional analog drive schemes involve supplying controllable currents to the display elements. It is known to provide a current source transistor as part of the pixel structure, the gate voltage supplied to the current source transistor determining the current flowing through the display element. After the addressing phase, the storage capacitor maintains this gate voltage.

Figure 1 shows a known pixel circuit for an active matrix addressed electroluminescent display device. The display device comprises a panel having a matrix array of rows and columns of uniformly spaced pixels shown in block 1, wherein the pixels comprise intersections between intersecting sets of row (select) address conductors 4 and sets of column (data) address conductors 6 The electroluminescent display element 2 and the associated switching device. For simplicity, only a few pixels are shown in the figure. In fact, there can be hundreds of pixel rows and columns. The pixels 1 are addressed via the row and column address conductor sets by a peripheral driver circuit comprising a row scan driver circuit 8 and a column data driver circuit 9 connected to the ends of the respective conductor sets.

The electroluminescent display element 2 comprises an organic light emitting diode, denoted here as a diode element (LED), and comprising a pair of electrodes between which one or more active layers of organic electroluminescent material are sandwiched. The display elements of the array are mounted on one side of an insulating carrier together with associated active matrix circuitry. The cathode or anode of the display element is formed of a transparent conductive material. The carrier is a transparent material such as glass, and the electrode closest to the substrate of the display element 2 can be made of a transparent conductive material such as ITO, so that the light generated by the electroluminescent layer is transmitted through these electrodes and the carrier, so that it can be obtained by A viewer at the other side of the carrier sees it. Typically, the thickness of the organic electroluminescent material layer is between 100 nm and 200 nm. Typical examples of suitable organic electroluminescent materials that can be used for element 2 are known and described in EP-A-0717446. Conjugated polymer materials as described in WO96/36959 may also be used.

Figure 2 shows in a simplified schematic form a known pixel and driver circuit arrangement for providing voltage programming operations. Each pixel 1 comprises an EL display element 2 and associated driver circuitry. The driver circuit has an address transistor 16 which is switched on by a row address pulse on the row conductor 4 . When address transistor 16 is turned on, the voltage on column conductor 6 can be passed to the rest of the pixel. In particular, address transistor 16 supplies the column conductor voltage to current source 20 , which includes drive transistor 22 and storage capacitor 24 . The column voltage is supplied to the gate of the drive transistor 22, and the gate is held at this voltage by the storage capacitor 24 even after the end of the row address pulse. Drive transistor 22 draws current from power supply line 26 .

To date, most active-matrix circuits for LED displays use low-temperature polysilicon (LTPS) TFTs. The threshold voltage of these devices is stable in time, but varies in a random fashion from one pixel to another. This produces unacceptable static noise in the image. In order to overcome this problem, various circuits have been proposed. In one example, each time a pixel is addressed, the pixel circuitry measures the threshold voltage of the TFT supplying the current to overcome this pixel-to-pixel variation. Such circuits target LTPS TFTs and use p-type devices. Such circuits cannot be fabricated with hydrogenated amorphous silicon (a-Si:H) devices, which are currently limited to n-type devices.

However, a-Si:H has been considered. The change in threshold voltage in amorphous silicon transistors is smaller, at least over a short range across the substrate, although threshold voltage is very sensitive to voltage stress. Applying a high voltage above the threshold required to drive the transistor results in a large change in threshold voltage, which depends on the information content of the displayed image. Therefore, there is a large difference between the threshold voltages of always-on and non-always-on amorphous silicon transistors. This differential aging is a serious problem in LED displays driven by amorphous silicon transistors.

Typically, the proposed circuits using a-Si:HTFTs use current addressing instead of voltage addressing. Of course, it is also recognized that current programmed pixels can reduce or eliminate the effects of transistor variations on the substrate. For example, a current programmed pixel may use a current mirror to sample the gate-source voltage on a sampling transistor through which the desired pixel drive current is driven. The drive transistor is addressed using the sampled gate-source voltage. This alleviates in part the problem of non-uniformity of the device, since the sampling transistor and the driving transistor are adjacent to each other on the substrate and can be more precisely matched to each other. Another current-sensing circuit uses the same transistors for sampling and driving, eliminating the need for transistor matching, but requiring additional transistors and address lines.

The high current required to drive conventional LED devices means that amorphous silicon is difficult to use in active-matrix organic LED displays. Recently, OLEDs and solution-processed OLEDs have shown extremely high efficiencies by using phosphorescence. With reference to the article "Electrophosphorescent Organic Light Emitting Devices (Electroluminescent Organic Light Emitting Devices)" by S.R.Forrest et al. (52.1 SID 02 Digest, May 2002, p. 1357), and the article "Highly Efficient Solution Processible Dendrimer LEDs" by J.P.J.Markham solution can handle dendrimer LEDs)" (L-8 SID 02 Digest, May 2002, p. 1032). Thus, the currents required by these devices are within the reach of a-Si TFTs. However, other problems are beginning to manifest themselves.

The extremely small current required for phosphorescent organic LEDs results in column charging times that are too long for large displays. Another problem is the stability (rather than the absolute value) of the threshold voltage of the TFT. Under constant bias, the threshold voltage of the TFT increases so that a simple constant current circuit will stop operating after a short time.

Difficulties therefore remain in implementing an addressing scheme suitable for use with pixels having amorphous silicon TFTs, even for phosphorescent LED displays.

According to the present invention, there is provided an active matrix display device comprising an array of display pixels, each pixel comprising:

Current-driven light-emitting display elements;

an amorphous silicon drive transistor for driving current through the display element;

The first and second capacitors are connected in series between the gate and the source or drain of the drive transistor, and the data input to the pixel is supplied to the junction between the first and second capacitors, thereby charging the second capacitor to a voltage derived from the pixel data voltage, and a voltage derived from the drive transistor threshold voltage is stored on the first capacitor.

The pixel arrangement can store the threshold voltage onto the first capacitor, and can do so each time the pixel is addressed, thereby compensating for age-related threshold voltage changes. Therefore, an amorphous silicon circuit is provided that measures the threshold voltage of the TFT supplying the current every frame time to compensate for aging effects.

In particular, the pixel layout of the present invention can overcome the increased threshold voltage of amorphous silicon TFTs while enabling voltage programming of the pixels in a sufficiently short time for large high resolution AMOLED displays.

Each pixel may also include an input first transistor connected between the input data line and a junction between the first and second capacitors. The first transistor times the application of the data voltage to the pixel for storing the data voltage on the second capacitor.

Each pixel may also include a second transistor connected between the gate and drain of the drive transistor. This is used to control the supply of current from the drain (which may be connected to the supply line) to the first transistor. Thus, by turning on the second transistor, the first capacitor can be charged to the gate-source voltage. The second transistor may be controlled by a first gate control line shared between one pixel row.

In one example, the first and second capacitors are connected in series between the gate and the source of the driving transistor. Then, the third transistor is connected to both ends of the second capacitor, and is controlled by a third gate control line shared among one pixel row. The second and third gate control lines comprise a single shared control line.

Alternatively, the first and second capacitors may be connected in series between the gate and drain of the driving transistor. Then, a third transistor is connected between the input terminal and the source of the driving transistor. The third transistor may be controlled by a third gate control line shared between one pixel row. Likewise, the second and third gate control lines may comprise a single shared control line.

The third transistor is used in each case to short-circuit the second capacitor so that only the first capacitor can store the gate-source voltage of the drive transistor.

Each pixel may further include a fourth transistor connected between the source of the driving transistor and the ground potential line. This is used to act as a current drain for the drive transistors, in particular not to illuminate the display elements during the pixel programming sequence. The fourth transistor may also be controlled by a fourth gate control line shared between one pixel row. The ground potential line may be shared between one pixel row, and the ground potential line may include a fourth gate control line for a fourth transistor of an adjacent pixel row.

In another arrangement, the capacitor is arranged to be connected between the gate and the source of the drive transistor, and the source of the drive transistor is connected to ground. The drain of the driving transistor is connected to one end of the display element, and the other end of the display element is connected to the power line. This provides a circuit of reduced complexity, although the circuit elements are on the anode side of the display element.

Each pixel may also include a second transistor connected between the gate and drain of the drive transistor, a short transistor connected across the second capacitor, a charging transistor connected between the power supply line and the drain of the drive transistor, and a A discharge transistor between the gate and drain of the drive transistor.

In some circuits of the invention, the end of the display element opposite the drive transistor may be connected to a switchable voltage line. It may be a common cathode line shared between a row of pixels. The ability to vary the voltage on this common cathode line requires "structuring" it, specifically into separate wires for each separate row.

To eliminate the need to provide structured electrodes, and to allow all pixels of the array to share a common display element electrode opposite the drive transistor, each pixel may also comprise a second drive transistor. The second driving transistor may be provided between the power supply line and the first driving transistor, or between the first driving transistor and the display element. In each case, the second drive transistor provides a way to prevent illuminating the display element during the addressing phase without requiring changes to the voltage on the power supply line or on the common display element terminal.

The display element may comprise an electroluminescent (EL) display element, such as an electrophosphorescent organic electroluminescent display element.

The invention also provides a method for driving an active matrix display device comprising an array of current driven light emitting display pixels, each pixel comprising a display element and an amorphous silicon drive transistor for driving current through the display element , the method consists of for each pixel:

driving current to ground through the driving transistor, and charging the first capacitor to the generated gate-source voltage;

Discharging the first capacitor until the drive transistor is turned off, so that the first capacitor stores a threshold voltage;

charging a second capacitor connected in series with the first capacitor between the gate and the source or drain of the drive transistor to the data input voltage; and

A drive transistor is used to drive current through the display element using a gate voltage derived from the voltage across the first and second capacitors.

The method measures the drive transistor threshold voltage in each addressing sequence. This method is used in amorphous silicon TFT pixel circuits, especially n-type drive TFTs, so short pixel programming must be achieved in order to be able to address large displays. In this approach, threshold voltage measurements can be made in a pipelined addressing sequence (that is, addressing sequences for adjacent rows overlap in time) or by measuring all threshold voltage to achieve this.

In a pipelined addressing sequence, the step of charging the second capacitor is performed by switching on an address transistor connected between the data line and the pixel input. The address transistors for each pixel in a row are turned on simultaneously by a common row address control line, and the address transistors for a row of pixels are turned on substantially immediately after the address transistors for adjacent rows are turned off.

In the blanking period sequence, at the initial threshold measurement period of the display frame period, the first capacitor of each pixel is charged to store the corresponding threshold voltage of the pixel drive transistor, and the pixel drive of the frame period after the threshold measurement period cycle.

The invention will be described below by way of example with reference to the accompanying drawings, in which:

Figure 1 shows a known EL display device;

2 is a schematic diagram of a known pixel circuit for current addressing of an EL display pixel using an input drive voltage;

3 is a schematic diagram of a first example of a pixel layout for a display device of the present invention;

Fig. 4 is a timing diagram of the first operation method of the pixel layout in Fig. 3;

Fig. 5 is a timing diagram of the second operation method of the pixel layout in Fig. 3;

Fig. 6 is a timing diagram of the third operation method of the pixel layout in Fig. 3;

7 shows a schematic diagram of a second example of a pixel layout for a display device of the present invention;

Figure 8 shows an example of component values for the circuit of Figure 3 or 7;

9 shows a schematic diagram of a third example of a pixel layout with threshold voltage compensation of the present invention;

FIG. 10 is an operation timing diagram of the pixel layout of FIG. 9;

11 shows a schematic diagram of a fourth example of a pixel layout with threshold voltage compensation of the present invention;

FIG. 12 is an operation timing diagram of the pixel layout of FIG. 11;

13 shows a schematic diagram of a fifth example of a pixel layout with threshold voltage compensation of the present invention;

FIG. 14 is a timing diagram of the first operation method of the pixel layout in FIG. 13;

FIG. 15 is a timing diagram of the second operation method of the pixel layout in FIG. 13;

Figure 16 is a modification of the timing diagram of Figure 15;

17 shows a schematic diagram of a sixth example of a pixel layout with threshold voltage compensation of the present invention;

FIG. 18 is a timing diagram of the first operation method of the pixel layout in FIG. 17;

FIG. 19 is a timing diagram of the second operation method of the pixel layout in FIG. 17;

FIG. 20 is a modification of the timing diagram of FIG. 18 .

The same reference numerals are used for the same components in different drawings, and descriptions of these components will not be repeated.

Figure 3 shows a first pixel arrangement according to the invention. In preferred embodiments, each pixel has an electroluminescent (EL) display element 2 and an amorphous silicon drive transistor T _D connected in series between a power supply line 26 and a cathode line 28 . The driving transistor T _D is used to drive current to flow through the display element 2 .

The first capacitor _C1 and the second capacitor _C2 are connected in series between the gate and the source of the driving transistor _TD . Data input to the pixel is provided to the junction 30 between the first and second capacitors, and charges the second capacitor _C2 to the pixel data voltage, as described below. The first capacitor _C1 is used to store the driving transistor threshold voltage thereon.

The input transistor _A1 is connected between the input data line 32 and the junction 30 between the first and second capacitors. The first transistor clocks the application of the data voltage to the pixel for storing the data voltage on the second capacitor _C2 .

The second transistor _A2 is connected between the gate and the drain of the driving transistor _TD . This is used to control the supply of current from the power supply line 26 to the first capacitor C ₁ . Thus, by turning on the second transistor _A2 , the first capacitor _C1 can be charged to the gate-source voltage of the driving transistor _TD .

The third transistor _A3 is connected to both ends of the second capacitor _C2 . This is to short-circuit the second capacitor so that only the first capacitor can store the gate-source voltage of the drive transistor _TD .

The fourth transistor _A4 is connected between the source of the driving transistor _TD and ground. This is used to act as a current drain for the drive transistors, in particular not to illuminate the display elements during the pixel programming sequence.

Capacitor 24 may comprise an additional storage capacitor (as in the circuit of FIG. 2), or may comprise the self-capacitance of the display element.

Transistors _A1 to _A4 are controlled by respective row conductors connected to the gates of transistors _A1 to _A4 . As will be described further below, certain row conductors may be shared. Addressing of the pixel array thus involves sequentially addressing rows of pixels, and data lines 32 comprise column conductors, thereby addressing rows sequentially while simultaneously addressing an entire row of pixels in a conventional manner.

The circuit of Figure 3 can operate in a number of different ways. The basic operation will be described first, and then the method of extending the basic operation to provide pipelined addressing will be explained. Pipelined addressing means that there is some timing overlap between the control signals of adjacent rows.

Only the drive transistor _TD is used in constant current mode. All other TFTs A ₁ to A ₄ in the circuit are used as switches operating at short duty cycles. Consequently, threshold voltage shifts in these devices are small and do not affect circuit performance. A timing chart is shown in FIG. 4 . Curves _A1 to _A4 represent the gate voltages applied to the respective transistors. Curve "28" represents the voltage applied to cathode line 28, and the blank portion of curve "Data" represents the timing of the data signal on data line 32. The shaded area represents the time when there is no data on the data line 32 . As will be apparent from the description below, data for other pixel rows may be applied during this time period so that data is applied to data line 32 almost continuously, thereby exhibiting a pipelined operation.

The circuit operates to store the threshold voltage of drive transistor _TD on _C1 and then store the data voltage on _C2 such that the gate-source voltage of _TD is the data voltage plus the threshold voltage.

The circuit operation includes the following steps.

The cathodes (line 28) for the pixels in one row of the display are at a voltage sufficient to keep the LEDs reverse biased throughout the addressing sequence. In curve "28" of FIG. 4 it is a positive pulse.

Address lines _A2 and _A3 go high to turn on the associated TFT. This shorts capacitor _C2 and connects one side of capacitor _C1 to the power line and the other side to the LED anode.

Then, the address line _A4 becomes high level, turning on its TFT. This puts the anode of the LED at ground level and generates a large gate-source voltage across the driving TFT _TD . _C1 is thus charged, but _C2 is not charged as it remains short circuited.

Next, address line _A4 goes low, turns off the corresponding TFT, and drives TFT _TD to discharge capacitor _C1 until it reaches its threshold voltage. Thus, the threshold voltage of the drive transistor _TD is stored on _C1 . Likewise, there is no voltage on the second capacitor _C2 .

_A2 is made low to isolate the measured threshold voltage on the first capacitor _C1 , and _A3 is made low so that the second capacitor _C2 is no longer shorted.

Then, bring _A4 high again to connect the anode to ground. Then the data voltage is applied to the second capacitor C ₂ , and at the same time, the input transistor is turned on by the high level pulse on A ₁ .

Finally, _A4 goes low, subsequently reducing the cathode to ground. Then, the LED anode floats to its operating point.

Or the cathode can be brought down to ground after taking _A2 and _A3 low and before bringing _A4 high.

The addressing sequence can be pipelined so that more than one row of pixels can be programmed at any one time. Thus, the addressing signals on lines _A2 through _A4 and the row-wise cathodic line 28 can overlap with the same signals for different rows. Thus, the length of the addressing sequence does not imply a long pixel programming time, and the effective row time is limited only by the time required to charge the second capacitor _C2 when the address line _A1 is high. This time period is the same as that used for a standard active matrix addressing sequence. The other part of addressing means that the total frame time will be extended only slightly by the set-up time required for the first few lines of the display. However, this setup is easily done during the frame blanking period, so the time required for the threshold voltage measurement is not an issue.

Pipelined addressing is shown in the timing diagram of FIG. 5 . Therein the control signals for transistors _A2 to _A4 have been combined into a single curve, but the operation is the same as described with reference to FIG. 4 . The "data" curve in FIG. 5 shows that data line 32 is used nearly continuously to provide data to successive rows.

In the methods of FIGS. 4 and 5 , the threshold measurement operation is combined with the display operation, so that each row of pixels is sequentially thresholded and displayed.

Figure 6 shows a timing diagram of a method in which threshold voltages are measured at the beginning of a frame for all pixels in a display. The curve in FIG. 6 corresponds to the curve in FIG. 4 . The advantage of this approach is that it does not require structured cathodes (i.e. different cathode lines 28 for different rows, as is required to implement the approach of Figures 4 and 5), but the disadvantage is that leakage currents can cause some image non-uniformity . The circuit diagram of this method is still shown in FIG. 3 .

As shown in Figure 6, the signals _A2 , _A3 , _A4 and the signal for cathode line 28 in Figure 6 are provided to all pixels in the display during the blanking period to perform threshold voltage measurements. During the blanking period, signal _A4 is supplied to each pixel simultaneously, so that all signals _A2 to _A4 are supplied to all rows simultaneously. During this period, no data can be provided to the pixel, corresponding to the shaded portion of the data curve at the bottom of FIG. 6 .

In the subsequent addressing period, data is sequentially provided to each row, eg, signal A ₁ . The pulse train on _A1 in FIG. 6 represents pulses for successive rows, and each pulse is timed by applying data to data line 32 .

The circuit in Figure 3 has a large number of rows for control transistors and structured cathode lines (if required). Figure 7 shows a circuit modification which reduces the number of rows required. The timing diagrams show that signals _A2 and _A3 are very similar. Simulations have shown that _A2 and _A3 can actually be made identical so that only one address line is required. The number of rows can be further reduced by connecting the ground line associated with transistor _A4 in FIG. 3 to address line _A4 in the previous row. The circuit in Fig. 7 shows address lines for row n and row n-1.

FIG. 8 shows component values for the circuit of FIG. 3 used in an example simulation. The length (L) and width (W) dimensions of the transistor are given in μm. The addressing time is 16μs (that is, the time when A ₁ is turned on). With a voltage 5V above the threshold on the driver TFT, the circuit delivers up to 1.5µA to the LED. The TFT mobility is 0.41 cm ² /Vs. Using an LED with an efficiency of 10 Cd/A in a pixel size of 400 μm x 133 μm (Super-yellow Polymer Efficiency currently available) would give 280 Cd/m ² assuming a full aperture in a top emitting structure .

This simulation shows that changing the threshold voltage (for driving the transistor) from 4V up to 10V produces only a 10% change in output current. The lifetime of such a display can be calculated to be 60,000 hours at room temperature and 8000 hours at 40°C.

FIG. 9 shows a modification of the circuit of FIG. 3. FIG. Although not described in detail in this application, the circuit of FIG. 9 has particular utility in pixel circuits in which each pixel has two or more drive transistors operating alternately. The circuit of Figure 9 can be replicated in a single pixel in a simple manner by reducing the number of components. This can be achieved by making certain TFTs dual-functional. When multiple drive transistors are provided, independent control of the sources or gates of the multiple drive TFTs is required, and all TFTs used to control the two drive TFTs must operate on a normally off basis (i.e., have a low duty cycle). ratio), unless these TFTs themselves have some kind of _VT drift correction.

The TFT connected to the address line _A4 in FIG. 3 is large because it needs to pass the current supplied by the driving TFT during the address period. Thus, this TFT is an ideal candidate for a dual purpose TFT, ie used as both a driving TFT and an addressing TFT. Unfortunately, the circuit shown in Figure 3 cannot achieve this.

In FIG. 9, the same components as those in the circuit of FIG. 3 are denoted by the same reference numerals, and the description thereof will not be repeated.

In this circuit, first and second capacitors _C1 and _C2 are connected in series between the gate and drain of the driving transistor _TD . Also, the pixel input is provided to the junction between the capacitors. The first capacitor _C1 for storing the threshold voltage is connected between the gate of the driving transistor and the input terminal. The second capacitor _C2 for storing the data input voltage is directly connected between the pixel input terminal and the power line (to which the drain of the transistor is connected). The transistor connected to the control line _A3 is also used to provide a charging path _for the first capacitor _C1 , which bypasses the second capacitor _C2 so that only capacitor _C1 is used to store the threshold gate-source voltage .

Circuit operation is represented in Figure 10 and has the following steps:

During the entire addressing sequence, the cathodes of the pixels in one row of the display are brought to a voltage sufficient to keep the LEDs reverse biased.

The address lines _A2 and _A3 go high to turn on the associated TFT, which in doing so connects the parallel combination of _C1 and _C2 to the power supply line.

The address line _A4 then goes high to turn on its TFT, which in doing so puts the LED's anode at ground and creates a large gate-source voltage across the drive TFT _TD .

Next, the address line _A4 goes low to turn off the TFT, and drives the TFT _TD to discharge the parallel capacitance _C1 + _C2 until it reaches the threshold voltage.

_A2 and _A3 then go low to isolate the measured threshold voltage.

Afterwards, A ₁ is turned on, and stores the data voltage on the capacitor C ₁ .

Finally, _A4 goes low, which subsequently drops the cathode to ground.

Also as described above, this circuit can be used to perform pipelined addressing or threshold measurements during blanking periods.

Thus the voltage V _data -V _T is stored on the gate-drain of the driving TFT. therefore:

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Thus, the threshold voltage dependence is eliminated. Note that the current depends on the LED anode voltage at this point.

The circuit described above has a relatively high number of components (due to the separate gates and sources driving the TFTs). Circuits with only one independent node (i.e. source or gate) allow for a lower parts count. The circuit described below uses the circuit on the cathode side of the LED and uses an independent source voltage to implement a threshold voltage measurement circuit with a recovery function. The threshold voltage measurement circuit is described with reference to FIG. 11 , and in FIG. 12 is a timing chart.

In the circuit of Fig. 11, each pixel has a first and a second capacitance C1 _{, C2} connected in series between the gate of the drive transistor _TD and ground. The sources of the drive transistors are connected to ground, but when combining the two circuits, the source of each drive transistor is connected to the corresponding control line. Data input to the pixel is also provided to the junction between the first and second capacitors.

The short-circuit transistor is connected across the second capacitor _C2 and is controlled by the line _A2 . As with the previous circuit, this stores the gate-source voltage on capacitor _C1 , thereby bypassing capacitor _C2 . The charging transistor associated with control line _A4 is connected between power supply line 50 and the drain of drive transistor _TD . It provides a charging path for capacitor _C1 together with a discharge transistor associated with control line _A3 and connected between the gate and drain of the drive transistor.

The circuit operates as follows: hold _A2 and _A3 high, then hold _A4 high briefly to pull the cathode high and charge capacitor _C1 to a high gate-source voltage. The power line is ground level to reverse bias the LED. _TD is then discharged to its threshold voltage (the discharge transistor associated with line _A3 is turned on) and stored onto _C1 . Next, make _A2 and _A3 low, make _A1 high, and transfer the data onto _C2 . Then bring the power line high again to light up the LED.

Likewise, the addressing sequence can be pipelined, or the threshold voltage can be measured during the vertical blanking period.

In the common cathode circuits of Figures 3, 7 and 9 above, structured cathodes are required to be able to switch the cathodes of the individual rows to different voltages during the addressing period.

Figure 13 shows a first modification of the circuit of Figure 3 in which no structured cathode is required. Between the power supply line 26 and the first drive transistor _TD , a second drive transistor _Ts is provided in series with the first drive transistor _TD .

In this circuit, a switchable voltage is provided on the supply line 26 (instead of the cathode line 28), which is used to switch the second drive transistor T _S off. Operation timings are shown in FIG. 14 .

As shown, the operation of this circuit is similar to that of the circuit of FIG. 4 . Instead of switching off the cathode 28 of the display element, the power line 26 is brought low during the addressing sequence. This turns off the second drive transistor T _S which _is diode-connected by connecting its gate and drain together.

When transistors _A2 - _A4 are conducting, the supply line 26 is high for the initial part of the cycle, because the supply line is used to charge capacitor _C1 during this period, and the second drive transistor _Ts must be conducting during this period. pass. This initial period is long enough for the capacitor _C1 to be charged.

When the power line is switched to low level, the second address transistor T _S is turned off. As a result, there is no need to switch the fourth transistor _A4 off.

Also, addressing may be pipelined as shown in FIG. 15 in a manner similar to that described with reference to FIG. 5 .

The addressing scheme of Figure 15 does not allow any duty cycling of the light output. This is a technique whereby the drive transistor is not illuminated all the time. This reduces threshold voltage drift and also improves motion portrayal. In order to provide the operating cycle of the drive transistor, the operating timing of FIG. 15 is modified as represented in FIG. 16 .

As described with reference to FIG. 14 , after the capacitor _C1 is charged, the voltage on the power supply line 26 is made low, thereby cutting off the current to the display element 2 . The first drive transistor _TD will still have a gate-source voltage above threshold, and this voltage is removed through transistors _A2 and _A3 , so that the source-drain current of drive transistor _TD is removed by capacitor _C1 charge until the threshold voltage is reached.

In the scheme of FIG. 16, the power line is kept high only for a part (eg, half) of the frame period. As shown in FIG. 16, at some later point in the frame period, the power line 26 is switched low. To ensure that the drive transistor _TD is switched off for the remainder of the frame period, after the power line is switched low, pulses are provided on the control line for transistors _A2 and _A3 as shown .

In the example of FIG. 13, the fourth transistor _A4 is connected to ground. However, the transistor could be connected to the power line 26 of the previous row (instead of being connected to ground as in Figure 13). The timing of Figure 16 achieves this because the power supply line is at ground level when measuring the threshold voltages of the drive TFTs of the previous row. During the time that the fourth transistor is on, this period (labeled 27 in Figure 16) can be used to act as ground for the next row of pixels. Thus, the address cycle of _A4 is in that cycle when the power line for the previous row is low.

The circuit of FIG. 13 adds a second drive transistor between the power supply line 26 and the first drive transistor _TD . This second drive transistor will pass the same current as the first drive transistor _TD , so threshold compensation is not required. The gate-source voltage will float to the level required by the second drive transistor TD to provide the current required by the first drive transistor _TD .

Another option is to add a second drive transistor between the first drive transistor T _D and the display element, again in order not to provide a structured cathode. Furthermore, no specific compensation for the second drive transistor is likewise required.

An example of this circuit is shown in FIG. 17 . The gate of the second driving transistor _TS is grounded through the fourth transistor _A4 , and the fifth transistor _A5 is connected between the gate and the drain of the fifth transistor. In other respects the circuit is the same as in Figure 3 and operates in the same manner.

As will be apparent from the description below, the circuit does not require switching voltages to be provided at the common cathode terminals of the display elements or on the supply lines.

As shown in Figure 18, at the beginning of the addressing phase, transistors _A2 - _A5 are all switched on. For the circuit of Figure 3, doing this charges capacitor _C1 to a level that turns on drive transistor _TD and shorts capacitor _C2 . The source of the driving transistor T _D is grounded through the fourth and fifth transistors A ₄ , A ₅ . During this time, the second drive transistor _TS is off because the gate is coupled to ground through the fourth transistor _A4 .

The gate of the fifth transistor _A5 is then brought low, thereby switching it off. In the same manner as the circuit of Figure 3, the drive current through the drive transistor (since the source-gate voltage does not change) discharges capacitor _C1 until the threshold voltage is stored. Thus, the voltage on the source of the drive transistor is the supply line voltage below the threshold voltage, which drops across _C1 .

Transistors _A2 and _A3 are then switched off to isolate the respective capacitors. The fifth address transistor is turned on again before the address pulse is applied on _A1 . Doing so pulls the source of drive transistor _TD (and thus one end of data storage capacitor _C2 ) to ground through the fourth and fifth transistors so that a data voltage can be stored on _C2 during the addressing phase.

Transistor _A4 is turned off at the end of the address pulse to allow the second drive transistor _TS to turn on (because its gate is no longer held at ground level) and drive the display element.

Transistor _A5 is also off at the end of addressing. This keeps the duty cycle of _A5 short to prevent significant aging during operation. The gate-source and gate-drain parasitic capacitances of _A5 are able to keep the second drive transistor turned on.

In the same manner as described above, pipelined addressing can be used and is shown in FIG. 19 .

FIG. 20 shows a modification to the timing described with reference to FIG. 18 . In this case, the fifth address transistor is turned on simultaneously with the address pulse for _A1 after transistors _A2 and _A3 are switched off to isolate the capacitance. At the beginning of the address pulse, the data line 32 is at ground voltage (as shown by the bottom curve). Thus, at the beginning of the addressing phase, the junction between capacitors _C1 and _C2 is also grounded, thereby grounding both sides of capacitor _C2 . So even though _A3 is off, there is no voltage across _C2 . This helps to ensure that the threshold voltage of drive transistor _TD is retained across _C1 after the data signal is loaded onto _C2 .

There are other modifications to the specific circuit layout that can work in the same manner. Essentially, the present invention provides a circuit capable of storing a threshold voltage on one capacitor and a data signal on another capacitor connected in series between the gate and source or drain of a drive transistor. To store a threshold voltage onto the first capacitor, the circuit can drive the drive transistor with charge from the first capacitor until the drive transistor turns off, at which point the first capacitor stores a gate-source voltage from the threshold resulting voltage.

The circuit can be used in currently available LED devices. However, the electroluminescent (EL) display element may include an electrophosphorescent organic electroluminescent display element. The present invention can use a-Si:H for active matrix OLED displays.

Only n-type transistors are shown above to implement the above circuits, and these will all be amorphous silicon devices. Although amorphous silicon is preferably used to fabricate n-type devices, it is of course possible to implement alternative circuits with p-type devices.

Various other modifications will be apparent to those skilled in the art.

Claims (35)

1. An active matrix device comprising an array of display pixels, each pixel comprising: A current-driven light-emitting display element (2); An amorphous silicon drive transistor (T _D ) for driving current through the display element; The first and second capacitors (C 1 , C 2 ) are connected in series between the gate and the source or drain of the driving transistor, and _the data input to the pixel is supplied to the first and second capacitors (C ₁ , C ₂ ). ₂ ) to charge the second capacitor (C ₂ ) to a voltage derived from the pixel data voltage and to store a voltage derived from the drive transistor threshold voltage to the first capacitor (C ₁ ) superior. 2. A device as claimed in claim 1, wherein each pixel further comprises an input first transistor connected between the input data line (32) and the junction between the first and second capacitors (C ₁ , C ₂ ) (A ₁ ). 3. The device as claimed in claim 1 or 2, wherein the drain of the drive transistor (T _D ) is connected to the power supply line (26). 4. A device as claimed in claim 1 or 2, wherein each pixel further comprises a second transistor ( _A2 ) connected between the gate and drain of the drive transistor. 5. A device as claimed in claim 4, wherein the second transistor ( _A2 ) is controlled by a first gate control line shared between one row of pixels. 6. The device as claimed in claim 1 or 2, wherein the first and the second capacitance (C ₁ , C ₂ ) are connected in series between the gate and the source of the driving transistor (T _D ). 7. A device as claimed in claim 6, wherein each pixel further comprises a third transistor ( _A3 ) connected across the second capacitor ( _C2 ). 8. The device of claim 7, wherein the third transistor is controlled by a third gate control line shared between one row of pixels. 9. The apparatus of claim 8, wherein the second and third gate control lines comprise a single shared control line. 10. The device as claimed in claim 1 or 2, wherein the first and the second capacitance (C ₁ , C ₂ ) are connected in series between the gate and the drain of the driving transistor (T _D ). 11. A device as claimed in claim 10, wherein each pixel further comprises a third transistor ( _A3 ) connected between the input terminal and the source of the drive transistor ( _TD ). 12. A device as claimed in claim 11, wherein the third transistor ( _A3 ) is controlled by a third gate control line shared between one row of pixels. 13. The apparatus of claim 12, wherein the second and third gate control lines comprise a single shared control line. 14. A device as claimed in claim 1 or 2, wherein each pixel further comprises a fourth transistor ( _A4 ) connected between the source of the drive transistor and the ground potential line. 15. A device as claimed in claim 14, wherein the fourth transistor ( _A4 ) is controlled by a fourth gate control line shared between one row of pixels. 16. The device according to claim 1 or 2, wherein said first and second capacitors (C ₁ , C ₂ ) are connected between the gate and source of a drive transistor (T _D ) and drive The source of the transistor is connected to ground. 17. The device as claimed in claim 16, wherein the drain of the driving transistor (T _D ) is connected to one end of the display element (2), and the other end of the display element is connected to a power line. 18. A device as claimed in claim 16, wherein each pixel further comprises a second short-circuit transistor ( _A2 ) connected across the second capacitor ( _C2 ). 19. A device as claimed in claim 16, wherein each pixel further comprises a third transistor ( _A3 ) connected between the gate and drain of the drive transistor. 20. A device as claimed in claim 19, wherein the third transistor ( _A3 ) is controlled by a gate control line shared between one row of pixels. 21. The device as claimed in claim 16, wherein each pixel further comprises a fourth charge transistor ( _A4 ) connected between the power supply line (50) and the drain of the drive transistor. 22. A device as claimed in claim 1 or 2, wherein each pixel further comprises a second drive transistor ( _TS ). 23. The device as claimed in claim 22, wherein the second drive transistor is provided between a power supply line (26) and the first drive transistor ( _TD ). 24. The apparatus of claim 23, wherein the gate and drain of the second driving transistor are connected together. 25. A device as claimed in claim 22, wherein the second drive transistor is provided between the first drive transistor ( _TD ) and the display element (2). 26. A device as claimed in claim 25, wherein the transistor ( _A5 ) is connected between the gate and the drain of the second driving transistor ( _TS ). 27. A device as claimed in claim 25, wherein each pixel further comprises a fourth transistor ( _A4 ) connected between the gate of the second drive transistor ( _TS ) and the ground potential line. 28. The device as claimed in claim 1 or 2, wherein the drive transistor (T _D ) comprises an n-type transistor. 29. The device of claim 1 or 2, wherein the display element comprises an electroluminescent (EL) display element. 30. The device of claim 29, wherein the electroluminescent (EL) display element comprises an electrophosphorescent organic electroluminescent display element. 31. A method for driving an active matrix display device comprising an array of current-driven light-emitting display pixels, wherein each pixel comprises a display element (2) and an amorphous Silicon drive transistor (T _D ), the method for each pixel consists of: drive current through the drive transistor (T _D ) to ground and charge the first capacitor (C ₁ ) to the resulting gate-source voltage; Discharging the first capacitor (C ₁ ) until the drive transistor is turned off, so that the first capacitor stores a threshold voltage; charging a second capacitor (C ₂ ) connected in series with the first capacitor between the gate and source or drain of the drive transistor to the data input voltage; and A drive transistor (T _D ) is used to drive current through the display element using a gate voltage derived from the voltage across the first and second capacitors (C ₁ , C ₂ ). 32. A method as claimed in claim 31, wherein said step of charging the second capacitance is carried out by switching an address transistor ( _A1 ) connected between the data line and the pixel input into conduction. 33. The method of claim 32, wherein the address transistors of each pixel in a row are simultaneously switched on by a common row address control line. 34. The method of claim 33, wherein an address transistor for a row of pixels is turned on immediately after an address transistor for an adjacent row is turned off. 35. A method as claimed in claim 31 , wherein the first capacitor (C ₁ ) of each pixel is charged to store the corresponding threshold voltage of the pixel drive transistor during the initial threshold measurement period of the display frame period, the pixel of the frame period The drive period follows the threshold measurement period.

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