CN100405547C - TFT electrode structure for preventing metal layer from diffusion and its manufacturing process - Google Patents

Abstract

The invention is a TFT electrode structure and its preparation method for preventing metal layer from diffusing to the adjacent insulating layer when the metal layer of the Thin Film Transistor is made, namely reduce the risk that the metal ion pollutes the chemical vapor deposition process (CVD) in the preparation method, wherein make after connecting the metal layer of grid with a transparent electrode of picture element, can be regarded as the barrier (barrier) of the metal ion on the one hand and prevented the metal ion from diffusing to the insulating layer even the active layer at high temperature; on the other hand, the fabrication of the pixel transparent electrode is a Physical Vapor Deposition (PVD) method, the platform can be coated at a low temperature, the sensitivity to the environment is small, and the pixel transparent electrode itself is a conductive layer, so as to avoid the influence of metal ions, and improve the leakage phenomenon (leak) and poor conductivity of the TFT device manufacturing process.

Description

TFT electrode structure and manufacturing process for preventing metal layer diffusion

technical field

The invention uses a TFT electrode structure and its manufacturing process to prevent the metal layer of the thin film transistor from diffusing to the adjacent dielectric layer or insulating layer when it is manufactured.

Background technique

For the structure and manufacturing process of a thin film transistor (Thin Film Transistor, TFT), please refer to US Patent No. 6,218,22 as shown in Figure 1A, Figure 1B and Figure 1C, which describes a thin film transistor with a multi-layer metal layer and its manufacturing process ( Thin Film Transistor with a Multi-MetalStructure and a Method of Manufacturing the same), as shown in Figure 1A, wherein a glass substrate 10 is used as an insulating transparent substrate, on which a conductive layer formed by metal or alloy is deposited, and then etched The gate 11 of the TFT element is formed. This example is a multi-gate TFT structure. A dielectric layer 12 is formed on the glass substrate 10 and the gate 11 as an isolation layer for the gate 11. The dielectric layer 12 can be Silicon oxide (silicon oxide), silicon nitride (silicon nitride) or a multilayer structure formed by a combination of the two. An amorphous silicon semiconductor layer 13 is further formed on the dielectric layer 12 , and an N+ amorphous silicon layer 14 doped with N+ ions is further formed on the semiconductor layer 13 .

The continuation process is shown in Figure 1B, which shows a multi-layer metal layer 15 formed on the N+ amorphous silicon layer 14 and the dielectric layer 12, each layer has different etching resistance (: etching resistance), there are The lower layer with greater etching resistance is used to prevent the upper layer from being etched without affecting the structure of the lower layer.

As shown in FIG. 1C and FIG. 1D , a layer of photomask 61 is used on the structure shown in FIG. 1A and FIG. 1B and then according to actual needs, different etching methods are used to form the desired structure.

Finally, a passivation layer (passivation layer) 17 is deposited on the above structure by chemical deposition to isolate and protect the underlying structure. The conductive electrode (ITO) 18 is the pixel electrode (pixel electrode) used later.

The above process is only an example of the TFT process, in which a conductive layer 11 is formed above the glass substrate 10, but the method of making the dielectric layer 12 on it will cause the diffusion of the metal layer 11 due to the high temperature process, which may cause leakage current and conduction. Poor electrical conduction through the dielectric layer 12.

Please refer to FIG. 2A to FIG. 2E for the schematic diagrams of the array manufacturing process of the thin film transistors of US Patent No. 5,838,037. The triode structure TFT element of one embodiment wherein has as shown in Figure 2A, on the substrate 21 respectively form a grid 22, a pixel electrode (pixel electrode) 23 and a counter electrode (counter electrode) with protective element effect 24 and other metal material layers.

Figure 2B shows that an insulating layer 25 is formed on the above-mentioned three electrodes, and a first amorphous silicon layer 26 and a second amorphous silicon layer 27 are formed above the relative position of the gate 22, and the gate 22 is formed by etching. above to form the desired shape.

As shown in FIG. 2C, a connection hole 28 is etched on the insulating layer 25, so that the pixel electrode 23 can be electrically connected to the electrode above. The source electrode 29 and the drain electrode 30 shown in FIG. On the crystal silicon layer 26, 27, and make the pixel electrode 23 conductive to the drain electrode 30, finally as shown in FIG. 2E, a passivation layer (passivation film) 31 is used to form a protection layer for this TFT element.

In the current thin-film transistor array manufacturing process, the chemical vapor deposition process (Chemical Vapor Deposition, CVD) is a high-temperature coating technology. For metal ions that are easy to diffuse at high temperatures, it is easy to diffuse to the adjacent dielectric layer or other insulating layers. Layers will pollute the process, affecting production and device characteristics, and chemical vapor deposition machines are sensitive to the environment, and their coating quality is easily affected by the previously produced structural layers.

In the prior art, the ITO conductive glass is plated with a layer of conductive indium tin oxide (ITO) on the mother glass (mother glass) substrate, which cannot conduct electricity originally, so as to act as an electrode. As far as the above-mentioned technology of TFT element array is concerned, no matter whether the pixel transparent conductive electrode (ITO), gate and other electrodes are fabricated on the top (Top ITO) or below (Bottom ITO) of the active layer of the TFT element, it is completed The insulating layer of the dielectric layer or other structures behind the gate metal layer is processed by chemical vapor deposition, which may easily cause the metal ions of the front layer to contaminate the chemical vapor deposition machine.

The present invention uses a process to prevent metal diffusion to reduce the risk of metal ions contaminating the chemical vapor deposition process. The pixel transparent electrode is fabricated after the gate metal layer (Metal), which can be used as a barrier layer for metal ions on the one hand to avoid metal The ions diffuse to the insulating layer and even the active layer at high temperature. On the other hand, its manufacturing method is the physical vapor deposition (PVD) method, which is less sensitive to the environment, and the pixel transparent electrode itself is a conductive layer, which can avoid the influence of metal ions.

Contents of the invention

The present invention uses a process to prevent metal diffusion to reduce the risk of metal ions contaminating the chemical vapor deposition process. The pixel transparent electrode is fabricated after the gate metal layer (Metall), which can be used as a barrier layer for metal ions on the one hand to avoid metallization. The high-temperature diffusion of ions to the insulating layer and even the active layer also prevents metal ions from affecting the structure of the back layer, and its production method is the physical vapor deposition (PVD) method, which is less sensitive to the environment.

The manufacturing process described in the present invention prevents metal ions from diffusing to adjacent insulating layers by changing the order of the manufacturing process. The manufacturing steps at least include: forming a first metal layer, forming the first metal layer on a substrate, and The first metal layer is etched to form a gate of a thin film transistor (TFT); and a transparent conductive electrode is formed, and the transparent conductive electrode is directly formed on the substrate and the etched first metal layer so that the transparent conductive electrode covers cover the gate, and then etch the transparent conductive electrode to define a pattern, so that the transparent conductive electrode is divided into a pixel electrode part and a non-pixel electrode part, wherein the pixel electrode part forms a pixel electrode, and the pixel electrode is directly located on the substrate and Do not short connect to gate. Further comprising: forming a dielectric layer; forming an amorphous silicon layer; forming an N+ amorphous silicon layer by plasma-enhanced chemical vapor deposition; and forming a second metal layer, which is etched to define the source of the thin film transistor and the drain; forming a passivation layer as a protection layer for the TFT element.

The structural sequence described in the present invention includes: forming a first metal layer on a substrate, which is etched to form a gate of a thin film transistor; forming a transparent conductive electrode above the etched first metal layer, Covering the gate, and after etching, the transparent conductive electrode is divided into a pixel electrode part and a non-pixel electrode part, wherein the pixel electrode part is used as a pixel electrode; a dielectric layer is formed on the non-pixel electrode part of the transparent conductive electrode, an insulating layer for this structure; an amorphous silicon layer is formed on the dielectric layer; and a second metal layer is formed on the amorphous silicon layer, and the source and drain of the thin film transistor are formed after etching; A passivation layer is formed as a protection layer for the TFT element.

A TFT electrode structure for preventing metal layer diffusion, the structure at least includes:

A first metal layer, formed on a substrate, becomes a gate of a thin film transistor after being etched;

A transparent conductive electrode is directly formed on the substrate and the etched first metal layer, covering the grid, and after etching, the transparent conductive electrode is divided into a pixel electrode part and a non-pixel electrode part, wherein the pixel electrode part As a pixel electrode, the pixel electrode is directly located on the substrate and is not short-circuited to the gate;

A dielectric layer, formed on the non-pixel electrode portion of the transparent conductive electrode, is an insulating layer;

an amorphous silicon layer formed over the dielectric layer; and

A second metal layer is formed on the amorphous silicon layer and etched to form the source and drain of the thin film transistor.

Description of drawings

1A to 1E are schematic diagrams showing the structure of a thin film transistor with multiple metal layers and its manufacturing process in US Patent No. 6,218,221;

2A to 2E are schematic diagrams of the array manufacturing process of the US Patent No. 5,838,037 thin film transistor;

3A to 3F are schematic diagrams showing the TFT electrode structure and its manufacturing process according to the embodiment of the present invention;

FIG. 4 is a flow chart showing the process steps of the TFT electrode for preventing metal layer diffusion according to the present invention.

Symbol Description

Glass substrate 10 Conductive layer 11

Dielectric layer 12 Semiconductor layer 13

N+ amorphous silicon layer 14 multi-layer metal layer 15

Mask 61 Passivation layer 17

Transparent Conductive Electrode 18 Substrate 21

Gate 22 Pixel Electrode 23

Counter Electrode 24 Insulation Layer 25

The first amorphous silicon layer 26 The second amorphous silicon layer 27

Connection Hole 28 Source 29

Drain 30 Passivation layer 31

Glass substrate 300 first metal layer 301

Transparent Conductive Electrode 302 Dielectric Layer 303

Amorphous silicon layer 304 Amorphous silicon layer 304a

N+ amorphous silicon layer 304b second metal layer 305

N+ polysilicon layer 304b’, 304b” Second metal layer 305’, 305”

Passivation layer 306 protection circuit 308a

Three-pole structure 308b pixel electrode 302’

Detailed ways

The present invention is a TFT electrode structure and its manufacturing process for preventing metal layer diffusion, which is used to prevent the metal layer of a thin film transistor (TFT) from diffusing to the adjacent insulating layer, especially when copper is used as the material of the metal layer , to improve the leakage phenomenon and poor conduction of the TFT process.

In the manufacturing process of thin film transistors, the present invention makes the pixel transparent electrode after connecting the gate metal layer, which can be used as a barrier layer (barrier) for metal ions in the gate metal layer, and can avoid high-temperature diffusion of metal ions due to its conductive properties To the insulating layer and even the active layer. On the other hand, compared with the existing insulating layer, the transparent electrode of the pixel is produced by the chemical vapor deposition (CVD) method that requires high temperature, and by the physical vapor deposition (PVD) method, the machine can be used for low-temperature coating and environmental protection. The sensitivity is small and the influence of metal ions can be avoided.

Please refer to FIG. 3A to FIG. 3F for the schematic diagrams of the embodiment of the manufacturing process of the TFT device of the present invention.

As shown in FIG. 3A, one of the glass substrates 300 is used as an insulating transparent substrate, on which a first metal layer (metal) 301 formed by metal or alloy is deposited, which can be implemented by depositing, and then etched to form the TFT. For the gate electrode of the element and the peripheral protection circuit element, etc., a multi-pole TFT structure such as that shown in the figure can be used in practical applications, and is not limited to the structure described above.

As shown in FIG. 3B, a transparent conductive electrode (ITO) 302 is formed on the glass substrate 300 and the first metal layer 301, which can be implemented by sputtering (sputtering) process, and can be etched to become the pixel electrode of the TFT element. In the prior art, the first metal layer is fabricated behind the transparent conductive electrode. The formation of the transparent conductive electrode 302 covers the first metal layer 301 to block and avoid the metal ion diffusion phenomenon of the first metal layer 301 due to the high temperature process, especially for the diffusion phenomenon of the first metal layer 301 whose main material is copper. , and after the etching process, the transparent conductive electrode 302 can also serve as the pixel electrode 302' of the TFT element.

As shown in FIG. 3C, a dielectric layer (dielectric) 303 is formed on the transparent conductive electrode 302 as an isolation layer, which can be formed of silicon oxide, silicon nitride or a combination of the two. The multi-layer structure, and Plasma Enhanced Chemical Vapor Deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) as its embodiment, this is a high-temperature process, the first metal layer 301 is coated with the above-mentioned transparent conductive electrode 302, so It can avoid leakage or poor electrical conductivity caused by metal ion diffusion caused by this high-temperature process.

Next, please refer to the semiconductor layer formed by an amorphous silicon layer (a-Si) 304 shown in FIG. 3D. This amorphous silicon layer 304 can be a single-layer or multi-layer structure, and can be implemented by plasma chemical deposition. , and then directly deposit an N+ amorphous silicon layer on the amorphous silicon layer 304 by plasma-enhanced chemical vapor deposition or implant N+ ions above the amorphous silicon layer 304 by ion implanting to form amorphous silicon layer 304a and N+ amorphous silicon layer 304b.

The subsequent manufacturing process is shown in FIG. 3E, which shows that the second metal layer 305 is formed on the N+ amorphous silicon layer 304b, and the N+ amorphous silicon layer 304b and the second metal layer 305 are etched to form the thin film transistor according to actual requirements. The source (source) and drain (drain) poles (305', 305") of the element, and other element layers. The second metal layer (metal II) 305 described here can also be a multi-layer metal layer structure , is not limited to this.

As shown in FIG. 3F again, a passivation layer (passivation film) 306 is used to form a protection layer for the TFT element, but the passivation layer 306 is not necessary, and the polarity of the TFT element can still be measured. And the protection circuit 308a on the side of the TFT element, the triode structure 308b of the element and the pixel electrode 302' can be formed as required.

In the present invention, the pixel transparent electrode is connected to the gate metal layer (Metal I) to form a barrier layer for metal ions on the one hand, which can prevent the high-temperature diffusion of metal ions to the insulating layer or even the active layer formed by the dielectric layer. On the other hand, PVD machines can coat films at low temperatures, are less sensitive to the environment, and are conductive layers themselves, which can avoid the influence of metal ions. The invention uses a new process to reduce the risk of metal ions contaminating the CVD process.

4 is a flow chart of the TFT electrode manufacturing process for preventing metal layer diffusion according to the present invention. This embodiment is a TFT transistor with a unipolar structure, and those skilled in the art can easily extend it to a thin film transistor manufacturing process with a multipolar structure.

Step S41: Depositing the first metal layer on the transparent substrate by physical vapor deposition (PVD), electroplating (EP), spin coating (Spincoating), printing (printing) or electroless plating (ELP) methods, etc., And the pattern is defined by the etching method, and the gate of the TFT element is formed.

In addition, the surface of the substrate has glass, silicon nitride, silicon oxide, amorphous silicon, crystalline silicon, doped silicon, metal layer, metal nitride, metal nitride silicon nitride, polymer, or organic material. The metal can be a single-layer metal or a multi-layer structure, and the single metal layer can be chromium, copper, aluminum-neodymium alloy (Al-Nd), molybdenum-tungsten alloy (MOW), or aluminum. The multilayer structure can be: titanium/aluminum/titanium layer (Ti/Al/Ti), titanium/aluminum/titanium nitride layer (Ti/AI/TiN), titanium/copper/titanium layer (Ti/Cu/Ti), Chromium/Cu/Cr (Cr/Cu/Cr), W/Cu/W (W/Cu/W), MoN/Al/MoN (MoN/Al/MoN), Mo/AlNd Alloy layer (Mo/Al-Nd), molybdenum nitride/aluminum neodymium alloy layer (MoN/Al-Nd), molybdenum/aluminum neodymium alloy/molybdenum layer (Mo/Al-Nd/Mo), tantalum/copper/tantalum layer (Ta/Cu/Ta), tantalum nitride/copper/tantalum nitride layer (TaN/Cu/TaN), titanium nitride/copper/titanium nitride layer (TiN/Cu/TiN), titanium/aluminum layer (Ti /Al), molybdenum/copper/molybdenum layer (Mo/Cu/Mo), or molybdenum/aluminum/molybdenum layer (Mo/Al/Mo).

Step S42: Deposit to form a transparent conductive electrode such as: ITO (indium tin oxide), IZO (Indium zinc oxide), ZnO (zinc oxidation) or organic materials, etc. The deposition method can be physical vapor deposition (PVD), electroplating (EP) , spin coating (spin coating), printing (printing) or electroless plating (ELP) method, and etched to define the pattern to form the pixel electrode.

The following can be the usual TFT manufacturing process:

Step S43 : forming a dielectric layer as an insulating layer, which may be silicon dioxide, silicon nitride, or the like.

Step S44 : forming one or more amorphous silicon semiconductor layers on the dielectric layer to improve the characteristics of the thin film transistor.

Step S45 : directly depositing an N+ amorphous silicon layer on the amorphous silicon layer by plasma-enhanced chemical vapor deposition or implanting N+ ions by ion implantation to form an N+ amorphous silicon layer with a higher ion concentration.

Step S46: forming a second metal layer on the N+ amorphous silicon layer.

Step S47: forming the source and drain of the TFT element through an etching step.

Step S48: forming a passivation layer as a protection layer for the TFT element.

To sum up, the present invention provides a TFT electrode structure and its manufacturing process that prevent the diffusion of the metal layer, so as to prevent the metal layer of the thin film transistor (TFT) from being diffused to the adjacent insulating layer when the metal layer is fabricated, so as to improve the leakage and leakage of the TFT manufacturing process. A case of poor electrical conductivity.

Claims (21)

1. processing procedure that prevents the TFT electrode structure of metal level diffusion changes wherein that the order of processing procedure diffuses to contiguous insulating barrier to prevent metal ion, it is characterized in that this fabrication steps comprises at least:

Form a first metal layer, on a substrate, form this first metal layer, and this first metal layer is carried out the grid that etching forms a thin-film transistor: and

Form a transparency conductive electrode, on the first metal layer after the etching, directly form this transparency conductive electrode in substrate and this, make this transparency conductive electrode coat described grid, then this transparency conductive electrode is carried out etching definition figure, make this transparency conductive electrode be divided into pixel electrode part and non-pixel electrode part, wherein pixel electrode part forms a pixel electrode, and this pixel electrode is located immediately on the substrate and is not connected with gate short.

2. the processing procedure that prevents the TFT electrode structure of metal level diffusion as claimed in claim 1 is characterized in that, the processing procedure after forming this transparency conductive electrode more order includes:

On the non-pixel electrode part of transparency conductive electrode, form a dielectric layer;

On dielectric layer, form an amorphous silicon layer;

On this amorphous silicon layer, form a N+ amorphous silicon layer; And

On the N+ amorphous silicon layer, form one second metal level, and define the source electrode and the drain electrode of this thin-film transistor through etching;

Form a passivation layer and be defined as the protective layer of TFT element for this reason through etching.

3. the processing procedure that prevents the TFT electrode structure of metal level diffusion as claimed in claim 1 is characterized in that this TFT electrode structure is an one pole or multi-polar structure.

4. the processing procedure that prevents the TFT electrode structure of metal level diffusion as claimed in claim 1 is characterized in that, the method that forms this first metal layer is included on this substrate with physical vapour deposition (PVD), electroplate, revolve plating, printing or electroless plating methods makes.

5. the processing procedure that prevents the TFT electrode structure of metal level diffusion as claimed in claim 1 is characterized in that the surface of this substrate has silicon nitride, silica, metal level or organic material.

6. the processing procedure that prevents the TFT electrode structure of metal level diffusion as claimed in claim 1 is characterized in that, is with physical vaporous deposition, electroplates, revolves plating, printing or electroless plating methods and make and form this transparency conductive electrode.

7. the processing procedure that prevents the TFT electrode structure of metal level diffusion as claimed in claim 1 is characterized in that this transparency conductive electrode is ITO, IZO, ZnO or organic material.

8. the processing procedure that prevents the TFT electrode structure of metal level diffusion as claimed in claim 1 is characterized in that this first metal layer is single metal-layer structure.

9. the processing procedure that prevents the TFT electrode structure of metal level diffusion as claimed in claim 8 is characterized in that the material of this single metal-layer structure is chromium, copper, aluminium neodymium alloy, molybdenum and tungsten alloy or aluminium.

10. the processing procedure that prevents the TFT electrode structure of metal level diffusion as claimed in claim 1 is characterized in that this first metal layer is a multiple layer metal layer structure.

11. the processing procedure that prevents the TFT electrode structure of metal level diffusion as claimed in claim 10, it is characterized in that the material of this multiple layer metal layer structure is titanium/aluminium/titanium layer, titanium/aluminium/titanium nitride layer, titanium/copper/titanium layer, chromium/copper/chromium layer, tungsten/copper/tungsten layer, molybdenum nitride/aluminium/nitrogenize molybdenum layer, molybdenum/aluminium neodymium alloy layer, molybdenum nitride/aluminum titanium alloy layer, molybdenum/aluminium neodymium alloy/molybdenum layer, tantalum/copper/tantalum layer, tantalum nitride/copper/tantalum nitride layer, titanium nitride/copper/titanium nitride layer, titanium/aluminium lamination, molybdenum/copper/molybdenum layer or molybdenum/aluminium/molybdenum layer.

12. a TFT electrode structure that prevents the metal level diffusion is characterized in that this structure includes at least:

One the first metal layer is formed on the substrate, is the grid of a thin-film transistor after etching;

One transparency conductive electrode, directly be formed at substrate and this first metal layer top after etching, coat this grid, and this transparency conductive electrode is divided into pixel electrode part and non-pixel electrode part after etching, wherein pixel electrode part is as pixel electrode, and this pixel electrode is located immediately on the substrate and is not connected with gate short;

One dielectric layer is formed at above the non-pixel electrode part of this transparency conductive electrode, is an insulating barrier;

One amorphous silicon layer is formed at this dielectric layer top; And

One second metal level is formed at this amorphous silicon layer top, forms the source electrode and the drain electrode of this thin-film transistor after etching.

13. the TFT electrode structure that prevents the metal level diffusion as claimed in claim 12 is characterized in that this TFT electrode structure is an one pole or multi-polar structure.

14. the TFT electrode structure that prevents the metal level diffusion as claimed in claim 12 is characterized in that the surface of this substrate has silicon nitride, silica, metal level or organic material.

15. the TFT electrode structure that prevents the metal level diffusion as claimed in claim 12 is characterized in that, forms this transparency conductive electrode with physical vaporous deposition.

16. the TFT electrode structure that prevents the metal level diffusion as claimed in claim 12 is characterized in that this transparency conductive electrode is ITO, IZO, ZnO or organic material.

17. the TFT electrode structure that prevents the metal level diffusion as claimed in claim 12 is characterized in that this first metal layer is single metal-layer structure.

18. the TFT electrode structure that prevents the metal level diffusion as claimed in claim 17 is characterized in that the material of this single metal-layer structure is chromium, copper, aluminium neodymium alloy, molybdenum and tungsten alloy or aluminium.

19. the TFT electrode structure that prevents the metal level diffusion as claimed in claim 12 is characterized in that this first metal layer is a multiple layer metal layer structure.

20. the TFT electrode structure that prevents the metal level diffusion as claimed in claim 19, it is characterized in that the material of this multiple layer metal layer structure is titanium/aluminium/titanium layer, titanium/aluminium/titanium nitride layer, titanium/copper/titanium layer, chromium/copper/chromium layer, tungsten/copper/tungsten layer, molybdenum nitride/aluminium/nitrogenize molybdenum layer, molybdenum/aluminium neodymium alloy layer, molybdenum nitride/aluminum titanium alloy layer, molybdenum/aluminium neodymium alloy/molybdenum layer, tantalum/copper/tantalum layer, tantalum nitride/copper/tantalum nitride layer, titanium nitride/copper/titanium nitride layer, titanium/aluminium lamination, molybdenum/copper/molybdenum layer or molybdenum/aluminium/molybdenum layer.

21. the TFT electrode structure that prevents the metal level diffusion as claimed in claim 12, it is characterized in that, between the described amorphous silicon layer and second metal level, also be formed with a N+ amorphous silicon layer, this N+ amorphous silicon layer is directly deposited by plasma gain chemical vapour deposition technique and forms, or the N+ ion flow into the amorphous silicon layer top and forms with the ion injection mode.

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