CN107316907A - Coplanar type thin film transistor (TFT) and its manufacture method - Google Patents

Abstract

The invention provides a coplanar thin film transistor, comprising: a gate covering the substrate; a gate insulating layer covering the gate; a source and a drain covering the gate insulating layer, located between the source and the drain. In the channel region between the drain electrodes, the source electrode and the drain electrode have a two-layer structure, the bottom layer is a copper layer, and the top layer is a titanium layer. The titanium layer is located on the copper layer and partly located on the side of the channel area; , the titanium layer is in contact with the semiconductor layer, the titanium layer includes a titanium barrier layer, and the titanium barrier layer isolates the copper layer and the semiconductor layer. The invention solves the problem of the contact between the copper layer and the semiconductor layer at the channel region, avoids the diffusion of copper atoms to the semiconductor layer, and thus achieves the purpose of isolating the copper layer and the semiconductor layer.

Description

Coplanar thin film transistor and manufacturing method thereof

technical field

The invention belongs to the technical field of thin film transistors, and in particular relates to a coplanar thin film transistor, a manufacturing method thereof, an array substrate, a liquid crystal panel, and a display device.

Background technique

Among flat panel display devices, Thin Film Transistor Liquid Crystal Display (TFT-LCD for short) has the characteristics of small size, low power consumption, relatively low manufacturing cost and low radiation.

In the coplanar thin film transistor structure, as shown in FIG. 1, the coplanar thin film transistor 10 includes a gate 02 covering the substrate 01, a gate insulating layer 03 covering the gate 02, and The source and the drain on the insulating layer 03, wherein both the source and the drain have a two-layer structure, the bottom copper layer 041, the top layer is a titanium layer 042, and the semiconductor layer 05 covering the source and the drain, wherein, The semiconductor layer 05 is an IGZO semiconductor layer and an insulating layer 06 covering the semiconductor layer 05 . Wherein, the channel region 07 is located between the source and the drain. At the channel region 07 , since the copper layer and the titanium layer are etched simultaneously, the source and drain electrodes will be in contact with the semiconductor layer on the side of the channel region, that is, the copper layer 041 is in direct contact with the semiconductor layer 05 . For IGZO semiconductors, there is a problem of diffusion of copper atoms in the IGZO film, which will lead to short circuit of TFT devices and switch failure.

In this case, aiming at the diffusion of copper atoms, the present invention proposes a new coplanar thin film transistor structure: a barrier layer is provided on the side of the channel to isolate the copper layer from the semiconductor layer.

Contents of the invention

The object of the present invention is to provide a coplanar thin film liquid crystal tube which solves the short circuit of the thin film transistor device caused by the diffusion of copper atoms in the copper layer in the semiconductor layer.

The present invention provides a coplanar thin film transistor, comprising: a gate; a source; a drain; and a channel region located between the source and the drain; wherein the source and the drain both include a A copper layer, and a titanium layer located above the copper layer and partly located on the side of the channel region; a semiconductor layer is provided in the channel region, and the titanium layer is in contact with the semiconductor layer.

Preferably, the titanium layer includes a titanium barrier layer disposed on the side of the channel region, the titanium barrier layer covers the copper layer, and isolates the copper layer from the semiconductor layer.

Preferably, the distance between the copper layer of the source electrode and the copper layer of the drain electrode is greater than the distance between the titanium layer of the source electrode and the titanium layer of the drain electrode.

Preferably, a gate insulating layer is further included, the gate is below the gate insulating layer, and the source, drain and semiconductor layer are above the gate insulating layer.

Preferably, the gate insulating layer adopts a combined film layer of _SiOx and _SiNx , wherein the _SiNx film layer is located above the gate, and the _SiOx film layer is located above the _SiNx film layer.

Preferably, the semiconductor layer is an IGZO semiconductor layer

The present invention further provides an array substrate, which includes gate lines and data lines criss-crossing, and also includes the aforementioned coplanar thin film transistor, and the coplanar thin film transistor is located at the intersection of the gate lines and data lines.

The present invention also provides a method for manufacturing a coplanar thin film transistor, the method comprising:

The first step: forming the gate;

Step 2: forming a gate insulating layer overlying the gate;

Step 3: forming a source and a drain covering the gate insulating layer, the source and drain are at least composed of a titanium layer formed of metal titanium, and a channel region is formed between the source and the drain , the titanium layer is located in the channel region;

Step 4: forming a semiconductor layer located in the channel region, the semiconductor layer is in contact with the titanium layer of the source and the titanium layer of the drain.

Preferably, the specific steps of the third step are:

Depositing a copper layer formed of metallic copper on the gate insulating layer;

Coating a layer of first photoresist layer on the copper layer;

Exposing the first photoresist layer, the length of exposure on the photoresist layer is a; at the same time, over-etching the copper layer below the photoresist layer, the length of copper layer etching is b, where b>a>0 ;

removing the first photoresist layer;

Depositing a titanium layer formed of metal titanium on the copper layer, and the titanium layer is located on the surface and sides of the copper layer;

coating a second photoresist layer on the titanium layer;

Exposing the second photoresist layer, the length of exposure on the photoresist layer is a; at the same time, etching the titanium layer below the photoresist layer to form a channel region and a titanium barrier layer is provided on the side of the channel region;

removing the second photoresist layer;

The semiconductor layer is sputtered in the trench region.

Preferably, the specific steps of the second step are:

Cover the SiN _X film layer on the gate;

A _SiOx film layer is formed on the _SiNx film layer.

The present invention isolates the copper layer from the semiconductor layer at the channel region, so that in the subsequent patterning process of the titanium layer, the copper layer at the channel region is covered, thereby blocking the contact between the copper layer and the semiconductor layer.

Description of drawings

FIG. 1 is a schematic structural diagram of an existing coplanar thin film transistor;

2 is a schematic structural view of a coplanar thin film transistor of the present invention;

3-8 are exploded schematic diagrams of the manufacturing method of the coplanar thin film transistor of the present invention.

detailed description

Below in conjunction with accompanying drawing and specific embodiment, further illustrate the present invention, should be understood that these embodiments are only for illustrating the present invention and are not intended to limit the scope of the present invention, after having read the present invention, those skilled in the art will understand various aspects of the present invention Modifications in equivalent forms all fall within the scope defined by the appended claims of this application.

As shown in FIG. 2 , the coplanar thin film transistor 100 of the present invention includes a gate 2 covering the substrate 1 , a gate insulating layer 3 covering the gate 2 , and a source covering the gate insulating layer 3 . electrode and drain electrode, and a channel region 7 formed between the source electrode and the drain electrode, wherein both the source electrode and the drain electrode have a two-layer structure, including a copper layer 41 at the bottom layer and a titanium layer 42 at the top layer, wherein, The titanium layer 42 is located on the copper layer 41 and partially located on the side of the channel region 7 . The semiconductor layer 5 is disposed in the channel region 7 . The semiconductor layer 5 covers the source and drain electrodes. The titanium layer 42 is in contact with the semiconductor layer 5 . The distance between the copper layer of the source electrode and the copper layer of the drain electrode is greater than the distance between the titanium layer of the source electrode and the titanium layer of the drain electrode.

Preferably, the metal used for the gate is a single metal or a composite metal in Mo, Al, Cu, Ti or other metals; the gate insulating layer 3 is made of a combination of _SiOx and _SiNx , and the gate is covered with a _SiNx film , forming a SiO _X film layer on the SiN _X film layer. Among them, _SiNx has excellent waterproof performance, and placing _SiOx on the upper layer can provide oxygen atoms for IGZO and prevent the diffusion of H in _SiNx . The semiconductor layer 5 is an IGZO semiconductor layer.

The coplanar thin film transistor 100 further includes an insulating layer 6 covering the semiconductor layer 5 , preferably, the insulating layer 6 can be SiO _x or SiN _x or a combination of both.

The titanium layer 42 includes a titanium barrier layer 8 located at the channel region 7 , and the titanium barrier layer 8 isolates the copper layer 41 from the semiconductor layer 5 and prevents copper atoms in the copper layer 41 from diffusing into the semiconductor layer 5 . Specifically, the titanium barrier layer 8 is disposed on the side of the channel region 7 and can cover the side of the copper layer 41 at the channel region 7 . Since the contact resistance between titanium and the IGZO semiconductor is 0.001 ohm, the present invention selects titanium as the barrier layer between the copper layer and the IGZO semiconductor layer. Preferably, since titanium is an existing metal in the source and drain electrodes, the titanium barrier layer 8 is a part of the titanium layer 42 , and no additional barrier layer is needed, which saves production costs.

The copper layer 41 adopts an over-etching process to leave the position of the titanium barrier layer 8, so that the titanium barrier layer 8 can be deposited on the outside of the copper layer 41 to avoid contact with the semiconductor layer 5,

Figure 3-Figure 8 is a schematic diagram of the method of manufacturing the coplanar thin film transistor of the present invention, the method includes:

S01: As shown in FIG. 3 , the gate 2 is patterned to form the gate 2 covering the substrate 1 , and the specific steps are: film formation, exposure, and etching. Wherein, the material used for the gate 2 is a single metal or a composite metal such as metal Mo, Al, Cu, Ti, etc.

S02: As shown in FIG. 4 , the gate insulating layer 3 is formed to form the gate insulating layer 3 covering the gate 2 . Preferably, the gate insulating layer 3 adopts a combined film layer of _SiOx and _SiNx , the gate is covered with a film layer of _SiNx , and a film layer of _SiOx is formed on the film layer of _SiNx . SiN _X with excellent water resistance is placed on the lower layer, and SiO _X is placed on the upper layer, so as to provide oxygen atoms for the IGZO semiconductor and prevent the diffusion of H in SiN _X.

S03: forming a source and a drain overlying the gate insulating layer 3, the source and the drain are at least composed of a titanium layer formed of metal titanium, and a channel region is formed between the source and the drain, the titanium layer is located in the channel region.

Preferably, the source and the drain have a two-layer structure, the bottom layer is a copper layer 41 , and the top layer is a titanium layer 42 .

The specific steps are:

S031: Deposit a copper layer formed of metal copper on the gate insulating layer.

S032: Coating a first photoresist layer 91 on the copper layer.

S033: Expose the first photoresist layer 91, the length of exposure on the photoresist layer is a; at the same time, perform over-etching treatment on the copper layer below the photoresist layer, the copper layer is patterned, and the length of the copper layer etching is b, where b>a>0; as shown in FIG. 5 , thereby leaving a space for depositing a titanium barrier layer. During operation, the adhesion between the photoresist and the copper layer can be appropriately reduced, thereby promoting the over-etching of the copper layer.

S034: Remove the first photoresist layer 91 .

S035: Deposit a titanium layer 42 formed of metal titanium on the copper layer 41, and the titanium layer is located on the surface and side surfaces of the copper layer.

S036: Coating a second photoresist layer 92 on the titanium layer.

S037: Expose the second photoresist layer 92, the length of exposure on the photoresist layer is a; at the same time, perform etching treatment on the titanium layer below the photoresist layer, pattern the titanium layer, and form the channel region 7 and A titanium barrier layer 8 is provided on the side of the channel region, as shown in FIG. 6 . Titanium is deposited on the side of the channel region 7 to form a titanium barrier layer 8 between the copper layer 41 and the IGZO semiconductor layer 5, thereby covering the copper layer 41 at the channel region 7, so that the titanium layer 42 of the source and drain electrodes is in the The distance b between the channel regions 7 is smaller than the gap a between the source and drain copper layers 41 at the channel regions 7 . During operation, the adhesion between the photoresist and the titanium layer can be appropriately improved, thereby avoiding over-etching of the titanium layer.

S038: removing the second photoresist layer;

S04: As shown in FIG. 7 , IGZO is formed into a film, and the semiconductor layer is sputtered in the channel region to form a semiconductor layer 5 covering the source and drain. The semiconductor layer 5 is located in the channel region 7 , and the titanium barrier layer 8 at the channel region 7 is used to avoid contact with the copper layer 41 and prevent copper atoms from diffusing into the semiconductor layer.

S05: As shown in FIG. 8 , form an insulating layer 6 overlying the semiconductor layer 5 ; the specific steps are film formation, exposure, and etching. Wherein, the material of the insulating layer 6 can be SiO _X or SiN _X or a combination of both.

The manufacturing method of the present invention requires 5 photomasks in total, wherein the same photomask is shared when forming the copper layer and the titanium layer. Compared with the Lift-off process (stripping process), one photomask is missing, and the production process is optimized. , saving manufacturing cost.

The present invention is based on the problem of diffusion between copper and IGZO. During the copper layer patterning process, the copper at the channel area is properly over-etched, and a barrier layer is provided on the side of the channel area, so that the titanium covers the channel. Copper in the road area. Since the stress between copper and titanium is just matched, the neutralization stress of the composite film is reduced, which improves the bonding force between the metal copper and the dielectric film, and the contact resistance between titanium and IGZO is 0.001 ohm, so titanium is selected as the copper and Barrier layer between IGZO layers. And since titanium is an existing metal in the source and drain, no additional barrier layer is required. It solves the problem that copper atoms diffuse into the IGZO film, which causes the leakage current of the TFT device to increase and the switch fails, and achieves the technical effect of avoiding the diffusion of copper atoms into the IGZO film.

Claims (10)

1. A coplanar thin film transistor comprising:

a gate (2);

a source electrode;

a drain electrode; and

a channel region (7) located between the source and the drain; wherein,

the source electrode and the drain electrode both comprise a copper layer (41) at the bottom and a titanium layer (42) above the copper layer (41) and partly on the side of the channel region (7); a semiconductor layer (5) is arranged in the channel region (7), and the titanium layer (42) is in contact with the semiconductor layer (5).

2. Coplanar thin film transistor according to claim 1 characterized in that the titanium layer (42) comprises a titanium barrier layer (8), the titanium barrier layer (8) being arranged laterally to the channel region (7), the titanium barrier layer (8) covering the copper layer (41) and isolating the copper layer (41) from the semiconductor layer (5).

3. Coplanar thin film transistor according to claim 1 characterized in that the distance between the copper layers of the source and drain electrodes (41) is greater than the distance between the titanium layers of the source and drain electrodes (42).

4. A coplanar thin film transistor as claimed in claim 1 further comprising a gate insulating layer (3) below which the gate electrode is located and above which the source, drain and semiconductor layers are located.

5. Coplanar thin film transistor according to claim 4 wherein the gate insulator layer (3) is of SiO_XAnd SiN_XA combined film layer of SiN_XA film layer is arranged above the gate, and the SiO layer_XA film layer is located on the SiN_XAbove the film layer.

6. Coplanar thin film transistor according to claim 1 wherein the semiconductor layer (5) is an IGZO semiconductor layer.

7. An array substrate comprising criss-crossed gate and data lines, further comprising the coplanar thin film transistor of any one of claims 1 to 6, the coplanar thin film transistor being located at an intersection of the gate and data lines.

8. A method of fabricating a coplanar thin film transistor, the method comprising:

the first step is as follows: forming a gate (2);

the second step is that: forming a gate insulating layer (3) overlying the gate electrode (2);

the third step: forming a source electrode and a drain electrode which cover the grid electrode insulating layer (3), wherein the source electrode and the drain electrode at least consist of titanium layers formed by metal titanium, and a channel region (7) is formed between the source electrode and the drain electrode, and the titanium layers are positioned in the channel region;

the fourth step: a semiconductor layer (5) is formed in the channel region, the semiconductor layer being in contact with the titanium layer of the source electrode and the titanium layer of the drain electrode.

9. The method according to claim 8, wherein the third step comprises the following specific steps:

depositing a copper layer formed of metallic copper on the gate insulating layer (3);

coating a first photoresist layer on the copper layer;

exposing the first photoresist layer, wherein the exposure length on the photoresist layer is a; meanwhile, carrying out over-etching treatment on the copper layer positioned below the photoresist layer, wherein the etching length of the copper layer is b, and b is greater than a and greater than 0;

removing the first photoresist layer;

depositing a titanium layer formed by metallic titanium on the copper layer, wherein the titanium layer is positioned on the surface and the side surface of the copper layer;

coating a second light resistance layer on the titanium layer;

exposing the second photoresist layer, wherein the exposure length on the photoresist layer is a; simultaneously, etching the titanium layer below the photoresist layer to form a channel region, wherein the side surface of the channel region is provided with a titanium barrier layer;

removing the second photoresist layer.

10. The method according to claim 8, wherein the second step comprises the following specific steps:

covering the gate with SiN_XA film layer;

in SiN_XForming SiO on the film layer_XAnd (5) film layer.