CN100399178C - Manufacturing method of pixel structure - Google Patents

Abstract

A method for manufacturing a pixel structure comprises forming a gate on a substrate. And then forming a gate insulating layer on the substrate to cover the gate electrode. And sequentially forming a patterned semiconductor layer and a patterned metal layer on the gate insulating layer and the gate electrode. A first insulating layer is formed on the substrate to cover the patterned metal layer. Then, the first insulating layer is patterned to expose a portion of the patterned metal layer. And forming a pixel electrode on the substrate, wherein the pixel electrode is in contact with the exposed patterned metal layer, and the patterned metal layer and the partial-thickness patterned semiconductor layer above the gate electrode are removed to define a source electrode, a drain electrode and a channel layer, and the pixel electrode is electrically connected with the drain electrode. The method of the present invention can reduce the number of photolithography masks required by the process and increase the yield of the thin film transistor and the pixel structure manufactured by using the same.

Description

Manufacturing method of pixel structure

technical field

The present invention relates to a method for manufacturing a pixel structure, and in particular to a method for manufacturing a pixel structure using a four-photomask.

Background technique

A thin film transistor liquid crystal display (TFT-LCD) is mainly composed of a thin film transistor array substrate, a color filter array substrate and a liquid crystal layer. The thin film transistor array substrate is composed of a plurality of thin film transistors arranged in an array. and a pixel electrode corresponding to each thin film transistor. The thin film transistor includes a gate, a channel layer, a drain and a source, and the thin film transistor and the pixel electrode form a pixel structure. Among them, thin film transistors are used as switching elements of liquid crystal display units.

When manufacturing thin film transistors, one of the most important considerations is to reduce the number of processes, thereby reducing the manufacturing cost. In particular, if the number of photolithography masks required for the process can be reduced, the manufacturing cost can be effectively reduced. Generally speaking, five to seven photolithographic masks are used to manufacture thin film transistors, but in order to improve process efficiency, four photolithographic mask processes have become a trend in the manufacture of new generation thin film transistors.

US Patent No. 6,653,028 proposes a process for producing thin film transistors using four photolithography masks. Figures 1A-1E are cross-sectional views of the known steps of manufacturing thin film transistors.

Referring to FIG. 1A , firstly a gate 110 is formed on a substrate 100 , and then a gate insulating layer 120 , a channel material layer 130 , an ohmic contact material layer 140 , a metal layer 150 and a photoresist layer 160 are sequentially formed.

Referring to FIG. 1B , the photoresist layer 160 is then exposed and developed to form a patterned photoresist layer 160 a. The patterned photoresist layer 160a covers the active region 170 where the TFT will be formed. It should be noted that the patterned photoresist layer 160a is exposed using a half-tone photolithography mask, so the middle thickness d1 of the patterned photoresist layer 160a is thinner than the thickness d2 at both sides.

FIG. 2 is a schematic diagram of a semi-transparent photolithography mask. Referring to FIG. 2 , the semi-transparent photolithographic mask 200 includes a transparent region A, a non-transparent region B and a semi-transparent region C. Referring to FIG. Wherein, a light-shielding pattern 220 is designed on the substrate 210 in the non-transparent region B and the semi-transparent region C. When the photolithography mask 200 is used to perform the exposure process, the semi-transparent region C corresponds to the middle position of the active region 170 covered by the patterned photoresist layer 160 a shown in FIG. 1B . Because the exposure intensity of the semi-transparent area C is higher than that of the non-transparent area B, and the exposure intensity of the semi-transparent area C is lower than that of the transparent area A, it can be formed after exposure and development. 1B shows a patterned photoresist layer 160a with different thicknesses.

Please continue to refer to FIG. 1C , using the patterned photoresist layer 160 a as an etching mask, an etching process is performed to remove the metal layer 150 outside the active region 170 to form a patterned metal layer 150 a.

Referring to FIG. 1D , continue to use the patterned photoresist layer 160a as an etching mask to perform another etching process to remove the ohmic contact material layer 140 and the channel material layer 130 outside the active region 170 to form the ohmic contact layer 140a and the channel. layer 130a. At the same time, because the middle thickness d1 of the patterned photoresist layer 160a on the active region 170 is relatively thin, the middle part of the patterned photoresist layer 160a and the patterned metal layer 150a below it will be moved simultaneously. In addition, the source 150a' and the drain 150a" are defined.

Referring to FIG. 1E, the etching process is continued to remove the ohmic contact layer 140a between the source electrode 150a' and the drain electrode 150a" and the channel layer 130a with a partial thickness, and then remove the patterned photoresist layer 160a. That is, the thin film transistor 300 is formed.

However, in the manufacturing process of the above-mentioned thin film transistor 300 , it is necessary to use the semi-transparent photolithographic mask 200 , which will not only increase the difficulty in designing the photolithographic mask. Moreover, at the edge of the light-shielding pattern 220 of the semi-transparent photolithographic mask 200, diffraction phenomenon is likely to occur during exposure, which reduces the precision of the exposure pattern. In addition, only using the patterned photoresist layer 160a to perform multiple etching processes may not be sufficient for the protection of the thin film transistor 300 during the manufacturing process, thus causing the thin film transistor 300 and the pixel structure (not shown in the figure) to be fabricated using it. ) manufacturing pass rate decreased.

Contents of the invention

The purpose of the present invention is to provide a method for manufacturing a pixel structure using a four-pass photolithography mask process, which is suitable for reducing the number of photolithography masks required for the process, and improving the manufacture of thin film transistors and pixel structures manufactured using it Pass rate.

The invention proposes a method for manufacturing a pixel structure, which firstly forms a gate on a substrate. Next, a gate insulating layer is formed on the substrate to cover the gate. A patterned semiconductor layer and a patterned metal layer are sequentially formed on the gate insulation layer and the gate. A first insulating layer is formed on the substrate to cover the patterned metal layer. Next, the first insulating layer is patterned to expose part of the patterned metal layer. Afterwards, a pixel electrode is formed on the substrate, and the pixel electrode is in contact with the exposed patterned metal layer, and at the same time, the patterned metal layer above the gate and part of the thickness of the patterned semiconductor layer are removed to define a source, drain and channel layer, and the pixel electrode is electrically connected to the drain, and the gate, source and drain form a thin film transistor.

The present invention further proposes a method for manufacturing a four-pass photolithographic mask pixel structure, which includes the following steps. Firstly, a first photolithography mask process is performed to form a gate on the substrate. Next, a gate insulating layer is formed on the substrate to cover the gate. Then, a second photolithography mask process is performed to sequentially form a patterned semiconductor layer and a patterned metal layer on the gate insulating layer and the gate. Next, a first insulating layer is formed on the substrate to cover the patterned metal layer. Then, a third photolithography mask process is performed to pattern the first insulating layer, thereby exposing part of the patterned metal layer. Afterwards, a fourth photolithographic masking process is performed to form a pixel electrode on the substrate, and the pixel electrode is in contact with the exposed patterned metal layer, and at the same time, the patterned metal layer and part above the gate are removed Thick patterned semiconductor layer to define the source, drain and channel layer, and the pixel electrode will be electrically connected to the drain, and the gate, source and drain form a thin film transistor.

In the embodiment of the present invention, for example, another insulating layer is formed on the thin film transistor. A method for forming another insulating layer on the thin film transistor is, for example, firstly forming a second insulating layer on the substrate, which covers the thin film transistor and the pixel electrodes. Next, a photoresist layer is formed on the second insulating layer. Then, a back exposure process and a development process are performed on the photoresist layer to form a patterned photoresist layer, and the patterned photoresist layer covers the thin film transistor. Afterwards, the patterned photoresist layer is used as an etching mask to remove the second insulating layer covering the pixel electrodes, leaving the second insulating layer covering the TFT.

In an embodiment of the present invention, the above-mentioned patterned semiconductor layer includes, for example, a patterned channel material layer and a patterned ohmic contact material layer, and the material of the patterned channel material layer is, for example, amorphous silicon, and the patterned ohmic contact material layer The material is, for example, doped amorphous silicon.

In an embodiment of the present invention, the above-mentioned method for forming a pixel electrode on a substrate includes performing a sputtering process and a patterning process.

In an embodiment of the present invention, the pixel electrode is made of, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

In an embodiment of the present invention, the above-mentioned substrate is made of glass, for example.

In an embodiment of the present invention, the material of the gate insulating layer is, for example, silicon nitride or silicon oxide.

In an embodiment of the present invention, the material of the gate material layer is, for example, metal.

The present invention adopts the process of four photolithography masks, which not only saves the cost of photolithography masks compared with the known five photolithography mask processes, but also does not need to use semi-transparent photolithography masks, which can help Improvement of process pass rate. In addition, compared with the known four-pass photolithography mask process, the method of the present invention reduces the etching damage to the source, drain and channel layer (semiconductor layer) of the thin film transistor.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

1A-1E are cross-sectional views of the steps of manufacturing thin film transistors in the prior art.

FIG. 2 is a schematic diagram of a semi-transparent photolithography mask.

3A to 3M are cross-sectional schematic diagrams showing the steps of a method for manufacturing a pixel structure in a preferred embodiment of the present invention.

4A-4C are schematic cross-sectional views of the manufacturing process of covering another insulating layer on the thin film transistor in a preferred embodiment of the present invention.

Description of main component marking

100: Substrate

110: grid

120: gate insulating layer

130: channel material layer

130a: channel layer

140: Ohmic contact material layer

140a: Ohmic contact layer

150: metal layer

150a: patterned metal layer

150a': source

150a": drain

160: photoresist layer

160a: patterning photoresist layer

170: active area

200: semi-transparent photolithography mask

210: transparent substrate

220: Blackout pattern

300: thin film transistor

400: Substrate

410: gate material layer

410': grid

420, 422, 424, 426: patterned photoresist layer

424a, 424b, 462, 464: openings

430: Gate insulating layer

440: Semiconductor layer

440': patterned semiconductor layer

440'a: channel layer

442: Channel material layer

442': Patterned channel material layer

444: Ohmic contact material layer

444': patterned ohmic contact material layer

450: metal layer

450': patterned metal layer

450'a: source

450'b: drain

460: insulating layer

460': patterned insulating layer

470: transparent conductive layer

470a: pixel electrode

500: thin film transistor

610: insulating layer

610': Etched insulating layer

620: photoresist layer

620': patterned photoresist layer

630: Back exposure process

d1, d2: thickness

A: Translucent area

B: non-transparent area

C: Semi-transparent area

Detailed ways

The manufacturing method of the pixel structure of the thin film transistor liquid crystal display proposed by the present invention does not need to use a semi-transparent photolithography mask at all, and can use four photolithography masks to complete the manufacture of the pixel structure. The manufactured substrate with multiple pixel structures can be matched with the color filter substrate and liquid crystal layer in any way to form a thin film transistor liquid crystal display panel. The following descriptions are preferred embodiments of the present invention, but are not intended to limit the present invention.

3A to 3M are cross-sectional schematic diagrams showing the steps of a method for manufacturing a pixel structure in a preferred embodiment of the present invention.

Firstly, a gate 410' is formed on the substrate 400 (as shown in FIG. 3C ). In one embodiment, the method for forming the gate 410' is, for example, using the steps shown in FIG. 3A to FIG. 3C . Referring first to FIG. 3A , a gate material layer 410 is formed on a substrate 400 , wherein the method of forming the gate material layer 410 is, for example, sputtering. The material of the substrate 400 is, for example, glass, and the material of the gate material layer 410 is, for example, metal.

Next, as shown in FIG. 3B , a first photolithography masking process is performed to form a patterned photoresist layer 420 on the gate material layer 410 . Afterwards, an etching process is performed using the patterned photoresist layer 420 as a mask to pattern the gate material layer 410 to form a gate 410', as shown in FIG. 3C. The above etching process is, for example, a dry etching process or a wet etching process. After forming the gate 410', the patterned photoresist layer 420 is removed.

Afterwards, referring to FIG. 3D , a gate insulating layer 430 is formed on the substrate 400 to cover the gate 410'. In a preferred embodiment, the method of forming the gate insulating layer 430 is, for example, chemical vapor deposition (CVD), and the material of the gate insulating layer 430 is, for example, silicon nitride or silicon oxide.

Next, a patterned semiconductor layer and a patterned metal layer are sequentially formed on the gate insulation layer 430 and the gate 410' (as shown in FIG. 3G ). In one embodiment, the forming method is, for example, using the steps shown in FIG. 3E to FIG. 3G .

Referring to FIG. 3E first, a semiconductor layer 440 and a metal layer 450 are sequentially formed on the gate insulating layer 430 . In a preferred embodiment, the method for forming the semiconductor layer 440 is, for example, chemical vapor deposition, and the semiconductor layer 440 includes, for example, a channel material layer 442 and an ohmic contact material layer 444 . The material of the channel material layer 442 is, for example, amorphous silicon, and the material of the ohmic contact material layer 444 is, for example, doped amorphous silicon. The method of forming the metal layer 450 is, for example, sputtering.

Then, the metal layer 450 and the semiconductor layer 440 are patterned to form a patterned metal layer 450' and a patterned semiconductor layer 440' (as shown in FIG. 3G ). In one embodiment, the above patterning steps are shown in FIGS. 3F-3G . Please refer to FIG. 3F first. In one embodiment, a second photolithography masking process is performed to form a patterned photoresist layer 422 on the metal layer 450 . Next, an etching process is performed on the metal layer 450 and the semiconductor layer 440 by using the patterned photoresist layer 422 as an etching mask. Afterwards, the patterned photoresist layer 422 is removed to form a patterned metal layer 450' and a patterned semiconductor layer 440' as shown in FIG. 3G. Wherein, the patterned semiconductor layer 440' includes a patterned channel material layer 442' and a patterned ohmic contact material layer 444'.

Next, referring to FIG. 3H , an insulating layer 460 is formed on the substrate 400 to cover the patterned metal layer 450'. In one embodiment, the method for forming the insulating layer 460 is, for example, chemical vapor deposition, and the material of the insulating layer 460 is, for example, silicon oxide.

Next, a patterning process is performed on the insulating layer 460 . In one embodiment, the steps of patterning the insulating layer 460 are shown in FIGS. 3I-3J . Referring to FIG. 3I first, a third photolithographic masking process is performed to form a patterned photoresist layer 424 , wherein the patterned photoresist layer 424 exposes a portion of the insulating layer 460 . In more detail, the patterned photoresist layer 424 has an opening 424a and an opening 424b, wherein the position of the opening 424a is corresponding to the channel of the subsequently formed thin film transistor. The position of the opening 424b corresponds to above the drain of the subsequently formed thin film transistor.

Next, please refer to FIG. 3I again, using the patterned photoresist layer 424 as an etching mask, the insulating layer 460 is etched to form a patterned insulating layer 460', which has an opening 462 and an opening 464, and the opening 462 and The opening 464 exposes the patterned metal layer 450'. Afterwards, the patterned photoresist layer 424 is removed to obtain the structure shown in FIG. 3J .

Then, a pixel electrode is formed on the substrate 400, and the pixel electrode is in contact with the exposed patterned metal layer 450'. In a preferred embodiment, the method for forming the pixel electrode on the substrate 400 includes performing a sputtering process and a pattern Chemical process, the method of its formation is, for example, the steps shown in FIG. 3K-FIG. 3M.

First, please refer to FIG. 3K , a transparent conductive layer 470 is formed on the substrate 400, and the transparent conductive layer 470 is in contact with the exposed patterned metal layer 450'. In a preferred embodiment, the method for forming the transparent conductive layer 470 on the substrate 400 includes performing a sputtering process, and the material of the transparent conductive layer 470 is, for example, indium tin oxide (ITO) or indium zinc oxide. (indium zinc oxide, IZO). It should be noted that the transparent conductive layer 470 is in electrical contact with the patterned metal layer 450' through the opening 462 and the opening 464.

Afterwards, a patterning process is performed on the transparent conductive layer 470 . In one embodiment, the steps of patterning the transparent conductive layer 470 are shown in FIGS. 3L-3M . Please refer to FIG. 3L first, perform a fourth photolithography mask process to form a patterned photoresist layer 426 on the transparent conductive layer 470, wherein the patterned photoresist layer 426 has an opening 426a, and the opening 426a will correspond to At the position of the opening 462 of the patterned insulating layer 460 ′. Next, an etching process is performed using the patterned photoresist layer 426 as an etching mask to remove the transparent conductive layer 470 not covered by the photoresist layer 426 to define the pixel electrode 470a. In particular, this etching process simultaneously removes the transparent conductive layer 470 exposed by the opening 426a, the patterned metal layer 450' and the part of the thickness of the patterned semiconductor layer 440', and defines the source 450'a and the drain. 450'b and the channel layer 440'a, and the pixel electrode 470a is electrically connected to the drain 450'b, and the gate 410', the source 450'a and the drain 450'b form a thin film transistor 500, as shown in FIG. 3M Show. Then the patterned photoresist layer 426 is removed. The thin film transistor 500 can be used as a switch element for controlling the pixel electrode 470a, and the thin film transistor 500 and the pixel electrode 470a form a pixel structure.

It can be seen from the above that the present invention only needs to use four photolithography masks to complete the manufacture of the pixel structure. Moreover, in the process of the present invention, since there is no need to use a semi-transparent photolithographic mask, the cost required for photolithographic mask design can be reduced, and the patterned photoresist layer used in each process does not have a local In the case of a thinner thickness, the function of an etching mask can be fully utilized to avoid etching damage to the formed structure during the etching step. Therefore, the method of the present invention reduces the etching damage to the source, drain and channel layer (semiconductor layer) of the thin film transistor, thus contributing to the improvement of yield.

In addition, in a preferred embodiment of the present invention, after forming the thin film transistor 500 , another insulating layer is formed on the thin film transistor 500 . 4A-4C are schematic cross-sectional views of the manufacturing process of covering another insulating layer on the thin film transistor in a preferred embodiment of the present invention.

Referring to FIG. 4A , first, an insulating layer 610 is formed on the substrate 400 to cover the thin film transistor 500 and the pixel electrode 470a. The method of forming the insulating layer 610 is, for example, chemical vapor deposition, and the material of the insulating layer 610 is, for example, silicon oxide.

Referring to FIG. 4A again, the photoresist layer 620 is continuously formed on the insulating layer 610 . Then, a backside exposure process 630 and a developing process are performed on the photoresist layer 620 to form a patterned photoresist layer 620' as shown in FIG. 4B, and the patterned photoresist layer 620' covers the thin film transistor 500. .

Afterwards, as shown in FIG. 4B, using the patterned photoresist layer 620' as an etching mask, an etching process is performed to remove the insulating layer 610 covering the pixel electrode 470a, while leaving the via covering the thin film transistor 500. The etched insulating layer 610' is shown in FIG. 4C.

In summary, the manufacturing method of the pixel structure of the present invention includes the following advantages:

(1) The present invention uses four photolithography masks to manufacture the pixel structure, which can simplify the process and reduce the cost of the photolithography mask compared with the known five photolithography mask process.

(2) The present invention does not need to use a semi-transparent photolithographic mask, so the problem of poor exposure accuracy at the edge of the pattern on the semi-transparent photolithographic mask can be avoided. Contribute to the improvement of process qualification rate.

(3) The process of the present invention can provide better protection for the source, drain and channel layer (semiconductor layer) of the thin film transistor.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (11)

1. A method for manufacturing a pixel structure, characterized in that it comprises: forming a gate on the substrate; forming a gate insulating layer on the substrate to cover the gate; sequentially forming a patterned semiconductor layer and a patterned metal layer on the gate insulating layer and the gate; forming a first insulating layer on the substrate to cover the patterned metal layer; patterning the first insulating layer, thereby exposing a part of the patterned metal layer; and forming a pixel electrode on the substrate, and the pixel electrode is in contact with the exposed patterned metal layer, and simultaneously removing the patterned metal layer and part of the thickness of the patterned semiconductor layer above the gate, A source, a drain and a channel layer are defined, and the pixel electrode is electrically connected to the drain, and the gate, the source and the drain form a thin film transistor. 2. The method for manufacturing a pixel structure according to claim 1, further comprising forming another insulating layer on the thin film transistor. 3. The method for manufacturing a pixel structure according to claim 2, wherein the method for forming another insulating layer on the thin film transistor comprises: forming a second insulating layer on the substrate, which covers the thin film transistor and the pixel electrode; forming a photoresist layer on the second insulating layer; performing a back exposure process and a development process on the photoresist layer to form a patterned photoresist layer, the patterned photoresist layer covers the thin film transistor; and The patterned photoresist layer is used as an etching mask to remove the second insulating layer covering the pixel electrode while leaving the second insulating layer covering the thin film transistor. 4. The method for manufacturing a pixel structure according to claim 1, wherein the patterned semiconductor layer comprises a patterned channel material layer and a patterned ohmic contact material layer. 5. The method for manufacturing a pixel structure according to claim 4, wherein the material of the patterned channel material layer comprises amorphous silicon. 6 . The method for manufacturing the pixel structure according to claim 4 , wherein the material of the patterned ohmic contact material layer includes doped amorphous silicon. 7. The manufacturing method of the pixel structure according to claim 1, wherein the method of forming the pixel electrode on the substrate comprises sputtering process and patterning process. 8. The method for manufacturing a pixel structure according to claim 1, wherein the pixel electrode is made of indium tin oxide (ITO) or indium zinc oxide (IZO). 9. The method for manufacturing a pixel structure according to claim 1, wherein the substrate is made of glass. 10. The manufacturing method of the pixel structure according to claim 1, wherein the gate insulating layer is made of silicon nitride or silicon oxide. 11. The manufacturing method of the pixel structure according to claim 1, wherein the material of the gate material layer includes metal.

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