CN100397661C - Metal-induced unidirectional lateral crystallization thin film transistor device and its preparation method - Google Patents

Abstract

The invention relates to a metal-induced single-direction lateral crystallization thin film transistor device and a preparation method thereof. Use catalytic metal nickel to form peripheral crystallized polysilicon islands on the amorphous silicon film covered under the low-temperature silicon oxide covering layer in the selective crystallization region, and select the appropriate position of the polysilicon islands to form metal-induced unidirectional lateral crystallization TFT trenches road. The optimized use of various metal-induced polysilicon materials can not only obtain high-performance polysilicon TFT devices, but also significantly reduce the crystallization time, effectively reduce the impact of substrate shrinkage and metal ion diffusion in the substrate, and improve the preparation yield. Rate. This technology is suitable for the preparation of low-temperature polysilicon circuits, active addressing substrates for low-temperature polysilicon displays, and the preparation of various microelectronic and optoelectronic products such as area array image sensors, and is a technology with important industrial application value.

Description

Metal-induced unidirectional lateral crystallization thin film transistor device and its preparation method

technical field

The invention relates to the preparation technology of thin-film microelectronic devices, in particular to a metal-induced single-direction lateral crystallization thin-film transistor device and a preparation method thereof. Use catalytic metal nickel to form peripheral crystallized polysilicon islands on the amorphous silicon film covered under the low-temperature silicon oxide covering layer in the selective crystallization region, and select the appropriate position of the polysilicon islands to form metal-induced unidirectional lateral crystallization TFT trenches road. Therefore, high-quality polysilicon thin film transistor technology can be obtained through a short crystallization time.

Background technique

High-performance flat-panel display devices, including liquid crystal displays (LCDs), organic light-emitting diodes (OLED/PLEDs), require active addressing and active drive technology for thin-film transistors (TFTs) (Development of High Quality LCDTV, M.Shigeta, H. Fukuoka, SID 04 Digest, Page 754; A 4.3-in.VGA (188ppi) Display with a New Driving Method, Y.Tanada, M.Osame, R.Fukumoto, K.Saito, J.Sakata, S.Yamazaki (Semiconductor Energy Laboratory Co., Ltd.) S. Murakami, K. Inose, N. Miyoshi (ELDis Inc.) K. Sato, SID04 Digest, Page 1398). The further development of active site selection and active driving technology can integrate the driving circuit (scanning circuit, digital circuit, DC level conversion, clock signal generator, etc.) and the active matrix on the same substrate to realize system integration ( SOP) so that the display has the characteristics of high display density, few external pins, and low cost (as reported by Y.Nakajima, Y.Kida et al. Latest Development of "System-on-Glass" Display with Low Temperature Poly-Si TFT (SID 2004 Digest, p864-867)). The best device choice for making a fully integrated display is the Low Temperature Polysilicon Thin Film Transistor (LTPS). The more mature LTPS technology now includes excimer laser annealing (ELA) crystallization method (such as: US Patent 6,071,796, Voutsastolis, "Method of Controlling Oxygen Incorporation During Crystallization of Silicon Film by Excimer Laser Annealing in Air Ambient) and metal-induced crystallization ( MIC), metal-induced lateral crystallization technology (MILC). The problem of the method existence of ELA has following shortcoming, and the equipment price of excimer laser is expensive, and mostly used is toxic gas, (as: Chinese patent, application number: 200410086941.8, Kasahara Kenji; Kawasaki Ritsuko; Otani Hisahi; Tanaka Koichiro, laser device and laser annealing method). There is also the problem of uneven distribution of device performance caused by beam-to-beam overlap, (such as: C-W Kim, K-C Moon, H-J Kim, Development of SLS-Based System on Glass Display, SID Digest 2004, p868-871).

Contents of the invention

The object of the present invention is to provide a metal-induced unidirectional lateral crystallization thin film transistor device and a preparation method thereof. Using a shorter crystallization time, a high-performance MIUC polysilicon TFT is obtained. The MIPC polysilicon is obtained by using the LTO mask area on the amorphous silicon, and the MIUC area in the MIPC polysilicon island is selected as the channel region of the MIUC polysilicon TFT to form a high-quality MIUC polysilicon TFT. Compared with conventional MIUC polysilicon TFT, the crystallization time can be shortened by 3-4 times, and the performance of the device is the same as that of conventional MIUC polysilicon TFT. Compared with MIPC and MIC polysilicon TFT, the crystallization time is similar, but the performance of the device is obviously better For MIPC and MIC polysilicon TFT. The device can be used to prepare low-temperature polysilicon circuits, flat panel display active addressing substrates, area array image sensors and the like.

The metal-induced unidirectional lateral crystallization thin film transistor device provided by the present invention is: a metal-induced unidirectional lateral crystallization thin film transistor is formed on a large-area transparent substrate, and the metal-induced unidirectional lateral crystallization thin film transistor includes:

Polysilicon islands crystallized around the large-area transparent substrate; the precursor formed by the polysilicon is an amorphous silicon film formed by LPCVD, PECVD or sputtering;

The transition layer deposited on the substrate, the amorphous silicon film is deposited on the LTO transition layer; the transition layer is silicon nitride or LTO transition layer;

A cover layer deposited on the amorphous silicon film; the cover layer is low temperature silicon oxide LTO, and the LTO cover layer is etched into a rectangular cover area by photolithography;

The induced nickel layer is on the surface of amorphous silicon outside the masking area;

After thermal annealing, the amorphous silicon outside the LTO mask area becomes MIC polysilicon, which is used to prepare capacitor electrodes and display pixel electrodes. For the amorphous silicon under the LTO mask pattern, four MIUC polysilicon regions (also collectively referred to as MIPC regions) are formed from the periphery of the mask region pattern to the middle. The MILCs that start to crystallize from the adjacent vertical sides stop crystallization after they meet, forming crystals at an angle close to 45 degrees and colliding with the grain boundary. The MILCs on the opposite sides collide with each other to form a collision grain boundary perpendicular to the direction of crystallization advancement;

The active channel selection of the thin film transistor is designed on one of the four metal-induced unidirectional crystallization (MIUC) regions.

A gate insulating layer and a gate electrode are sequentially prepared on the active island after photolithography etching.

The metal-induced unidirectional lateral crystallization thin film transistor device is characterized in that the pattern of the LTO masking layer is rectangular, and the size of the masking layer pattern is closely related to the position of the polysilicon TFT device on the substrate. The relatively long sides of the mask pattern and the colliding grain boundaries produced by MILC are separated at both ends of the channel, and the distance from the channel side is 3-5 microns; the position of one of the two relatively long sides is in the TFT trench 4 microns outside the track (relative to 5 micron TFT), the position of the other side is the channel twice as far from the opposite side plus the size of the bilateral margin, so that the collision grain boundaries of the opposing MILC crystallized from both sides are just distributed outside the channel 4 microns; the distance between the two narrow sides of the rectangle is greater than the sum of the width of the channel and the length of the two narrow sides.

The metal-induced unidirectional lateral crystallization thin film transistor device is characterized in that the transparent substrate is glass substrate glass or quartz glass that can withstand a thermal process of 650°C.

The metal-induced unidirectional lateral crystallization thin film transistor device is characterized in that the thickness of the LTO cover layer is 100nm-500nm.

The metal-induced unidirectional lateral crystallization thin film transistor device is characterized in that the induced metal is nickel, and the continuous or discontinuous nickel-containing induction layer.

The metal-induced unidirectional lateral crystallization thin film transistor device is characterized in that the channel of the metal-induced unidirectional lateral crystallization thin film transistor and the extensions on both sides are polysilicon materials of metal-induced unidirectional crystallization (MIUC) The source and drain electrodes on one side are metal-induced crystallization (MIC) polysilicon material, and the source and drain electrodes on the other side are metal-induced lateral crystallization (MILC) polysilicon material, and the thickness of the polysilicon material is 30nm-300nm.

The metal-induced unidirectional lateral crystallization thin film transistor device is characterized in that the gate insulating layer material of the metal-induced unidirectional lateral crystallization thin film transistor is a low-temperature silicon oxide material obtained by PECVD or LPCVD with a thickness of 30nm -300nm.

The metal-induced unidirectional lateral crystallization thin film transistor device is characterized in that the gate electrode of the metal-induced unidirectional lateral crystallization thin film transistor is polysilicon or a high-temperature metal gate, and the thickness of the electrode is 100nm-300nm.

The method for preparing a metal-induced unidirectional lateral crystallization thin film transistor device of the present invention is characterized in that it comprises the following steps:

1) Deposit a silicon nitride or LTO transition layer on a large-area transparent substrate to prevent the diffusion of metal impurities in the substrate to the active layer; use PECVD, LPCVD and other methods to form a large-area amorphous silicon film;

2) Depositing an LTO film on the amorphous silicon film, and forming a rectangular LTO mask pattern at an appropriate position;

3) Using nickel solution, vacuum evaporation, ion implantation and other methods to form an ultra-thin induced film of metallic nickel;

4) Under nitrogen, anneal at 450-600°C, and the completed MIC and the periphery under the cover layer undergo a lateral crystallization MILC process that advances to the interior of the pattern;

5) Removal of nickel residues and LTO of the cover layer;

6) Photoetching the polysilicon TFT active island pattern, the channel region of the TFT is formed in the MIUC region of the surrounding crystallized MILC region, and the channel carrier transport direction is parallel to the long crystal grains of the MIUC. The source-drain area is composed of MIC and MILC, and the extended area of source-drain can be used as storage capacitor electrode and display pixel electrode;

7) Depositing the gate insulating layer of the polysilicon TFT;

8) Depositing the gate electrode layer of the polysilicon TFT, and photoetching out the gate electrode pattern;

9) The method of self-aligned ion implantation is adopted, and the dopant is activated at a temperature of 550° C. to form the source-drain electrodes and the extended region of the polysilicon TFT.

10) Depositing an insulating layer between LTO electrodes, and photoetching a contact hole.

11) Sputter metal electrodes, photolithographically pattern electrodes, and complete the alloying process.

The present invention uses the technology of preparing metal-induced single-direction lateral crystallization thin film transistors on surrounding crystallized polysilicon islands, which can effectively avoid the problem of too long crystallization time in the conventional MIUC polysilicon TFT preparation process, and can effectively reduce the crystallization time , to reduce the crystallization time by 3-5 times. The channel of the polysilicon TFT device is MIUC material, and the performance of the device is the same as that of the conventional MIUC polysilicon TFT.

The present invention adopts the metal induction technology to prepare thin film transistors, and the required equipment is cheaper than that of ELA. A conventional heating furnace can complete the crystallization process of the material, and other preparation processes are conventional processes. Among various metal-induced thin film transistor fabrication technologies, metal-induced unidirectional lateral crystallization thin film transistors have the best characteristics, because there is no grain boundary between vertical crystallization and lateral crystallization in the channel of this kind of thin film transistors, and there is no The colliding grain boundaries of the laterally crystallized regions in different directions, moreover, the content of residual nickel in the channel is comparatively lowest. However, in the usual MIUC-TFT technology, the induction hole should be opened on the outer edge of the source and drain electrodes, so the entire crystallization length should include the source and drain electrodes and the channel interval, so the crystallization time is too long. For example, the length of the crystallization region of a 5 micron MIUC polysilicon TFT is 37 microns, the crystallization rate at 550°C is 4-5 microns/hour, and the crystallization time is about 10 hours. In our current technology, a rectangular LTO pattern is designed to cover the amorphous silicon film, and an appropriate amount of induced nickel is deposited on the surface of the amorphous silicon. During the subsequent annealing process, MILC polysilicon will start to form around the covering pattern, and Pushing toward the center of the pattern, the polysilicon islands of the MIPC are finally formed. The region without a large grain boundary of the polysilicon island is selected as the channel region of the thin film transistor, and an MIUC polysilicon TFT can be formed. The adoption of this process can effectively reduce the crystallization time. For example, for a 5-micron polysilicon TFT, the width of the channel is 5 microns. Considering the tolerance of 4 microns on each side, the length of the MIUC interval required for device fabrication is 9 microns. For 550 ° C, 4-5 microns/hour Crystallization rate, crystallization time of 2-3 hours can meet the requirements. The reduction of crystallization time can effectively reduce the impact of substrate shrinkage and metal ion diffusion in the substrate, and improve the production yield. This technology is suitable for the preparation of low-temperature polysilicon circuits, active addressing substrates for low-temperature polysilicon displays, and the preparation of various microelectronic and optoelectronic products such as area array image sensors, and has important industrial application value.

The invention is suitable for the requirements of preparing active substrates for displays, polysilicon TFT circuits and area array scanners on glass substrates.

The above detailed description is a specific description of the present invention, and any equivalent implementation or modification that does not deviate from the spirit of the present invention falls within the scope of the present invention.

Description of drawings

Figure 1: A schematic cross-sectional view of a stacked structure forming a barrier layer, an amorphous silicon layer, and an LTO mask layer on a glass substrate.

Figure 2: Schematic diagram of opening the induction port and depositing metal nickel during the preparation process of the conventional MIUC polysilicon TFT.

Figure 3: Schematic diagram of the polysilicon formation process for the active layer of a conventional MIUC polysilicon TFT.

Fig. 4: In the new process of the present invention, the schematic diagram of the LTO cover layer in the selected crystallization interval.

Fig. 5: Schematic diagram of the formation process of the active layer of the transistor in the MIUC polysilicon TFT process of the present invention.

FIG. 6 : A correlation diagram between each crystallization region and the channel position of a polysilicon TFT formed in the process of the present invention.

Fig. 7: Schematic diagram of the polysilicon active layer of the TFT in the present invention.

Figure 8: Schematic diagram of the preparation process of ion implantation to form source and drain electrodes after the gate electrode is formed.

Fig. 9: A novel MIUC polysilicon TFT prepared by the present invention.

Detailed ways

Example

The present invention is described in detail as follows with reference to accompanying drawing:

As shown in the figure, the present invention adopts a method of preparing a metal-induced single-direction lateral crystallization thin film transistor on a transparent glass substrate on a peripheral crystallized polysilicon island, which ensures that the device has the same performance as the conventional MIUC polysilicon TFT On the basis of excellent performance, the crystallization time is obviously reduced.

As shown in Figure 1, the substrate material for preparing polysilicon devices is transparent substrate glass 101. In order to prevent impurities in the glass substrate from diffusing into the active layer during the thermal process of preparation, silicon nitride is deposited on the glass substrate and LTO mixed layer 102. The precursor for preparing the polysilicon material—the dehydrogenated amorphous silicon material layer 103 is deposited on the mixed barrier layer 102 of silicon nitride and LTO. An LTO capping layer 104 is deposited on the amorphous silicon layer for forming a crystallization selection region pattern.

FIG. 2 is a schematic diagram of opening an induction port and depositing metal nickel during the crystallization process of a conventional MIUC polysilicon TFT. In the conventional MIUC polysilicon TFT active island crystallization process, the induction opening 105 is first formed on the LTO cover layer 104 through photolithography and etching processes, and then a very thin layer of metal nickel 106 is deposited on it. This layer of thin metal Nickel is deposited directly on the selected amorphous silicon film at the induction port.

FIG. 3 is a schematic diagram of the formation process of polysilicon in the active layer of a conventional MIUC polysilicon TFT. During the annealing process under the nitrogen atmosphere, a discontinuous MIC crystallization region 105 is first formed in the amorphous silicon region with a small amount of nickel adhered under the induction opening, and then a continuous MIC crystallization region 105 is formed under the LTO coverage interval on both sides of the MIC crystallization region 105. MILC interval. The size of the MILC is determined by the active island length of the MIUC polysilicon TFT to be prepared. Taking a TFT with a channel length of 5 microns as an example, the entire active island, including the source and drain electrodes, the channel, and the margins on both sides of the channel are designed with a total distance of 37 microns, which is marked as "L1" in the figure.

Figure 4 shows the novel crystallization process designed by the present invention. According to the channel length and width requirements of the polysilicon TFT, a rectangular mask pattern 108 of a certain size is formed in the selected area of the LTO cover layer, and then the solution method is adopted. A small amount of nickel is adhered to the surface of the amorphous silicon film outside the mask pattern.

FIG. 5 is a schematic diagram of the formation process of the transistor active layer in the MIUC polysilicon TFT process of the present invention. During the annealing process, MIC polysilicon 110 is formed in the amorphous silicon regions not covered by the LTO pattern 108 where nickel adheres. In the amorphous silicon region covered by the LTO pattern 108, four MIUC regions as shown in FIG. 6 are formed from the periphery of the masked region 108 to the middle. The MILCs that start to crystallize from the adjacent vertical sides stop crystallization after they meet, so the crystallization at an angle close to 45 degrees collides with the grain boundary. The MILCs on opposite sides collide with each other to form collision grain boundaries perpendicular to the crystallization advancing direction. We call the four MIUC polysilicon regions of the LTO mask region 108 MIPC regions 111 . The distance of opposite crystallization is two "L2".

FIG. 6 is a schematic diagram of the relationship and relative position between the design size of the MIPC and the channel size of the TFT. The overlapping region of the gate electrode 117 of the polysilicon TFT and the active island is the channel interval 113, and the channel interval 113 is set in the larger one of the above four MIUC intervals, and the edge of the MIPC interval 111 and the pair of the MILC Hit the grain boundary, and set it outside the channel region 113; in the position adjacent to it, the polysilicon source and drain electrodes are formed at the left and right ends of the channel, such as the extended region of the polysilicon source and drain region shown on the right, can also be used to form storage capacitor electrode or display pixel electrode 115 . As long as the MIUC crosses the channel and the two colliding grain boundaries and the channel edge, it can meet the crystallization requirements of the device. Therefore, compared with the usual MIUC polysilicon TFT, the crystallization time is significantly shortened. time. Taking a TFT with a channel length of 5 microns as an example, the left side of the TFT channel plus a 4 micron margin is aligned with one long side of the MIPC, and the 4 micron margin beyond the right side of the channel is aligned with the colliding grain boundary of the bidirectional MILC. Therefore L2 includes the channel length of 5 microns and the left and right side margins of 8 microns, for a total of 13 microns. The width of the used mask pattern is 26 microns. When the MILC crystallization process occurs from all sides, it occurs simultaneously from the left and right directions on the cross section shown in Figure 4. The MILC crystallization interval on each side is L2=13 microns, which is different from conventional MIUC polycrystalline Compared with the TFT channel L1=33 microns, the length (time) ratio required for crystallization is 13/37=35%.

7 shows the TFT device active island pattern of the present invention, including the left MIC source and drain region 112, the middle MIUC channel region 113, the right MILC source and drain region 114, MIC capacitor electrodes and display pixel electrodes 115. The various parts of the device are optimally combined.

FIG. 8 is a schematic diagram of the formation process of the TFT device. A PECVD or LPCVD low-temperature gate insulating layer 116 is deposited on the polysilicon active island, and then a gate electrode 117 is formed thereon. The source and drain of the polysilicon TFT and the source and drain extension regions are formed by self-alignment ion implantation 118 .

What Fig. 9 shows is the polysilicon TFT device prepared by adopting the technology of the present invention, after completing the process described in Fig. 8, deposit the LTO electrode isolation layer 119, finish the activation process of implanted ions afterwards, open the contact hole, form the metal electrode 120, After alloying, the entire polysilicon TFT preparation process is completed.

The specific preparation method is:

1) On the transparent glass substrate 101, a mixed layer of 300nm low-temperature silicon nitride and 100nm low-temperature silicon oxide is deposited at 350°C by plasma chemical vapor deposition (PECVD) as the glass substrate impurity barrier layer and substrate material and transition layer 102 of silicon membrane material.

2) On the above-mentioned substrate on which the transition layer has been deposited, an amorphous silicon layer 103 of 30nm-200nm is deposited by PECVD or LPCVD at 350-400°C or 550°C respectively.

3) Afterwards, a 100nm-300nm LTO layer is deposited on the amorphous silicon.

4) Form the photolithographic pattern of the LTO cover layer for selective crystallization, which is a rectangle, and the position of one side of the two opposite long sides is at 4 microns outside the TFT channel (relative to the 5 micron TFT), and the position of the other side is the distance Twice the size of the channel on the opposite side plus the size of the margin on both sides makes the collision grain boundaries of the facing MILC crystallized from both sides exactly distributed about 4 microns outside the channel. The distance between the two narrow sides of the rectangle is greater than the sum of the width of the channel and the length of the narrow sides. The LTO pattern 108 is etched by BOE. An ultra-thin nickel layer 109 is formed on the surface of the amorphous silicon outside the masking area by means of electroless plating with a nickel salt solution.

5) After several hours of annealing in a nitrogen atmosphere at 500-590° C., MILC polysilicon material 111 will be formed in the area covered by LTO, and MIC polysilicon material 110 will be formed in the area not covered by LTO.

6) Photoetching TFT active island patterns, forming a MILUC-TFT channel 113 and a source-drain electrode region 114 on one side in the MILC polysilicon region, and forming a source-drain electrode region 112 on the other side and capacitance and display images in the MIC polysilicon region The element electrode interval 115 .

7) Deposit the gate insulating layer 116 of the LTO polysilicon TFT of 50nm-100nm, form a polysilicon or metal gate electrode pattern 117 with a thickness of 200nm-300nm, automatically inject the TFT source-drain electrode dopant 118 of 4E15/ ^cm2 , for N-type TFT implants phosphorus and arsenic with corresponding energy, and P-type TFT injects boron with corresponding energy. Afterwards, after a doping activation process at 550° C. for 30 minutes, the source and drain electrodes 112 and 114 of the polysilicon TFT are formed.

6) Deposit a 500 nm LTO electrode insulating layer 119 by using LPCVD method. Photoetching and processing the contact hole pattern, sputtering a 500nm silicon aluminum alloy layer, and processing it into a metal electrode 120 . Forming gas annealing (FGA) completes the alloying process of the metal.

The turn-on voltage of the thin-film transistor prepared by this invention is lower than 10 volts, the on-off current ratio is higher than 10 ⁶ , and the carrier mobility is higher than 50 cm ² /Vs. performance is comparable.

Claims (10)

1. metal inducement single direction transverse crystallization thin film transistor device, it is characterized in that described metal inducement single direction transverse crystallization thin film transistor is formed on the large-area transparent substrate, described metal inducement single direction transverse crystallization thin film transistor comprises:

The polysilicon island of large-area transparent substrate upper periphery crystallization; The amorphous silicon membrane of the predecessor that described polysilicon forms for forming with low-pressure chemical vapor deposition, plasma reinforced chemical vapour deposition or sputtering method;

Be deposited on the transition zone on the described substrate, amorphous silicon membrane is deposited on the transition zone; Described transition zone is silicon nitride or cryogenic oxidation silicon transition zone;

Be deposited on the layer of covering on the described amorphous silicon membrane; The described layer of covering is cryogenic oxidation silicon, and cryogenic oxidation silicon is covered layer is become rectangle by photoetching corrosion covered area;

Induce on the amorphous silicon surfaces of metal level outside the covered area;

Through the metal inducing crystallization polycrystalline silicon that the amorphous silicon outside the cryogenic oxidation silicon covered area behind the thermal annealing becomes, be used to prepare capacitance electrode and display element electrode; Amorphous silicon below the figure of cryogenic oxidation silicon covered area, around the figure of covered area, begin to form between four metal inducement single direction transverse crystallization multi-crystal silicon areas simultaneously to the centre, also be referred to as metal inducement periphery crystallization region, just stop crystallization after meeting from the metal-induced lateral crystallization forward position that adjacent vertical edges begins crystallization, formation is near 45 degree angle crystallization collision crystal boundaries, the metal-induced lateral crystallization of opposite face collides relatively, forms the collision crystal boundary vertical with the crystallization direction of propulsion;

The active channel of thin-film transistor selects design between four metal inducement single direction crystallization regions;

Photoetching corrosion goes out gate insulation layer and the gate electrode for preparing successively behind the active island thereon.

2. metal inducement single direction transverse crystallization thin film transistor device according to claim 1, it is characterized in that it is rectangle that described cryogenic oxidation silicon is covered layer pattern, cover the size of layer pattern and the position of polycrystalline SiTFT on the substrate connection that is closely related; Cover the head-on collision crystal boundary that long relatively long limit of figure and metal-induced lateral crystallization produced and split at the raceway groove two ends, and with raceway groove limit 3-5 micron apart; With respect to 5 micron film transistors, 4 microns places outside the TFT raceway groove, position on the one side in two long relatively long limits, the position of another side is for adding bilateral spacious and comfortable size apart from the raceway groove of opposite side twice, makes from the collision crystal boundary of the subtend metal-induced lateral crystallization of bilateral crystallization and is distributed in 4 microns of raceway groove outsides just; The distance on rectangular two narrow limits be greater than the width of raceway groove and the two narrow limit length of sides and.

3. metal inducement single direction transverse crystallization thin film transistor device according to claim 1 is characterized in that described transparent substrates is the glass substrate that can tolerate 650 ℃ of thermal processs.

4. metal inducement single direction transverse crystallization thin film transistor device according to claim 1 is characterized in that it is 100nm-500nm that described cryogenic oxidation silicon is covered the thickness of layer.

5. metal inducement single direction transverse crystallization thin film transistor device according to claim 1, it is characterized in that the described metal of inducing is a nickel, the continuous or discrete nickeliferous inducing layer that adopts vacuum evaporation, ion injection or nickel salt solution method for non-electric plating to obtain.

6. metal inducement single direction transverse crystallization thin film transistor device according to claim 1, it is characterized in that being the polycrystalline silicon material of metal inducement single direction crystallization between the raceway groove of described metal inducement single direction transverse crystallization thin film transistor and both sides zones of extensibility, the source-drain electrode of one side is the metal inducing crystallization polycrystalline silicon material, the source-drain electrode of opposite side is the metal-induced lateral crystallization polycrystalline silicon material, and the thickness of polycrystalline silicon material is 30nm-300nm.

7. metal inducement single direction transverse crystallization thin film transistor device according to claim 1, it is characterized in that described metal inducement single direction transverse crystallization thin film transistor gate insulation layer material is the low-temperature oxidation silicon materials, adopt the method for plasma reinforced chemical vapour deposition or low-pressure chemical vapor deposition to obtain, thickness is 30nm-300nm.

8. metal inducement single direction transverse crystallization thin film transistor device according to claim 1, the gate electrode that it is characterized in that described metal inducement single direction transverse crystallization thin film transistor is polysilicon or high-temperature metal grid, and the thickness of electrode is 100nm-300nm.

9. the application of the described metal inducement single direction transverse crystallization thin film transistor device of claim 1 is characterized in that it is used to make flat panel displays, polysilicon circuit and large tracts of land picture matrix scanner.

10. the preparation method of a metal inducement single direction transverse crystallization thin film transistor device is characterized in that it comprises the steps:

1) the excessive layer of deposited silicon nitride or cryogenic oxidation silicon on the large-area transparent substrate is used for stoping the metal impurities in the substrate to spread to active layer; Adopt low-pressure chemical vapor deposition, plasma reinforced chemical vapour deposition or sputtering method to form large-area amorphous silicon membrane;

2) deposition low-temperature oxidation silicon thin film on amorphous silicon membrane, and go up the rectangular cryogenic oxidation silicon of formation in position and cover layer pattern;

3) adopt nickel solution, vacuum evaporation or ion injection method, form the ultra-thin film of inducing of metallic nickel;

4) under nitrogen, 450-600 ℃ of annealing, metal-induced crystallization of finishing and the periphery of covering under the layer take place to the inner transverse crystallization process that advances of figure;

5) residual substance of removal nickel and the cryogenic oxidation silicon of covering layer;

6) make the active island of polycrystalline SiTFT figure by lithography, the channel region of thin-film transistor is formed on the metal inducement single direction transverse crystallization interval of metal inducement periphery crystallization polysilicon, and it is parallel with the microscler crystal grain of the crystal of metal inducement single direction transverse crystallization to make channel carrier transport direction; Form by metal-induced crystallization and metal-induced lateral crystallization polysilicon between source-drain area, can be used as storage capacitors electrode and displayer pixel electrode between the expansion area that leak in the source;

7) gate insulation layer of deposited polycrystalline silicon thin film transistor;

8) gate electrode layer of deposited polycrystalline silicon thin film transistor, and make gate electrode figure by lithography;

9) method that adopts the autoregistration ion to inject, and under 550 ℃ of temperature, activate dopant, form between the source-drain electrode and expansion area of polycrystalline SiTFT.

10) insulating barrier between deposition low-temperature oxidation silicon electrode, and make contact hole by lithography.

11) splash-proofing sputtering metal electrode, the photoetching electrode pattern, and finish alloying process.

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