CN100389451C - Pixel structure and overhauling method and manufacturing method thereof - Google Patents

Abstract

A pixel structure comprises at least two scanning lines and at least two data lines, wherein the scanning lines and the data lines are intersected with each other, and at least one interval is formed in the inner periphery of the scanning lines and the data lines. The pixel structure further includes a thin film transistor, a protective layer, a defect detection pattern, and a pixel electrode. The pixel electrode is arranged on the protective layer and is electrically connected with the thin film transistor through the opening. The defect detecting pattern is disposed in the region for detecting whether there is a residue formed by other conductive or semiconductor material below the defect detecting pattern.

Description

A pixel structure, repair method and manufacturing method thereof

technical field

The present invention relates to a pixel structure, in particular to a pixel structure capable of conveniently detecting whether there is excess conductive or semiconductor material remaining.

Background technique

Generally speaking, a liquid crystal panel mainly includes a filter substrate, an array substrate, and a liquid crystal material layer filled between the filter substrate and the array substrate. By controlling the electric field between the array substrate and the filter substrate, the liquid crystal molecules in the liquid crystal material layer are twisted, and the traveling direction of the light in the liquid crystal panel is changed, resulting in differences in the brightness of the light passing through the filter substrate, thereby displaying images .

Please refer to FIG. 1 , which is a schematic top view of an array substrate 1 in a liquid crystal display.

A plurality of scan lines 10 and a plurality of data lines 11 are disposed on the array substrate 1 . The scan lines 10 and the data lines 11 are interlaced in rows and columns, and the array substrate 1 is divided into a plurality of pixel structures 12 , and each pixel structure is provided with a thin film transistor 121 and a pixel electrode 122 . Wherein, the thin film transistor 121 is a three-terminal switching element, and is electrically connected to the scan line 10 , the data line 11 and the pixel electrode 122 at the same time. The electrical signal input from the scan line 10 can be used to turn on or turn off the thin film transistor 121 to control the voltage signal transmitted from the data line 11 to the pixel electrode 122 .

It is worth noting that the aforementioned scan lines 10, data lines 11, thin film transistors 121, pixel electrodes 122 and other components are all formed in sequence by depositing and etching various required materials in a preset pattern. on the array substrate 1. However, in the manufacturing process of these devices, sometimes the material remains outside the preset pattern area, resulting in different types of defects.

For example, as shown in FIG. 2 , it is a schematic diagram of a pixel structure 12 . Wherein, when manufacturing the thin film transistor 121, amorphous silicon is deposited on its gate 1211, as the channel layer 1212 of the thin film transistor, if amorphous silicon is deposited outside the predetermined position, it will form in the pixel structure. Residue 13 as shown in Figure 2.

If the position of the residue is at the position across the data line and the pixel electrode, the residue 13 and the pixel electrode 122 above it will generate a coupling capacitance, then when the array substrate 1 is in operation, the scanning line 10 and the data line 11 will both input voltage , the voltage of the data line 11 will affect the normal operation of the pixel electrode 122 through the coupling capacitance generated by the residue 13 and the pixel electrode 122 above it, resulting in point defects.

As shown in FIG. 3 , it is a schematic diagram of another pixel structure. Wherein, when a metal layer is deposited on the array substrate to form a plurality of scan lines 10 , if any metal is deposited outside the predetermined position, residues 13 will be formed in the pixel structure, such as shown in FIG. 3 . If the residue 13 is just connected between two scan lines 10 , it will inevitably cause a short circuit between the two scan lines 10 and cause a line defect.

Therefore, the aforementioned residues are often one of the main causes of defects in liquid crystal panels. In the current testing method, a voltage is applied to the scanning line and the data line, and the potential value of each pixel electrode is measured to compare whether a certain pixel electrode has a particularly abnormal potential value. However, this testing method has great disadvantages to be overcome. In the case of the coupling capacitance in the aforementioned pixel structure, the coupling capacitance has little influence on the potential value of the pixel electrode. In other words, it is difficult to sensitively detect the potential value difference between the pixel electrode with coupling capacitance and the pixel electrode without coupling capacitance, and it is impossible to judge whether there is redundant residue in the pixel structure causing the coupling capacitance.

If there are residues in the aforementioned pixel structure that short-circuit the two scanning lines, even though the voltage is applied to the scanning line and the data line, if a short circuit occurs between the two scanning lines, the sensor connected to the scanning line will be connected to the scanning line. The potential values of the pixel electrodes of all will be abnormal values, but the potential values of these pixel electrodes are not very different from each other. In other words, although it can be determined that a short circuit occurs between the two scan lines, it is difficult to determine where the residue in the pixel electrode causes the short circuit between the two scan lines.

Therefore, for the designers or manufacturers in this field, how to effectively detect the redundant residues on the array substrate to overcome the defects caused by the residues has become a direction that relevant people are working on.

Contents of the invention

Therefore, the present invention proposes a pixel structure, which can facilitate testing whether there is residue and the location of the residue.

The pixel structure of the present invention includes at least two scan lines and at least two data lines, the scan lines and the data lines intersect with each other, and at least one interval is formed within the scan lines and the data lines.

Moreover, the pixel structure of the present invention further includes a thin film transistor, a protection layer, a defect detection pattern and a pixel electrode.

The thin film transistor is arranged in the section and is electrically connected to one of the two scanning lines and one of the two data lines.

At least one protective layer is disposed on the array substrate and covers the scanning lines, data lines and thin film transistors to protect these elements from pollution or damage. And the protection layer has at least one opening.

At least one defect detecting pattern (defect detecting pattern) is arranged in the section for detecting whether there are other conductive or semiconducting material residues below it.

At least one pixel electrode is disposed on the protective layer, and is electrically connected to the thin film transistor through the opening.

By setting the defect detection pattern, the pixel electrode can be in contact with the possible residues under the defect detection pattern. If the potential value of the pixel electrode touches the residue during the voltage test, the measured potential value will be affected by the residue and produce abnormalities, and it can be determined that there is a residue in the pixel structure.

In order to further reveal the advantages and spirit of the present invention, a detailed description is given below with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a schematic top view of an array substrate in a liquid crystal display.

FIG. 2 is a schematic diagram of a pixel structure.

FIG. 3 is a schematic diagram of another pixel structure.

FIG. 4A is a schematic top view of a preferred embodiment of the pixel structure of the present invention.

Fig. 4B is a schematic cross-sectional view along the section line A-A' shown in Fig. 4A.

4C is a schematic cross-sectional view of a pixel structure with residues on the surface of the insulating layer.

4D is a schematic cross-sectional view of a pixel structure with residues on the surface of the array substrate.

5A to 5F are different implementations of defect detection patterns in the pixel structure of the present invention.

FIG. 6 is a schematic flowchart of the detection method for the aforementioned pixel structure.

FIG. 7A to FIG. 7C are schematic diagrams of the pixel structure of the present invention, which are repaired when residues occur between layers of films.

FIG. 8 is a schematic flowchart of the manufacturing method of the aforementioned pixel structure.

simple notation

1 array substrate 26 thin film transistors

2-pixel structure 27 protective layers

3-pixel structure 28 defect detection patterns

10 scan lines 29 pixel electrodes

11 data line 30 residues

12-pixel structure 261 gates

121 thin film transistor 262 insulating layer

122 pixel electrodes 263 channel layers

13 Residues 264 Sources

20 array substrates 265 drains

21 scan lines 271 openings

22 data lines 1211 grid

23 intervals 1212 channel layer

24 Light Masking Patterns W1 Cutting Path

25 public lines W2 cutting path

Detailed ways

Please refer to FIG. 4A and FIG. 4B , which are schematic top views of a preferred embodiment of the pixel structure 2 of the present invention, and a schematic cross-sectional view along the section line A-A'.

As shown in FIG. 4A, a plurality of scanning lines 21 and a plurality of data lines 22 are arranged on the array substrate 20. The rows and columns of the scanning lines 21 are interlaced with the data lines 22, and a plurality of pixel structures 2 can be separated, each The pixel structure 2 is divided by two adjacent scan lines 21 and two adjacent data lines 22 .

In other words, the pixel structure 2 of the present invention includes at least two scan lines 21 and at least two data lines 22, these scan lines 21 and data lines 22 intersect with each other, and in the inner periphery of these scan lines 21 and data lines 22, At least one interval 23 is formed.

In a preferred embodiment, the pixel structure 2 further includes at least two light-shielding patterns 24 and a common line 25 . Each light-shielding pattern 24 partially overlaps with the pixel electrode, and is not limited to where each light-shielding pattern 24 is located in the interval, and a preferred embodiment of the present invention, for example, can be: each light-shielding pattern 24 is parallel Each data line 22 is used to reduce light leakage in the pixel structure 2 . In other different implementations, it can also be parallel to each scanning line 21 ; or, the pixel structure 2 further includes at least three light-shielding patterns 24 and a common line 25 . Two of the light-shielding patterns 24 are parallel to the data lines 22 , and the other light-shielding pattern is parallel to one of the scanning lines 21 . The common line 25 is disposed between the two scan lines 22 and can be used as a storage capacitor in the pixel structure 2 .

Please also refer to FIG. 4B. Moreover, the pixel structure 2 of the present invention further includes a thin film transistor 26 , a protection layer 27 , a defect detection pattern 28 and a pixel electrode 29 .

The thin film transistor 26 is disposed in the region 23. In this embodiment, a back-channel etched (BCE) structure is used as an illustration. In other embodiments, it may also be an etch stop layer structure ( etched-stopper), bottom-gate structure (bottom-gate), inverted thin-film transistor structure (inversed-TFT) or top-gate structure (top-gate) are all applicable. Of course, the material of the thin-film transistor structure can be A group formed by amorphous silicon, microcrystalline silicon, polycrystalline silicon or any combination thereof. And the thin film transistor can be an N-type transistor (N-type), a P-type transistor (P-type) or a mixed type transistor (such as N-type+P-type). The thin film transistor is electrically connected to one of the two scan lines and one of the two data lines.

The thin film transistor 26 has a gate 261 , an insulating layer 262 , a channel layer 263 , a source 264 and a drain 265 . The fabrication method can simultaneously define the scanning lines 21 , the light shielding patterns 24 , the common lines 25 and the gates 261 of the thin film transistors while depositing the first metal layer on the surface of the array substrate. And cover the insulating layer 262 on the scan line 21, the light-shielding pattern 24, the common line 25 and the thin film transistor gate 261, this insulating layer 262 can be made of at least one inorganic dielectric material (such as: silicon oxide (SixOy), silicon nitride (SixNz, silicon oxynitride (SixOyNz)), or at least one organic material (such as photoresist, polyester or other polymers) or a mixed layer formed by any combination of the above.

And a semiconductor layer (such as an amorphous silicon layer and a doped layer) is formed on the insulating layer 262 to be configured as a channel layer 263 of a thin film transistor. A second metal layer is then deposited on the channel layer 262 to define the data line 22 and the source 264 and the drain 265 of the thin film transistor 26 . Alternatively, when depositing the first metal layer on the surface of the array substrate, the scan lines 21 , the common lines 25 and the gates 261 of the thin film transistors can be defined at the same time. And cover the insulating layer 262 above the scan line 21 , the common line 25 and the TFT gate 261 . And a semiconductor layer (such as an amorphous silicon layer and a doped layer) is formed on the insulating layer 262 to be configured as a channel layer 263 of a thin film transistor. A second metal layer is then deposited on the channel layer 262 to define the data line 22 and the source 264 , the drain 265 and the light shielding pattern 24 of the thin film transistor 26 .

The protection layer 27 is disposed on the array substrate and covers the scan lines 21 , the data lines 22 and the thin film transistors 26 to protect these elements from pollution or damage. Alternatively, the protection layer 27 is disposed on the array substrate and covers the scan lines 21 , the data lines 22 , the thin film transistors 26 and the light shielding patterns 24 to protect these elements from contamination or damage. And the protection layer 27 has at least one opening 271 . Wherein, the protection layer can be made of at least one inorganic dielectric material (such as: silicon oxide (SixOy), silicon nitride (SixNz), silicon oxynitride (SixOyNz)), or at least one organic material (such as photoresist, poly ester (polyester) or other polymers) or a mixed layer formed by any combination of the above.

A defect detecting pattern 28 (defect detecting pattern) is disposed in the section 23 for detecting whether there are other conductive or semiconducting residues remaining thereunder. As shown in FIGS. 4A-4D , it is a hole arranged in the section 23 . It is further explained that the hole is located at the corner of the section 23 in this embodiment, but it is not limited to be set at the corner, it can be set at any position in the section 23, such as the middle area of the section 23 , or a position adjacent to the thin film transistor 26 or other positions other than corners. That is to say, as long as the functions described in the embodiments of the present invention can be realized, the positions where the defect detection patterns are disposed in the intervals are not limited to the examples exemplified in this embodiment.

The pixel electrode 29 is disposed on the passivation layer 27 and is electrically connected to the thin film transistor 26 through the opening 271 . Furthermore, the gate 261 is electrically connected to one of the two scanning lines 21, the source 264 is electrically connected to one of the two data lines 22, and the pixel electrode 29 is electrically connected to the drain of the thin film transistor 26 through the opening 271. 265. Moreover, at least a part of the pixel electrode 29 covers the defect detection pattern 28 , and may completely cover the defect detection pattern 28 . Among them, the pixel electrode can be made of metal (such as molybdenum, aluminum, copper, silver, chromium, ... etc.), metal alloy (such as aluminum molybdenum alloy, aluminum neodymium alloy, molybdenum neodymium alloy, ... etc.), metal oxide (such as indium tin oxide, indium zinc oxide, cadmium tin oxide, etc.) or a mixed layer formed by any combination of the above.

In a preferred embodiment, in order to completely detect whether there are residues on the surface of the array substrate, the protective layer 27 and the insulating layer 262 may be dug through the protective layer 27 and the insulating layer 262 by etching when forming the aforementioned defect detection pattern 28 .

Taking the one shown in FIG. 4B as an example, if no residue remains, after the defect detection pattern 28 is formed by digging through the protective layer 27 and the insulating layer 262, the defect detection pattern 28 will expose the array substrate 20 located under the insulating layer 262. . And when the pixel electrode 29 is subsequently formed on the protective layer 27 , the pixel electrode 29 will pass through the defect detection pattern 28 and contact the surface of the array substrate 20 , and its potential value will not be affected.

As shown in FIG. 4C , when the defect detection pattern 28 is formed by digging through the protective layer 27 and the insulating layer 262 . If there are residues 30 made of conductive or semiconductor materials (such as amorphous silicon residues or residues made of the second metal layer) on the surface of the insulating layer 262 below the defect detection pattern 28, then in the digging protection After the layer 27, the surface of the residue 30 will be exposed, and the insulating layer 262 cannot be dug further. When the pixel electrode 29 is formed on the protective layer 27 , the pixel electrode 29 will pass through the defect detection pattern 28 and contact the aforementioned residue 30 to form an electrical connection. When a voltage is applied to the pixel structure, if the residue has a voltage different from that of the pixel electrode or has capacitive coupling with other structures with a different voltage, the pixel electrode 29 will be affected by the residue 30, causing Its potential value is abnormal.

And if, as shown in FIG. 4D , in the pixel structure, there are only residues 30 (such as residues formed by the first metal layer) on the surface of the array substrate 20, after the protective layer 27 and the insulating layer 262 are dug through by etching, , the defect detection pattern 28 will expose the surface of the residue 30 . When the pixel electrode 29 is formed on the protective layer 27, the pixel electrode 29 will be in contact with the aforementioned residue 30, if the residue has a voltage different from the pixel electrode or has capacitance with other structures with a different voltage coupling, its potential value will be affected and anomalies will occur. (The pixel electrode in FIG. 4D needs to be in contact with the residue).

Of course, in other embodiments, only the residue above the insulating layer 262 may be detected, that is, only the protective layer 27 is dug through, so as to form the required defect detection pattern 28 . If there are residues (such as amorphous silicon residues, or residues formed by the second metal layer) above the insulating layer 262, then when the pixel electrode 29 is formed on the protective layer, the pixel electrode 29 will be in contact with the aforementioned contact with residues and be affected.

It should be further explained that the pattern and location of the aforementioned defect detection pattern can be determined according to design requirements. As shown in FIG. 4A , a hole disposed at a corner of a section is used as an illustration. It can also be shown in FIG. 5A , the defect detection pattern 28 can be four holes, respectively located on two sides of each light shielding pattern 24 .

Alternatively, as shown in FIG. 5B , the defect detection pattern 28 may be a plurality of holes surrounding the area 23 .

Alternatively, as shown in FIG. 5C , the defect detection pattern 28 is two elongated grooves, both of which are parallel to and adjacent to one of the scanning lines 21 . Of course, the two elongated trenches can also be parallel to and adjacent to one of the data lines 22 .

Or, as shown in FIG. 5D, the defect detection pattern 28 is two elongated grooves, one of the two elongated grooves is parallel to and adjacent to one of the scanning lines 21, and the other elongated groove parallel to and adjacent to one of the data lines 22 .

Alternatively, as shown in FIG. 5E , the defect detection pattern 28 is a hole and two elongated grooves. As mentioned above, the opening position can be set at a non-corner position in the section 23, and the two elongated grooves are parallel to and adjacent to one of the scanning lines.

Alternatively, as shown in FIG. 5F, the defect detection pattern 28 is a hole and two long strip grooves, and the opening position can be set at the corner of the section 23, one of the two long strip grooves Parallel to and adjacent to one of the scan lines 21 , the other elongated groove is parallel to and adjacent to one of the data lines 22 . Of course, depending on design requirements, the defect detection pattern 28 only includes an opening and a long groove, and the long groove is parallel to and adjacent to the scan line 21 or the data line 22 .

The design of the pixel structure can be applied to the design of array substrates in various display panels such as liquid crystal panels and organic electroluminescent display panels, so as to detect whether there is residue in the pixel structure. Here, the method for repairing the pixel structure is also disclosed, which can be carried out as shown in FIG. 6 .

S11: Applying a voltage to a plurality of pixel structures. In a preferred embodiment, these pixel structures are electrically connected to the same scan line. That is, the pixel structures contained in each scanning line are detected one by one by sequentially applying a voltage to each scanning line on the array substrate.

S12: Measure the aforementioned pixel structures to obtain the potential values of the pixel electrodes of these pixel structures.

S13: Compare the potential values of the pixel electrodes of the pixel structures to obtain a pixel structure with abnormal potential values.

S14: It is determined that a conductive or semiconductor material remains in the pixel structure whose potential value is abnormal. As mentioned above, if there is a residue made of conductive or semiconductor material under the defect detection pattern, the pixel electrode in the pixel structure will be affected by the residue when the voltage is applied, so that Its potential is abnormal.

After the test of an array substrate is completed, it can be determined which pixel structures on the array substrate have residues, and further, these pixel structures can be observed with a microscope to determine the correctness of the residues in these pixel structures. position, and use a laser to ablate the electrical connection between the residue and its surrounding components, so that the potential at the measurement point is restored to normal.

To further illustrate the repair method when the pixel structure remains between the various layers of films, please refer to FIG. 7A to FIG. 7C .

As shown in FIG. 7A , when depositing a first metal layer on the array substrate to form scan lines, common lines, and light-shielding patterns, there may be redundant residues in unintended positions. In the pixel structure 2 , the residue 30 made of the first metal layer is located between the scan line 21 and the light-shielding pattern 24 , so that the two are short-circuited, and furthermore, the scan line 21 and the common line 25 are also short-circuited.

However, due to the arrangement of the defect detection pattern 28 , the pixel electrode 29 will cover the defect detection pattern 28 and be in contact with the residue 30 when the pixel electrode 29 is continuously deposited in the subsequent process. When the voltage is input to the pixel structure 2 and the pixel structure 3 at the same time, the potential value of the pixel electrode of the pixel structure 2 will be much lower than that of the pixel structure 3, and it can be determined that there is a residue in the pixel structure 2 . Then observe the pixel structure 2 with a microscope to determine the correct position of the residue, and cut off the residue 30 with the cutting paths W1 and W2 to block the connection between the residue 30 and the scanning line 21 and the common electrode 25. This creates an open circuit state and prevents the residue 30 from being energized to generate coupling capacitance.

As shown in FIG. 7B, when depositing an amorphous silicon layer to make the channel layer of the thin film transistor, there may also be redundant residues at unintended positions. As shown in the figure, in the pixel structure 2, there are The residue 30 formed by the amorphous silicon layer produces coupling capacitance.

However, by disposing the defect detection pattern 28, similarly, the pixel electrode can be brought into contact with the residue. When the voltage is input to the pixel structure 2 and the pixel structure 3 at the same time, the potential value of the pixel electrode of the pixel structure 2 will be much lower than that of the pixel structure 3, and it can be determined that there is a residue in the pixel structure 2 . Then observe the pixel structure 2 with a microscope to determine the correct position of the residue, and cut it off with a laser cutting path W1 to prevent the residue from being energized to generate coupling capacitance. Wherein, the microscope can use an infrared microscope or other types of microscopes.

And as shown in FIG. 7C, when depositing a second metal layer to make the source and drain of the data line and the thin film transistor, there may also be redundant residues at unintended positions. As shown in the figure, in the pixel In structure 2, there is a residue 30 of the second metal layer. This residue may also be connected to the data line to generate coupling capacitance. Or, as shown in this figure, its connection creates a short circuit between the two data lines 22 .

But by setting the defect detection pattern, similarly, the pixel electrode can be brought into contact with the residue. When the voltage is input to the pixel structure 2 and the pixel structure 3 at the same time, the potential value of the pixel electrode of the pixel structure 2 will be much lower than that of the pixel structure 3, and it can be determined that there is a residue in the pixel structure 2 . Then observe the pixel structure 2 with a microscope to determine the correct position of the residue, and cut off the residue with the cutting paths W1 and W2 to block the connection between the residue and the two data lines, thereby forming an open circuit state , and prevent the residue from being energized to generate coupling capacitance.

In addition, the present invention hereby discloses the manufacturing method of the aforementioned pixel structure, the steps shown in FIG. 8 include:

S21: Form at least two scan lines on an array substrate.

S22: Form at least two data lines on the array substrate and intersect the scan lines to form at least one section.

S23: forming at least one thin film transistor in the interval, and electrically connected to one of the scan lines and one of the data lines.

S24: Forming at least one protection layer on the array substrate and covering the scan lines, the data lines and the thin film transistor, and the protection layer has at least one opening.

S25: Forming at least one defect detection pattern (defect detect pattern), in the interval, for detecting whether there are other conductive or semiconductor materials remaining thereunder.

S26: forming at least one pixel electrode on the protective layer, and electrically connecting it to the thin film transistor through the opening.

To sum up, the pixel structure provided by the present invention can be determined by setting the defect detection pattern so that the pixel electrode is in contact with possible residues, and by measuring the potential values of which pixel structures are abnormal. The positions of these abnormal pixel structures on the array substrate are convenient for repairing.

The above uses different embodiments to illustrate the present invention in detail, which is not intended to limit the scope of the present invention, and those skilled in the art can understand that appropriate minor modifications will not depart from the spirit and scope of the present invention.

Claims (30)

1. dot structure comprises:

At least two sweep traces are arranged on the substrate;

At least two data lines are arranged on this substrate, and itself and those sweep trace intersects, in order to form at least one interval;

At least one thin film transistor (TFT) is arranged in this interval, and it is electrically connected on one of them of those sweep traces and one of them of those data lines;

At least one protective seam is arranged on this substrate, and covers those sweep traces, those data lines and this thin film transistor (TFT), and this protective seam has at least one opening;

At least one defect detecting pattern is arranged in this interval, exposing the surface of the layer below this defect detecting pattern, and so that detect that this defect detecting pattern below is whether residual to have unnecessary conduction or semiconductor material to exist; And

At least one pixel electrode is arranged on this protective seam, and it is electrically connected on this thin film transistor (TFT) by this opening.

2. dot structure as claimed in claim 1, wherein, this thin film transistor (TFT) has a grid, at least one insulation course, a channel layer, one source pole and a drain electrode, this grid is electrically connected on one of them of those sweep traces, and this source electrode is electrically connected on those data lines one of them, and this drain electrode is electrically connected on this pixel electrode.

3. dot structure as claimed in claim 1, wherein, this pixel electrode partly covers this defect detecting pattern.

4. dot structure as claimed in claim 1, wherein, this pixel electrode all covers this defect detecting pattern.

5. dot structure as claimed in claim 1 comprises that also at least two light cover pattern, are arranged in this interval.

6. dot structure as claimed in claim 1, wherein, this defect detecting pattern is a plurality of holes, is positioned at this interval corner.

7. dot structure as claimed in claim 1, wherein, this defect detecting pattern is a plurality of holes, is surrounded on the periphery in this interval.

8. dot structure as claimed in claim 1, wherein, this defect detecting pattern is at least two strip grooves, is parallel to and is adjacent to one of them of those sweep traces or is parallel to and is adjacent to one of them of those data lines.

9. dot structure as claimed in claim 1, wherein, this defect detecting pattern is at least two strip grooves, one of them of those strip grooves is parallel to and is adjacent to one of them of those sweep traces, and another of those strip grooves is parallel to and is adjacent to one of them of those data lines.

10. dot structure as claimed in claim 5, wherein, this defect detecting pattern is a plurality of holes, lays respectively at the both sides that this light respectively covers pattern.

11. dot structure as claimed in claim 1, wherein, this defect detecting pattern is at least one hole and at least one strip groove, wherein, this hole is arranged in any position in this interval, and this strip groove is parallel to and is adjacent to one of them of those sweep traces or is parallel to and is adjacent to one of them of those data lines.

12. dot structure as claimed in claim 1 also comprises at least one concentric line, is arranged at respectively between this sweep trace.

13. the repair method of a dot structure in order to dot structure as claimed in claim 1 is overhauled its defective position of test, comprising:

Feed voltage in a plurality of dot structures;

Measure those dot structures, with the potential value of the pixel electrode that obtains those dot structures;

The potential value that compares the pixel electrode of those dot structures is to obtain the unusual dot structure of potential value; And

Determine that this potential value is that unusual dot structure is residual conduction or semiconductor material arranged.

14. repair method as claimed in claim 13, wherein those dot structures are electrically connected on the same sweep trace.

15. repair method as claimed in claim 13 also comprises with the unusual dot structure of this potential value of microscopic examination, to determine the tram of residue in this dot structure.

16. repair method as claimed in claim 15, also comprising should conduction or being electrically connected of semiconductor material and element around it with laser ablation, so that the current potential of this measurement point recovers normal.

17. repair method as claimed in claim 15 also comprises with this conduction of laser ablation or both electrical connections of semiconductor material sweep trace adjacent thereto.

18. repair method as claimed in claim 15 also comprises with this conduction of laser ablation or both electrical connections of semiconductor material data line adjacent thereto.

19. an one pixel structure process method comprises:

On substrate, form at least two sweep traces;

On this substrate, form at least two data lines, and its and those sweep trace is crossing, in order to form at least one interval;

Form at least one thin film transistor (TFT) in this interval, it is electrically connected on one of them of those sweep traces and one of them of those data lines;

Form at least one protective seam on this substrate, it covers those sweep traces, those data lines and this thin film transistor (TFT), and this protective seam has at least one opening;

In this interval, form at least one defect detecting pattern, exposing the surface of the layer below this defect detecting pattern, and so that detect that this defect detecting pattern below is whether residual to have unnecessary conduction or semiconductor material to exist; And

Form at least one pixel electrode on this protective seam, it is electrically connected on this thin film transistor (TFT) by this opening.

20. manufacture method as claimed in claim 19, wherein, this thin film transistor (TFT) has grid, at least one insulation course, a channel layer, one source pole and a drain electrode, this grid is electrically connected on one of them of those sweep traces, and this source electrode is electrically connected on those data lines one of them, and this drain electrode is electrically connected on this pixel electrode.

21. manufacture method as claimed in claim 19, wherein, this pixel electrode partly covers this defect detecting pattern.

22. manufacture method as claimed in claim 19, wherein, this pixel electrode all covers this defect detecting pattern.

23. manufacture method as claimed in claim 19 also comprises, forms at least two light and cover pattern in this interval.

24. manufacture method as claimed in claim 19, wherein, this defect detecting pattern is a plurality of holes, is positioned at this interval corner.

25. manufacture method as claimed in claim 19, wherein, this defect detecting pattern is a plurality of holes, is surrounded on the periphery in this interval.

26. manufacture method as claimed in claim 19, wherein, this defect detecting pattern is at least two strip grooves, is parallel to and is adjacent to one of them of those sweep traces or is parallel to and is adjacent to one of them of those data lines.

27. manufacture method as claimed in claim 19, wherein, this defect detecting pattern is at least two strip grooves, one of them of those strip grooves is parallel to and is adjacent to one of them of those sweep traces, and another of those strip grooves is parallel to and is adjacent to one of them of those data lines.

28. manufacture method as claimed in claim 19, wherein, this defect detecting pattern is a plurality of holes, lays respectively at the both sides that this light respectively covers pattern.

29. manufacture method as claimed in claim 19, wherein, this defect detecting pattern is at least one hole and at least one strip groove, wherein, this hole is arranged in any position in this interval, and this strip groove is parallel to and is adjacent to one of them of those sweep traces or is parallel to and is adjacent to one of them of those data lines.

30. manufacture method as claimed in claim 19 also comprises, is respectively forming at least one concentric line between this sweep trace.

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